RealView.py (10356:198dfef33403) | RealView.py (10358:644b615fbe6a) |
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1# Copyright (c) 2009-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 170 unchanged lines hidden (view full) --- 179class RealView(Platform): 180 type = 'RealView' 181 cxx_header = "dev/arm/realview.hh" 182 system = Param.System(Parent.any, "system") 183 pci_io_base = Param.Addr(0, "Base address of PCI IO Space") 184 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 185 pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access" 186 " be compatible with the pci-generic-host or the legacy host bridge?") | 1# Copyright (c) 2009-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 170 unchanged lines hidden (view full) --- 179class RealView(Platform): 180 type = 'RealView' 181 cxx_header = "dev/arm/realview.hh" 182 system = Param.System(Parent.any, "system") 183 pci_io_base = Param.Addr(0, "Base address of PCI IO Space") 184 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 185 pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access" 186 " be compatible with the pci-generic-host or the legacy host bridge?") |
187 mem_start_addr = Param.Addr(0, "Start address of main memory") 188 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") | 187 _mem_regions = [(Addr(0), Addr('256MB'))] |
189 190 def attachPciDevices(self): 191 pass 192 193 def enableMSIX(self): 194 pass 195 196 def onChipIOClkDomain(self, clkdomain): --- 242 unchanged lines hidden (view full) --- 439 self.sci_fake.clk_domain = clkdomain 440 self.aaci_fake.clk_domain = clkdomain 441 self.mmc_fake.clk_domain = clkdomain 442 self.rtc.clk_domain = clkdomain 443 self.flash_fake.clk_domain = clkdomain 444 self.smcreg_fake.clk_domain = clkdomain 445 446class VExpress_EMM(RealView): | 188 189 def attachPciDevices(self): 190 pass 191 192 def enableMSIX(self): 193 pass 194 195 def onChipIOClkDomain(self, clkdomain): --- 242 unchanged lines hidden (view full) --- 438 self.sci_fake.clk_domain = clkdomain 439 self.aaci_fake.clk_domain = clkdomain 440 self.mmc_fake.clk_domain = clkdomain 441 self.rtc.clk_domain = clkdomain 442 self.flash_fake.clk_domain = clkdomain 443 self.smcreg_fake.clk_domain = clkdomain 444 445class VExpress_EMM(RealView): |
447 mem_start_addr = '2GB' 448 max_mem_size = '2GB' | 446 _mem_regions = [(Addr('2GB'), Addr('2GB'))] |
449 pci_cfg_base = 0x30000000 450 uart = Pl011(pio_addr=0x1c090000, int_num=37) 451 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \ 452 idreg=0x02250000, pio_addr=0x1C010000) 453 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 454 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 455 generic_timer = GenericTimer(int_num=29) 456 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') --- 140 unchanged lines hidden (view full) --- 597 self.aaci_fake.clk_domain = clkdomain 598 self.lan_fake.clk_domain = clkdomain 599 self.usb_fake.clk_domain = clkdomain 600 self.mmc_fake.clk_domain = clkdomain 601 602class VExpress_EMM64(VExpress_EMM): 603 pci_io_base = 0x2f000000 604 pci_cfg_gen_offsets = True | 447 pci_cfg_base = 0x30000000 448 uart = Pl011(pio_addr=0x1c090000, int_num=37) 449 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \ 450 idreg=0x02250000, pio_addr=0x1C010000) 451 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 452 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 453 generic_timer = GenericTimer(int_num=29) 454 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') --- 140 unchanged lines hidden (view full) --- 595 self.aaci_fake.clk_domain = clkdomain 596 self.lan_fake.clk_domain = clkdomain 597 self.usb_fake.clk_domain = clkdomain 598 self.mmc_fake.clk_domain = clkdomain 599 600class VExpress_EMM64(VExpress_EMM): 601 pci_io_base = 0x2f000000 602 pci_cfg_gen_offsets = True |
603 # Three memory regions are specified totalling 512GB 604 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 605 (Addr('512GB'), Addr('480GB'))] |
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605 def setupBootLoader(self, mem_bus, cur_sys, loc): 606 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 607 self.nvmem.port = mem_bus.master 608 cur_sys.boot_loader = loc('boot_emm.arm64') 609 cur_sys.atags_addr = 0x8000000 610 cur_sys.load_addr_mask = 0xfffffff 611 cur_sys.load_offset = 0x80000000 612 613 | 606 def setupBootLoader(self, mem_bus, cur_sys, loc): 607 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 608 self.nvmem.port = mem_bus.master 609 cur_sys.boot_loader = loc('boot_emm.arm64') 610 cur_sys.atags_addr = 0x8000000 611 cur_sys.load_addr_mask = 0xfffffff 612 cur_sys.load_offset = 0x80000000 613 614 |