| RealView.py (10353:dfebd39c48a7) | RealView.py (10356:198dfef33403) |
|---|---|
| 1# Copyright (c) 2009-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 166 unchanged lines hidden (view full) --- 175 "display") 176 amba_id = 0x00141000 177 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 178 179class RealView(Platform): 180 type = 'RealView' 181 cxx_header = "dev/arm/realview.hh" 182 system = Param.System(Parent.any, "system") | 1# Copyright (c) 2009-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 166 unchanged lines hidden (view full) --- 175 "display") 176 amba_id = 0x00141000 177 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 178 179class RealView(Platform): 180 type = 'RealView' 181 cxx_header = "dev/arm/realview.hh" 182 system = Param.System(Parent.any, "system") |
| 183 pci_io_base = Param.Addr(0, "Base address of PCI IO Space") |
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| 183 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") | 184 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") |
| 185 pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access" 186 " be compatible with the pci-generic-host or the legacy host bridge?") |
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| 184 mem_start_addr = Param.Addr(0, "Start address of main memory") 185 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 186 187 def attachPciDevices(self): 188 pass 189 190 def enableMSIX(self): 191 pass --- 400 unchanged lines hidden (view full) --- 592 self.sp810_fake.clk_domain = clkdomain 593 self.watchdog_fake.clk_domain = clkdomain 594 self.aaci_fake.clk_domain = clkdomain 595 self.lan_fake.clk_domain = clkdomain 596 self.usb_fake.clk_domain = clkdomain 597 self.mmc_fake.clk_domain = clkdomain 598 599class VExpress_EMM64(VExpress_EMM): | 187 mem_start_addr = Param.Addr(0, "Start address of main memory") 188 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 189 190 def attachPciDevices(self): 191 pass 192 193 def enableMSIX(self): 194 pass --- 400 unchanged lines hidden (view full) --- 595 self.sp810_fake.clk_domain = clkdomain 596 self.watchdog_fake.clk_domain = clkdomain 597 self.aaci_fake.clk_domain = clkdomain 598 self.lan_fake.clk_domain = clkdomain 599 self.usb_fake.clk_domain = clkdomain 600 self.mmc_fake.clk_domain = clkdomain 601 602class VExpress_EMM64(VExpress_EMM): |
| 603 pci_io_base = 0x2f000000 604 pci_cfg_gen_offsets = True |
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| 600 def setupBootLoader(self, mem_bus, cur_sys, loc): 601 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 602 self.nvmem.port = mem_bus.master 603 cur_sys.boot_loader = loc('boot_emm.arm64') 604 cur_sys.atags_addr = 0x8000000 605 cur_sys.load_addr_mask = 0xfffffff 606 cur_sys.load_offset = 0x80000000 607 608 | 605 def setupBootLoader(self, mem_bus, cur_sys, loc): 606 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 607 self.nvmem.port = mem_bus.master 608 cur_sys.boot_loader = loc('boot_emm.arm64') 609 cur_sys.atags_addr = 0x8000000 610 cur_sys.load_addr_mask = 0xfffffff 611 cur_sys.load_offset = 0x80000000 612 613 |