RealView.py (10187:7fef26827810) | RealView.py (10353:dfebd39c48a7) |
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1# Copyright (c) 2009-2013 ARM Limited | 1# Copyright (c) 2009-2014 ARM Limited |
2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 29 unchanged lines hidden (view full) --- 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 46from Pci import PciConfigAll | 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 29 unchanged lines hidden (view full) --- 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 46from Pci import PciConfigAll |
47from Ethernet import NSGigE, IGbE_e1000, IGbE_igb | 47from Ethernet import NSGigE, IGbE_igb, IGbE_e1000 |
48from Ide import * 49from Platform import Platform 50from Terminal import Terminal 51from Uart import Uart 52from SimpleMemory import SimpleMemory 53from Gic import * 54 55class AmbaPioDevice(BasicPioDevice): --- 123 unchanged lines hidden (view full) --- 179class RealView(Platform): 180 type = 'RealView' 181 cxx_header = "dev/arm/realview.hh" 182 system = Param.System(Parent.any, "system") 183 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 184 mem_start_addr = Param.Addr(0, "Start address of main memory") 185 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 186 | 48from Ide import * 49from Platform import Platform 50from Terminal import Terminal 51from Uart import Uart 52from SimpleMemory import SimpleMemory 53from Gic import * 54 55class AmbaPioDevice(BasicPioDevice): --- 123 unchanged lines hidden (view full) --- 179class RealView(Platform): 180 type = 'RealView' 181 cxx_header = "dev/arm/realview.hh" 182 system = Param.System(Parent.any, "system") 183 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 184 mem_start_addr = Param.Addr(0, "Start address of main memory") 185 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 186 |
187 def attachPciDevices(self): 188 pass 189 190 def enableMSIX(self): 191 pass 192 193 def onChipIOClkDomain(self, clkdomain): 194 pass 195 196 def offChipIOClkDomain(self, clkdomain): 197 pass 198 |
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187 def setupBootLoader(self, mem_bus, cur_sys, loc): 188 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 189 conf_table_reported = False) 190 self.nvmem.port = mem_bus.master 191 cur_sys.boot_loader = loc('boot.arm') 192 cur_sys.atags_addr = 0x100 193 cur_sys.load_addr_mask = 0xfffffff 194 cur_sys.load_offset = 0 --- 50 unchanged lines hidden (view full) --- 245 # Bridge ranges based on excluding what is part of on-chip I/O 246 # (gic, l2x0, a9scu, local_cpu_timer) 247 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 248 self.a9scu.pio_addr - 1), 249 AddrRange(self.flash_fake.pio_addr, 250 self.flash_fake.pio_addr + \ 251 self.flash_fake.pio_size - 1)] 252 | 199 def setupBootLoader(self, mem_bus, cur_sys, loc): 200 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 201 conf_table_reported = False) 202 self.nvmem.port = mem_bus.master 203 cur_sys.boot_loader = loc('boot.arm') 204 cur_sys.atags_addr = 0x100 205 cur_sys.load_addr_mask = 0xfffffff 206 cur_sys.load_offset = 0 --- 50 unchanged lines hidden (view full) --- 257 # Bridge ranges based on excluding what is part of on-chip I/O 258 # (gic, l2x0, a9scu, local_cpu_timer) 259 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 260 self.a9scu.pio_addr - 1), 261 AddrRange(self.flash_fake.pio_addr, 262 self.flash_fake.pio_addr + \ 263 self.flash_fake.pio_size - 1)] 264 |
265 # Set the clock domain for IO objects that are considered 266 # to be "close" to the cores. 267 def onChipIOClkDomain(self, clkdomain): 268 self.gic.clk_domain = clkdomain 269 self.l2x0_fake.clk_domain = clkdomain 270 self.a9scu.clkdomain = clkdomain 271 self.local_cpu_timer.clk_domain = clkdomain 272 |
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253 # Attach I/O devices to specified bus object. Can't do this 254 # earlier, since the bus object itself is typically defined at the 255 # System level. 256 def attachIO(self, bus): 257 self.uart.pio = bus.master 258 self.realview_io.pio = bus.master 259 self.timer0.pio = bus.master 260 self.timer1.pio = bus.master --- 16 unchanged lines hidden (view full) --- 277 self.gpio2_fake.pio = bus.master 278 self.ssp_fake.pio = bus.master 279 self.sci_fake.pio = bus.master 280 self.aaci_fake.pio = bus.master 281 self.mmc_fake.pio = bus.master 282 self.rtc.pio = bus.master 283 self.flash_fake.pio = bus.master 284 | 273 # Attach I/O devices to specified bus object. Can't do this 274 # earlier, since the bus object itself is typically defined at the 275 # System level. 276 def attachIO(self, bus): 277 self.uart.pio = bus.master 278 self.realview_io.pio = bus.master 279 self.timer0.pio = bus.master 280 self.timer1.pio = bus.master --- 16 unchanged lines hidden (view full) --- 297 self.gpio2_fake.pio = bus.master 298 self.ssp_fake.pio = bus.master 299 self.sci_fake.pio = bus.master 300 self.aaci_fake.pio = bus.master 301 self.mmc_fake.pio = bus.master 302 self.rtc.pio = bus.master 303 self.flash_fake.pio = bus.master 304 |
305 # Set the clock domain for IO objects that are considered 306 # to be "far" away from the cores. 307 def offChipIOClkDomain(self, clkdomain): 308 self.uart.clk_domain = clkdomain 309 self.realview_io.clk_domain = clkdomain 310 self.timer0.clk_domain = clkdomain 311 self.timer1.clk_domain = clkdomain 312 self.clcd.clk_domain = clkdomain 313 self.kmi0.clk_domain = clkdomain 314 self.kmi1.clk_domain = clkdomain 315 self.cf_ctrl.clk_domain = clkdomain 316 self.dmac_fake.clk_domain = clkdomain 317 self.uart1_fake.clk_domain = clkdomain 318 self.uart2_fake.clk_domain = clkdomain 319 self.uart3_fake.clk_domain = clkdomain 320 self.smc_fake.clk_domain = clkdomain 321 self.sp810_fake.clk_domain = clkdomain 322 self.watchdog_fake.clk_domain = clkdomain 323 self.gpio0_fake.clk_domain = clkdomain 324 self.gpio1_fake.clk_domain = clkdomain 325 self.gpio2_fake.clk_domain = clkdomain 326 self.ssp_fake.clk_domain = clkdomain 327 self.sci_fake.clk_domain = clkdomain 328 self.aaci_fake.clk_domain = clkdomain 329 self.mmc_fake.clk_domain = clkdomain 330 self.rtc.clk_domain = clkdomain 331 self.flash_fake.clk_domain = clkdomain 332 |
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285# Reference for memory map and interrupt number 286# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 287# Chapter 4: Programmer's Reference 288class RealViewEB(RealView): 289 uart = Pl011(pio_addr=0x10009000, int_num=44) | 333# Reference for memory map and interrupt number 334# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 335# Chapter 4: Programmer's Reference 336class RealViewEB(RealView): 337 uart = Pl011(pio_addr=0x10009000, int_num=44) |
290 realview_io = RealViewCtrl(pio_addr=0x10000000) | 338 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) |
291 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 292 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 293 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 294 clcd = Pl111(pio_addr=0x10020000, int_num=23) 295 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 296 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 297 298 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") --- 24 unchanged lines hidden (view full) --- 323 self.gic.pio = bus.master 324 self.l2x0_fake.pio = bus.master 325 # Bridge ranges based on excluding what is part of on-chip I/O 326 # (gic, l2x0) 327 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 328 self.gic.cpu_addr - 1), 329 AddrRange(self.flash_fake.pio_addr, Addr.max)] 330 | 339 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 340 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 341 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 342 clcd = Pl111(pio_addr=0x10020000, int_num=23) 343 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 344 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 345 346 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") --- 24 unchanged lines hidden (view full) --- 371 self.gic.pio = bus.master 372 self.l2x0_fake.pio = bus.master 373 # Bridge ranges based on excluding what is part of on-chip I/O 374 # (gic, l2x0) 375 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 376 self.gic.cpu_addr - 1), 377 AddrRange(self.flash_fake.pio_addr, Addr.max)] 378 |
379 # Set the clock domain for IO objects that are considered 380 # to be "close" to the cores. 381 def onChipIOClkDomain(self, clkdomain): 382 self.gic.clk_domain = clkdomain 383 self.l2x0_fake.clk_domain = clkdomain 384 |
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331 # Attach I/O devices to specified bus object. Can't do this 332 # earlier, since the bus object itself is typically defined at the 333 # System level. 334 def attachIO(self, bus): 335 self.uart.pio = bus.master 336 self.realview_io.pio = bus.master 337 self.timer0.pio = bus.master 338 self.timer1.pio = bus.master --- 14 unchanged lines hidden (view full) --- 353 self.ssp_fake.pio = bus.master 354 self.sci_fake.pio = bus.master 355 self.aaci_fake.pio = bus.master 356 self.mmc_fake.pio = bus.master 357 self.rtc_fake.pio = bus.master 358 self.flash_fake.pio = bus.master 359 self.smcreg_fake.pio = bus.master 360 | 385 # Attach I/O devices to specified bus object. Can't do this 386 # earlier, since the bus object itself is typically defined at the 387 # System level. 388 def attachIO(self, bus): 389 self.uart.pio = bus.master 390 self.realview_io.pio = bus.master 391 self.timer0.pio = bus.master 392 self.timer1.pio = bus.master --- 14 unchanged lines hidden (view full) --- 407 self.ssp_fake.pio = bus.master 408 self.sci_fake.pio = bus.master 409 self.aaci_fake.pio = bus.master 410 self.mmc_fake.pio = bus.master 411 self.rtc_fake.pio = bus.master 412 self.flash_fake.pio = bus.master 413 self.smcreg_fake.pio = bus.master 414 |
415 # Set the clock domain for IO objects that are considered 416 # to be "far" away from the cores. 417 def offChipIOClkDomain(self, clkdomain): 418 self.uart.clk_domain = clkdomain 419 self.realview_io.clk_domain = clkdomain 420 self.timer0.clk_domain = clkdomain 421 self.timer1.clk_domain = clkdomain 422 self.clcd.clk_domain = clkdomain 423 self.kmi0.clk_domain = clkdomain 424 self.kmi1.clk_domain = clkdomain 425 self.dmac_fake.clk_domain = clkdomain 426 self.uart1_fake.clk_domain = clkdomain 427 self.uart2_fake.clk_domain = clkdomain 428 self.uart3_fake.clk_domain = clkdomain 429 self.smc_fake.clk_domain = clkdomain 430 self.sp810_fake.clk_domain = clkdomain 431 self.watchdog_fake.clk_domain = clkdomain 432 self.gpio0_fake.clk_domain = clkdomain 433 self.gpio1_fake.clk_domain = clkdomain 434 self.gpio2_fake.clk_domain = clkdomain 435 self.ssp_fake.clk_domain = clkdomain 436 self.sci_fake.clk_domain = clkdomain 437 self.aaci_fake.clk_domain = clkdomain 438 self.mmc_fake.clk_domain = clkdomain 439 self.rtc.clk_domain = clkdomain 440 self.flash_fake.clk_domain = clkdomain 441 self.smcreg_fake.clk_domain = clkdomain 442 |
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361class VExpress_EMM(RealView): 362 mem_start_addr = '2GB' 363 max_mem_size = '2GB' 364 pci_cfg_base = 0x30000000 365 uart = Pl011(pio_addr=0x1c090000, int_num=37) | 443class VExpress_EMM(RealView): 444 mem_start_addr = '2GB' 445 max_mem_size = '2GB' 446 pci_cfg_base = 0x30000000 447 uart = Pl011(pio_addr=0x1c090000, int_num=37) |
366 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000) | 448 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \ 449 idreg=0x02250000, pio_addr=0x1C010000) |
367 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 368 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 369 generic_timer = GenericTimer(int_num=29) 370 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 371 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 372 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 373 hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117) 374 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 375 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 376 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 377 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 378 io_shift = 2, ctrl_offset = 2, Command = 0x1, 379 BAR0 = 0x1C1A0000, BAR0Size = '256B', 380 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 381 BAR0LegacyIO = True, BAR1LegacyIO = True) 382 383 pciconfig = PciConfigAll(size='256MB') | 450 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 451 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 452 generic_timer = GenericTimer(int_num=29) 453 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 454 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 455 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 456 hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117) 457 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 458 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 459 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 460 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 461 io_shift = 2, ctrl_offset = 2, Command = 0x1, 462 BAR0 = 0x1C1A0000, BAR0Size = '256B', 463 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 464 BAR0LegacyIO = True, BAR1LegacyIO = True) 465 466 pciconfig = PciConfigAll(size='256MB') |
384 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 385 InterruptLine=1, InterruptPin=1) 386 387 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 388 InterruptLine=2, InterruptPin=2) 389 390 | |
391 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 392 conf_table_reported = False) 393 rtc = PL031(pio_addr=0x1C170000, int_num=36) 394 395 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 396 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 397 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 398 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 399 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 400 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 401 aaci_fake = AmbaFake(pio_addr=0x1C040000) 402 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 403 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 404 mmc_fake = AmbaFake(pio_addr=0x1c050000) 405 | 467 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 468 conf_table_reported = False) 469 rtc = PL031(pio_addr=0x1C170000, int_num=36) 470 471 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 472 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 473 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 474 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 475 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 476 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 477 aaci_fake = AmbaFake(pio_addr=0x1C040000) 478 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 479 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 480 mmc_fake = AmbaFake(pio_addr=0x1c050000) 481 |
482 # Attach any PCI devices that are supported 483 def attachPciDevices(self): 484 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 485 InterruptLine=1, InterruptPin=1) 486 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 487 InterruptLine=2, InterruptPin=2) 488 489 def enableMSIX(self): 490 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 491 self.gicv2m = Gicv2m() 492 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 493 |
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406 def setupBootLoader(self, mem_bus, cur_sys, loc): 407 self.nvmem = SimpleMemory(range = AddrRange('64MB'), 408 conf_table_reported = False) 409 self.nvmem.port = mem_bus.master 410 cur_sys.boot_loader = loc('boot_emm.arm') 411 cur_sys.atags_addr = 0x8000000 412 cur_sys.load_addr_mask = 0xfffffff 413 cur_sys.load_offset = 0x80000000 414 415 # Attach I/O devices that are on chip and also set the appropriate 416 # ranges for the bridge 417 def attachOnChipIO(self, bus, bridge): 418 self.gic.pio = bus.master 419 self.local_cpu_timer.pio = bus.master | 494 def setupBootLoader(self, mem_bus, cur_sys, loc): 495 self.nvmem = SimpleMemory(range = AddrRange('64MB'), 496 conf_table_reported = False) 497 self.nvmem.port = mem_bus.master 498 cur_sys.boot_loader = loc('boot_emm.arm') 499 cur_sys.atags_addr = 0x8000000 500 cur_sys.load_addr_mask = 0xfffffff 501 cur_sys.load_offset = 0x80000000 502 503 # Attach I/O devices that are on chip and also set the appropriate 504 # ranges for the bridge 505 def attachOnChipIO(self, bus, bridge): 506 self.gic.pio = bus.master 507 self.local_cpu_timer.pio = bus.master |
508 if hasattr(self, "gicv2m"): 509 self.gicv2m.pio = bus.master |
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420 self.hdlcd.dma = bus.slave 421 # Bridge ranges based on excluding what is part of on-chip I/O 422 # (gic, a9scu) 423 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 424 AddrRange(0x2B000000, size='4MB'), 425 AddrRange(0x30000000, size='256MB'), 426 AddrRange(0x40000000, size='512MB'), 427 AddrRange(0x18000000, size='64MB'), 428 AddrRange(0x1C000000, size='64MB')] 429 self.vgic.pio = bus.master 430 431 | 510 self.hdlcd.dma = bus.slave 511 # Bridge ranges based on excluding what is part of on-chip I/O 512 # (gic, a9scu) 513 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 514 AddrRange(0x2B000000, size='4MB'), 515 AddrRange(0x30000000, size='256MB'), 516 AddrRange(0x40000000, size='512MB'), 517 AddrRange(0x18000000, size='64MB'), 518 AddrRange(0x1C000000, size='64MB')] 519 self.vgic.pio = bus.master 520 521 |
432 # Attach I/O devices to specified bus object. Can't do this 433 # earlier, since the bus object itself is typically defined at the 434 # System level. | 522 # Set the clock domain for IO objects that are considered 523 # to be "close" to the cores. 524 def onChipIOClkDomain(self, clkdomain): 525 self.gic.clk_domain = clkdomain 526 if hasattr(self, "gicv2m"): 527 self.gicv2m.clk_domain = clkdomain 528 self.hdlcd.clk_domain = clkdomain 529 self.vgic.clk_domain = clkdomain 530 531 # Attach I/O devices to specified bus object. Done here 532 # as the specified bus to connect to may not always be fixed. |
435 def attachIO(self, bus): 436 self.uart.pio = bus.master 437 self.realview_io.pio = bus.master 438 self.timer0.pio = bus.master 439 self.timer1.pio = bus.master 440 self.clcd.pio = bus.master 441 self.clcd.dma = bus.slave 442 self.hdlcd.pio = bus.master 443 self.kmi0.pio = bus.master 444 self.kmi1.pio = bus.master 445 self.cf_ctrl.pio = bus.master 446 self.cf_ctrl.dma = bus.slave 447 self.cf_ctrl.config = bus.master 448 self.rtc.pio = bus.master 449 bus.use_default_range = True 450 self.vram.port = bus.master | 533 def attachIO(self, bus): 534 self.uart.pio = bus.master 535 self.realview_io.pio = bus.master 536 self.timer0.pio = bus.master 537 self.timer1.pio = bus.master 538 self.clcd.pio = bus.master 539 self.clcd.dma = bus.slave 540 self.hdlcd.pio = bus.master 541 self.kmi0.pio = bus.master 542 self.kmi1.pio = bus.master 543 self.cf_ctrl.pio = bus.master 544 self.cf_ctrl.dma = bus.slave 545 self.cf_ctrl.config = bus.master 546 self.rtc.pio = bus.master 547 bus.use_default_range = True 548 self.vram.port = bus.master |
451 self.ide.pio = bus.master 452 self.ide.config = bus.master 453 self.ide.dma = bus.slave 454 self.ethernet.pio = bus.master 455 self.ethernet.config = bus.master 456 self.ethernet.dma = bus.slave | |
457 self.pciconfig.pio = bus.default 458 459 self.l2x0_fake.pio = bus.master 460 self.uart1_fake.pio = bus.master 461 self.uart2_fake.pio = bus.master 462 self.uart3_fake.pio = bus.master 463 self.sp810_fake.pio = bus.master 464 self.watchdog_fake.pio = bus.master 465 self.aaci_fake.pio = bus.master 466 self.lan_fake.pio = bus.master 467 self.usb_fake.pio = bus.master 468 self.mmc_fake.pio = bus.master 469 | 549 self.pciconfig.pio = bus.default 550 551 self.l2x0_fake.pio = bus.master 552 self.uart1_fake.pio = bus.master 553 self.uart2_fake.pio = bus.master 554 self.uart3_fake.pio = bus.master 555 self.sp810_fake.pio = bus.master 556 self.watchdog_fake.pio = bus.master 557 self.aaci_fake.pio = bus.master 558 self.lan_fake.pio = bus.master 559 self.usb_fake.pio = bus.master 560 self.mmc_fake.pio = bus.master 561 |
562 # Try to attach the I/O if it exists 563 try: 564 self.ide.pio = bus.master 565 self.ide.config = bus.master 566 self.ide.dma = bus.slave 567 self.ethernet.pio = bus.master 568 self.ethernet.config = bus.master 569 self.ethernet.dma = bus.slave 570 except: 571 pass 572 573 # Set the clock domain for IO objects that are considered 574 # to be "far" away from the cores. 575 def offChipIOClkDomain(self, clkdomain): 576 self.uart.clk_domain = clkdomain 577 self.realview_io.clk_domain = clkdomain 578 self.timer0.clk_domain = clkdomain 579 self.timer1.clk_domain = clkdomain 580 self.clcd.clk_domain = clkdomain 581 self.kmi0.clk_domain = clkdomain 582 self.kmi1.clk_domain = clkdomain 583 self.cf_ctrl.clk_domain = clkdomain 584 self.rtc.clk_domain = clkdomain 585 self.vram.clk_domain = clkdomain 586 self.pciconfig.clk_domain = clkdomain 587 588 self.l2x0_fake.clk_domain = clkdomain 589 self.uart1_fake.clk_domain = clkdomain 590 self.uart2_fake.clk_domain = clkdomain 591 self.uart3_fake.clk_domain = clkdomain 592 self.sp810_fake.clk_domain = clkdomain 593 self.watchdog_fake.clk_domain = clkdomain 594 self.aaci_fake.clk_domain = clkdomain 595 self.lan_fake.clk_domain = clkdomain 596 self.usb_fake.clk_domain = clkdomain 597 self.mmc_fake.clk_domain = clkdomain 598 |
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470class VExpress_EMM64(VExpress_EMM): 471 def setupBootLoader(self, mem_bus, cur_sys, loc): 472 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 473 self.nvmem.port = mem_bus.master 474 cur_sys.boot_loader = loc('boot_emm.arm64') 475 cur_sys.atags_addr = 0x8000000 476 cur_sys.load_addr_mask = 0xfffffff 477 cur_sys.load_offset = 0x80000000 478 479 | 599class VExpress_EMM64(VExpress_EMM): 600 def setupBootLoader(self, mem_bus, cur_sys, loc): 601 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 602 self.nvmem.port = mem_bus.master 603 cur_sys.boot_loader = loc('boot_emm.arm64') 604 cur_sys.atags_addr = 0x8000000 605 cur_sys.load_addr_mask = 0xfffffff 606 cur_sys.load_offset = 0x80000000 607 608 |