1# Copyright (c) 2009-2011 ARM Limited |
2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 162 unchanged lines hidden (view full) --- 172 gpio2_fake = AmbaFake(pio_addr=0x10015000) 173 ssp_fake = AmbaFake(pio_addr=0x1000d000) 174 sci_fake = AmbaFake(pio_addr=0x1000e000) 175 aaci_fake = AmbaFake(pio_addr=0x10004000) 176 mmc_fake = AmbaFake(pio_addr=0x10005000) 177 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 178 179 |
180 # Attach I/O devices that are on chip and also set the appropriate 181 # ranges for the bridge 182 def attachOnChipIO(self, bus, bridge): |
183 self.gic.pio = bus.port 184 self.l2x0_fake.pio = bus.port 185 self.a9scu.pio = bus.port 186 self.local_cpu_timer.pio = bus.port |
187 # Bridge ranges based on excluding what is part of on-chip I/O 188 # (gic, l2x0, a9scu, local_cpu_timer) 189 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 190 self.a9scu.pio_addr - 1), 191 AddrRange(self.flash_fake.pio_addr, Addr.max)] |
192 193 # Attach I/O devices to specified bus object. Can't do this 194 # earlier, since the bus object itself is typically defined at the 195 # System level. 196 def attachIO(self, bus): 197 self.uart.pio = bus.port 198 self.realview_io.pio = bus.port 199 self.timer0.pio = bus.port --- 49 unchanged lines hidden (view full) --- 249 ssp_fake = AmbaFake(pio_addr=0x1000d000) 250 sci_fake = AmbaFake(pio_addr=0x1000e000) 251 aaci_fake = AmbaFake(pio_addr=0x10004000) 252 mmc_fake = AmbaFake(pio_addr=0x10005000) 253 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 254 255 256 |
257 # Attach I/O devices that are on chip and also set the appropriate 258 # ranges for the bridge 259 def attachOnChipIO(self, bus, bridge): |
260 self.gic.pio = bus.port 261 self.l2x0_fake.pio = bus.port |
262 # Bridge ranges based on excluding what is part of on-chip I/O 263 # (gic, l2x0) 264 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 265 self.gic.cpu_addr - 1), 266 AddrRange(self.flash_fake.pio_addr, Addr.max)] |
267 268 # Attach I/O devices to specified bus object. Can't do this 269 # earlier, since the bus object itself is typically defined at the 270 # System level. 271 def attachIO(self, bus): 272 self.uart.pio = bus.port 273 self.realview_io.pio = bus.port 274 self.timer0.pio = bus.port --- 61 unchanged lines hidden (view full) --- 336 elba_aaci_fake = AmbaFake(pio_addr=0xE0004000) 337 mmc_fake = AmbaFake(pio_addr=0xE0005000) # not sure if we need this 338 rtc_fake = AmbaFake(pio_addr=0xE0017000, amba_id=0x41031) 339 spsc_fake = IsaFake(pio_addr=0xE001B000, pio_size=0x2000) 340 lan_fake = IsaFake(pio_addr=0xFA000000, pio_size=0xffff) 341 usb_fake = IsaFake(pio_addr=0xFB000000, pio_size=0x1ffff) 342 343 |
344 # Attach I/O devices that are on chip and also set the appropriate 345 # ranges for the bridge 346 def attachOnChipIO(self, bus, bridge): |
347 self.gic.pio = bus.port 348 self.a9scu.pio = bus.port |
349 # Bridge ranges based on excluding what is part of on-chip I/O 350 # (gic, a9scu) 351 bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1), 352 AddrRange(self.local_cpu_timer.pio_addr, Addr.max)] |
353 354 # Attach I/O devices to specified bus object. Can't do this 355 # earlier, since the bus object itself is typically defined at the 356 # System level. 357 def attachIO(self, bus): 358 self.elba_uart.pio = bus.port 359 self.uart.pio = bus.port 360 self.realview_io.pio = bus.port --- 32 unchanged lines hidden --- |