| 1# Copyright (c) 2009-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 37 unchanged lines hidden (view full) --- 46from Pci import PciConfigAll 47from Ethernet import NSGigE, IGbE_igb, IGbE_e1000 48from Ide import * 49from Platform import Platform 50from Terminal import Terminal 51from Uart import Uart 52from SimpleMemory import SimpleMemory 53from Gic import * |
| 54from EnergyCtrl import EnergyCtrl |
| 55 56class AmbaPioDevice(BasicPioDevice): 57 type = 'AmbaPioDevice' 58 abstract = True 59 cxx_header = "dev/arm/amba_device.hh" 60 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 61 62class AmbaIntDevice(AmbaPioDevice): --- 180 unchanged lines hidden (view full) --- 243 gpio0_fake = AmbaFake(pio_addr=0x10013000) 244 gpio1_fake = AmbaFake(pio_addr=0x10014000) 245 gpio2_fake = AmbaFake(pio_addr=0x10015000) 246 ssp_fake = AmbaFake(pio_addr=0x1000d000) 247 sci_fake = AmbaFake(pio_addr=0x1000e000) 248 aaci_fake = AmbaFake(pio_addr=0x10004000) 249 mmc_fake = AmbaFake(pio_addr=0x10005000) 250 rtc = PL031(pio_addr=0x10017000, int_num=42) |
| 251 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) |
| 252 253 254 # Attach I/O devices that are on chip and also set the appropriate 255 # ranges for the bridge 256 def attachOnChipIO(self, bus, bridge): 257 self.gic.pio = bus.master 258 self.l2x0_fake.pio = bus.master 259 self.a9scu.pio = bus.master --- 40 unchanged lines hidden (view full) --- 300 self.gpio1_fake.pio = bus.master 301 self.gpio2_fake.pio = bus.master 302 self.ssp_fake.pio = bus.master 303 self.sci_fake.pio = bus.master 304 self.aaci_fake.pio = bus.master 305 self.mmc_fake.pio = bus.master 306 self.rtc.pio = bus.master 307 self.flash_fake.pio = bus.master |
| 308 self.energy_ctrl.pio = bus.master |
| 309 310 # Set the clock domain for IO objects that are considered 311 # to be "far" away from the cores. 312 def offChipIOClkDomain(self, clkdomain): 313 self.uart.clk_domain = clkdomain 314 self.realview_io.clk_domain = clkdomain 315 self.timer0.clk_domain = clkdomain 316 self.timer1.clk_domain = clkdomain --- 12 unchanged lines hidden (view full) --- 329 self.gpio1_fake.clk_domain = clkdomain 330 self.gpio2_fake.clk_domain = clkdomain 331 self.ssp_fake.clk_domain = clkdomain 332 self.sci_fake.clk_domain = clkdomain 333 self.aaci_fake.clk_domain = clkdomain 334 self.mmc_fake.clk_domain = clkdomain 335 self.rtc.clk_domain = clkdomain 336 self.flash_fake.clk_domain = clkdomain |
| 337 self.energy_ctrl.clk_domain = clkdomain |
| 338 339# Reference for memory map and interrupt number 340# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 341# Chapter 4: Programmer's Reference 342class RealViewEB(RealView): 343 uart = Pl011(pio_addr=0x10009000, int_num=44) 344 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 345 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) --- 17 unchanged lines hidden (view full) --- 363 gpio0_fake = AmbaFake(pio_addr=0x10013000) 364 gpio1_fake = AmbaFake(pio_addr=0x10014000) 365 gpio2_fake = AmbaFake(pio_addr=0x10015000) 366 ssp_fake = AmbaFake(pio_addr=0x1000d000) 367 sci_fake = AmbaFake(pio_addr=0x1000e000) 368 aaci_fake = AmbaFake(pio_addr=0x10004000) 369 mmc_fake = AmbaFake(pio_addr=0x10005000) 370 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) |
| 371 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) |
| 372 |
| 373 # Attach I/O devices that are on chip and also set the appropriate 374 # ranges for the bridge 375 def attachOnChipIO(self, bus, bridge): 376 self.gic.pio = bus.master 377 self.l2x0_fake.pio = bus.master 378 # Bridge ranges based on excluding what is part of on-chip I/O 379 # (gic, l2x0) 380 bridge.ranges = [AddrRange(self.realview_io.pio_addr, --- 30 unchanged lines hidden (view full) --- 411 self.gpio2_fake.pio = bus.master 412 self.ssp_fake.pio = bus.master 413 self.sci_fake.pio = bus.master 414 self.aaci_fake.pio = bus.master 415 self.mmc_fake.pio = bus.master 416 self.rtc_fake.pio = bus.master 417 self.flash_fake.pio = bus.master 418 self.smcreg_fake.pio = bus.master |
| 419 self.energy_ctrl.pio = bus.master |
| 420 421 # Set the clock domain for IO objects that are considered 422 # to be "far" away from the cores. 423 def offChipIOClkDomain(self, clkdomain): 424 self.uart.clk_domain = clkdomain 425 self.realview_io.clk_domain = clkdomain 426 self.timer0.clk_domain = clkdomain 427 self.timer1.clk_domain = clkdomain --- 12 unchanged lines hidden (view full) --- 440 self.gpio2_fake.clk_domain = clkdomain 441 self.ssp_fake.clk_domain = clkdomain 442 self.sci_fake.clk_domain = clkdomain 443 self.aaci_fake.clk_domain = clkdomain 444 self.mmc_fake.clk_domain = clkdomain 445 self.rtc.clk_domain = clkdomain 446 self.flash_fake.clk_domain = clkdomain 447 self.smcreg_fake.clk_domain = clkdomain |
| 448 self.energy_ctrl.clk_domain = clkdomain |
| 449 450class VExpress_EMM(RealView): 451 _mem_regions = [(Addr('2GB'), Addr('2GB'))] 452 pci_cfg_base = 0x30000000 453 uart = Pl011(pio_addr=0x1c090000, int_num=37) 454 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \ 455 idreg=0x02250000, pio_addr=0x1C010000) 456 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) --- 22 unchanged lines hidden (view full) --- 479 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 480 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 481 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 482 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 483 aaci_fake = AmbaFake(pio_addr=0x1C040000) 484 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 485 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 486 mmc_fake = AmbaFake(pio_addr=0x1c050000) |
| 487 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) |
| 488 489 # Attach any PCI devices that are supported 490 def attachPciDevices(self): 491 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 492 InterruptLine=1, InterruptPin=1) 493 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 494 InterruptLine=2, InterruptPin=2) 495 --- 64 unchanged lines hidden (view full) --- 560 self.uart2_fake.pio = bus.master 561 self.uart3_fake.pio = bus.master 562 self.sp810_fake.pio = bus.master 563 self.watchdog_fake.pio = bus.master 564 self.aaci_fake.pio = bus.master 565 self.lan_fake.pio = bus.master 566 self.usb_fake.pio = bus.master 567 self.mmc_fake.pio = bus.master |
| 568 self.energy_ctrl.pio = bus.master |
| 569 570 # Try to attach the I/O if it exists 571 try: 572 self.ide.pio = bus.master 573 self.ide.config = bus.master 574 self.ide.dma = bus.slave 575 self.ethernet.pio = bus.master 576 self.ethernet.config = bus.master --- 21 unchanged lines hidden (view full) --- 598 self.uart2_fake.clk_domain = clkdomain 599 self.uart3_fake.clk_domain = clkdomain 600 self.sp810_fake.clk_domain = clkdomain 601 self.watchdog_fake.clk_domain = clkdomain 602 self.aaci_fake.clk_domain = clkdomain 603 self.lan_fake.clk_domain = clkdomain 604 self.usb_fake.clk_domain = clkdomain 605 self.mmc_fake.clk_domain = clkdomain |
| 606 self.energy_ctrl.clk_domain = clkdomain |
| 607 608class VExpress_EMM64(VExpress_EMM): 609 pci_io_base = 0x2f000000 610 pci_cfg_gen_offsets = True 611 # Three memory regions are specified totalling 512GB 612 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 613 (Addr('512GB'), Addr('480GB'))] 614 def setupBootLoader(self, mem_bus, cur_sys, loc): 615 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 616 self.nvmem.port = mem_bus.master 617 cur_sys.boot_loader = loc('boot_emm.arm64') 618 cur_sys.atags_addr = 0x8000000 619 cur_sys.load_addr_mask = 0xfffffff 620 cur_sys.load_offset = 0x80000000 621 622 |