1c1
< # Copyright (c) 2009-2011 ARM Limited
---
> # Copyright (c) 2009 ARM Limited
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> platform = Param.Platform(Parent.any, "Platform this device is part of.")
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< # Attach I/O devices that are on chip and also set the appropriate
< # ranges for the bridge
< def attachOnChipIO(self, bus, bridge):
---
> # Attach I/O devices that are on chip
> def attachOnChipIO(self, bus):
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< # Bridge ranges based on excluding what is part of on-chip I/O
< # (gic, l2x0, a9scu, local_cpu_timer)
< bridge.ranges = [AddrRange(self.realview_io.pio_addr,
< self.a9scu.pio_addr - 1),
< AddrRange(self.flash_fake.pio_addr, Addr.max)]
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< self.clcd.dma = bus.port
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< self.cf_ctrl.config = bus.port
< self.cf_ctrl.dma = bus.port
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< # Attach I/O devices that are on chip and also set the appropriate
< # ranges for the bridge
< def attachOnChipIO(self, bus, bridge):
---
> # Attach I/O devices that are on chip
> def attachOnChipIO(self, bus):
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< # Bridge ranges based on excluding what is part of on-chip I/O
< # (gic, l2x0)
< bridge.ranges = [AddrRange(self.realview_io.pio_addr,
< self.gic.cpu_addr - 1),
< AddrRange(self.flash_fake.pio_addr, Addr.max)]
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< self.clcd.dma = bus.port
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< # Attach I/O devices that are on chip and also set the appropriate
< # ranges for the bridge
< def attachOnChipIO(self, bus, bridge):
---
> # Attach I/O devices that are on chip
> def attachOnChipIO(self, bus):
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< # Bridge ranges based on excluding what is part of on-chip I/O
< # (gic, a9scu)
< bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1),
< AddrRange(self.local_cpu_timer.pio_addr, Addr.max)]
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< self.clcd.dma = bus.port
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< self.cf_ctrl.config = bus.port
< self.cf_ctrl.dma = bus.port
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< self.ide.config = bus.port
< self.ide.dma = bus.port
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< self.ethernet.config = bus.port
< self.ethernet.dma = bus.port