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< # Copyright (c) 2009-2012 ARM Limited
---
> # Copyright (c) 2009-2013 ARM Limited
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> class VGic(PioDevice):
> type = 'VGic'
> cxx_header = "dev/arm/vgic.hh"
> gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
> platform = Param.Platform(Parent.any, "Platform this device is part of.")
> vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
> hv_addr = Param.Addr(0, "Address for hv control")
> pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
> # The number of list registers is not currently configurable at runtime.
> ppint = Param.UInt32("HV maintenance interrupt number")
>
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> class GenericTimer(SimObject):
> type = 'GenericTimer'
> cxx_header = "dev/arm/generic_timer.hh"
> system = Param.System(Parent.any, "system")
> gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
> int_num = Param.UInt32("Interrupt number used per-cpu to GIC")
> # @todo: for now only one timer per CPU is supported, which is the
> # normal behaviour when Security and Virt. extensions are disabled.
>
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> cur_sys.atags_addr = 0x100
> cur_sys.load_addr_mask = 0xfffffff
> cur_sys.load_offset = 0
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> generic_timer = GenericTimer(int_num=29)
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> vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
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< cur_sys.atags_addr = 0x80000100
---
> cur_sys.atags_addr = 0x8000000
> cur_sys.load_addr_mask = 0xfffffff
> cur_sys.load_offset = 0x80000000
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> self.vgic.pio = bus.master
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>
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> class VExpress_EMM64(VExpress_EMM):
> def setupBootLoader(self, mem_bus, cur_sys, loc):
> self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
> self.nvmem.port = mem_bus.master
> cur_sys.boot_loader = loc('boot_emm.arm64')
> cur_sys.atags_addr = 0x8000000
> cur_sys.load_addr_mask = 0xfffffff
> cur_sys.load_offset = 0x80000000
>
>