1c1
< # Copyright (c) 2009-2017 ARM Limited
---
> # Copyright (c) 2009-2018 ARM Limited
583,585c583,587
< self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
< conf_table_reported = False)
< self.nvmem.port = mem_bus.master
---
> cur_sys.bootmem = SimpleMemory(
> range = AddrRange('2GB', size = '64MB'),
> conf_table_reported = False)
> if mem_bus is not None:
> cur_sys.bootmem.port = mem_bus.master
974,976c976,979
< self.nvmem = SimpleMemory(range = AddrRange('64MB'),
< conf_table_reported = False)
< self.nvmem.port = mem_bus.master
---
> cur_sys.bootmem = SimpleMemory(range = AddrRange('64MB'),
> conf_table_reported = False)
> if mem_bus is not None:
> cur_sys.bootmem.port = mem_bus.master
991,993c994,997
< self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
< conf_table_reported=False)
< self.nvmem.port = mem_bus.master
---
> cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'),
> conf_table_reported=False)
> if mem_bus is not None:
> cur_sys.bootmem.port = mem_bus.master
999d1002
<
1167,1169c1170,1173
< self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
< conf_table_reported=False)
< self.nvmem.port = mem_bus.master
---
> cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'),
> conf_table_reported=False)
> if mem_bus is not None:
> cur_sys.bootmem.port = mem_bus.master