1# Copyright (c) 2009-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42
43from m5.params import *
44from m5.proxy import *
45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
46from Pci import PciConfigAll
47from Ethernet import NSGigE, IGbE_e1000, IGbE_igb
48from Ide import *
49from Platform import Platform
50from Terminal import Terminal
51from Uart import Uart
52from SimpleMemory import SimpleMemory
53
54class AmbaDevice(BasicPioDevice):
55 type = 'AmbaDevice'
56 abstract = True
57 cxx_header = "dev/arm/amba_device.hh"
58 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
59
60class AmbaIntDevice(AmbaDevice):
61 type = 'AmbaIntDevice'
62 abstract = True
63 cxx_header = "dev/arm/amba_device.hh"
64 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
65 int_num = Param.UInt32("Interrupt number that connects to GIC")
66 int_delay = Param.Latency("100ns",
67 "Time between action and interrupt generation by device")
68
69class AmbaDmaDevice(DmaDevice):
70 type = 'AmbaDmaDevice'
71 abstract = True
72 cxx_header = "dev/arm/amba_device.hh"
73 pio_addr = Param.Addr("Address for AMBA slave interface")
74 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
75 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
76 int_num = Param.UInt32("Interrupt number that connects to GIC")
77 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
78
79class A9SCU(BasicPioDevice):
80 type = 'A9SCU'
81 cxx_header = "dev/arm/a9scu.hh"
82
83class RealViewCtrl(BasicPioDevice):
84 type = 'RealViewCtrl'
85 cxx_header = "dev/arm/rv_ctrl.hh"
86 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
87 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
88 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
89
90class Gic(PioDevice):
91 type = 'Gic'
92 cxx_header = "dev/arm/gic.hh"
93 platform = Param.Platform(Parent.any, "Platform this device is part of.")
94 dist_addr = Param.Addr(0x1f001000, "Address for distributor")
95 cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
96 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
97 cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
98 int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
99 it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
100
101class AmbaFake(AmbaDevice):
102 type = 'AmbaFake'
103 cxx_header = "dev/arm/amba_fake.hh"
104 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
105 amba_id = 0;
106
107class Pl011(Uart):
108 type = 'Pl011'
109 cxx_header = "dev/arm/pl011.hh"
110 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
111 int_num = Param.UInt32("Interrupt number that connects to GIC")
112 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
113 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
114
115class Sp804(AmbaDevice):
116 type = 'Sp804'
117 cxx_header = "dev/arm/timer_sp804.hh"
118 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
119 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
120 clock0 = Param.Clock('1MHz', "Clock speed of the input")
121 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
122 clock1 = Param.Clock('1MHz', "Clock speed of the input")
123 amba_id = 0x00141804
124
125class CpuLocalTimer(BasicPioDevice):
126 type = 'CpuLocalTimer'
127 cxx_header = "dev/arm/timer_cpulocal.hh"
128 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
129 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
130 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
131 # Override the default clock
132 clock = '1GHz'
133
134class PL031(AmbaIntDevice):
135 type = 'PL031'
136 cxx_header = "dev/arm/rtc_pl031.hh"
137 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
138 amba_id = 0x00341031
139
140class Pl050(AmbaIntDevice):
141 type = 'Pl050'
142 cxx_header = "dev/arm/kmi.hh"
143 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
144 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
145 int_delay = '1us'
146 amba_id = 0x00141050
147
148class Pl111(AmbaDmaDevice):
149 type = 'Pl111'
150 cxx_header = "dev/arm/pl111.hh"
| 1# Copyright (c) 2009-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42
43from m5.params import *
44from m5.proxy import *
45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
46from Pci import PciConfigAll
47from Ethernet import NSGigE, IGbE_e1000, IGbE_igb
48from Ide import *
49from Platform import Platform
50from Terminal import Terminal
51from Uart import Uart
52from SimpleMemory import SimpleMemory
53
54class AmbaDevice(BasicPioDevice):
55 type = 'AmbaDevice'
56 abstract = True
57 cxx_header = "dev/arm/amba_device.hh"
58 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
59
60class AmbaIntDevice(AmbaDevice):
61 type = 'AmbaIntDevice'
62 abstract = True
63 cxx_header = "dev/arm/amba_device.hh"
64 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
65 int_num = Param.UInt32("Interrupt number that connects to GIC")
66 int_delay = Param.Latency("100ns",
67 "Time between action and interrupt generation by device")
68
69class AmbaDmaDevice(DmaDevice):
70 type = 'AmbaDmaDevice'
71 abstract = True
72 cxx_header = "dev/arm/amba_device.hh"
73 pio_addr = Param.Addr("Address for AMBA slave interface")
74 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
75 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
76 int_num = Param.UInt32("Interrupt number that connects to GIC")
77 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
78
79class A9SCU(BasicPioDevice):
80 type = 'A9SCU'
81 cxx_header = "dev/arm/a9scu.hh"
82
83class RealViewCtrl(BasicPioDevice):
84 type = 'RealViewCtrl'
85 cxx_header = "dev/arm/rv_ctrl.hh"
86 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
87 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
88 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
89
90class Gic(PioDevice):
91 type = 'Gic'
92 cxx_header = "dev/arm/gic.hh"
93 platform = Param.Platform(Parent.any, "Platform this device is part of.")
94 dist_addr = Param.Addr(0x1f001000, "Address for distributor")
95 cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
96 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
97 cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
98 int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
99 it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
100
101class AmbaFake(AmbaDevice):
102 type = 'AmbaFake'
103 cxx_header = "dev/arm/amba_fake.hh"
104 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
105 amba_id = 0;
106
107class Pl011(Uart):
108 type = 'Pl011'
109 cxx_header = "dev/arm/pl011.hh"
110 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
111 int_num = Param.UInt32("Interrupt number that connects to GIC")
112 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
113 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
114
115class Sp804(AmbaDevice):
116 type = 'Sp804'
117 cxx_header = "dev/arm/timer_sp804.hh"
118 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
119 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
120 clock0 = Param.Clock('1MHz', "Clock speed of the input")
121 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
122 clock1 = Param.Clock('1MHz', "Clock speed of the input")
123 amba_id = 0x00141804
124
125class CpuLocalTimer(BasicPioDevice):
126 type = 'CpuLocalTimer'
127 cxx_header = "dev/arm/timer_cpulocal.hh"
128 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
129 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
130 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
131 # Override the default clock
132 clock = '1GHz'
133
134class PL031(AmbaIntDevice):
135 type = 'PL031'
136 cxx_header = "dev/arm/rtc_pl031.hh"
137 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
138 amba_id = 0x00341031
139
140class Pl050(AmbaIntDevice):
141 type = 'Pl050'
142 cxx_header = "dev/arm/kmi.hh"
143 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
144 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
145 int_delay = '1us'
146 amba_id = 0x00141050
147
148class Pl111(AmbaDmaDevice):
149 type = 'Pl111'
150 cxx_header = "dev/arm/pl111.hh"
|
153 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
154 amba_id = 0x00141111
155
156class RealView(Platform):
157 type = 'RealView'
158 cxx_header = "dev/arm/realview.hh"
159 system = Param.System(Parent.any, "system")
160 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
161 mem_start_addr = Param.Addr(0, "Start address of main memory")
162 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform")
163
164 def setupBootLoader(self, mem_bus, cur_sys, loc):
165 self.nvmem = SimpleMemory(range = AddrRange(Addr('2GB'),
166 size = '64MB'),
167 zero = True)
168 self.nvmem.port = mem_bus.master
169 cur_sys.boot_loader = loc('boot.arm')
170
171
172# Reference for memory map and interrupt number
173# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
174# Chapter 4: Programmer's Reference
175class RealViewPBX(RealView):
176 uart = Pl011(pio_addr=0x10009000, int_num=44)
177 realview_io = RealViewCtrl(pio_addr=0x10000000)
178 gic = Gic()
179 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
180 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
181 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600)
182 clcd = Pl111(pio_addr=0x10020000, int_num=55)
183 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
184 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
185 a9scu = A9SCU(pio_addr=0x1f000000)
186 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
187 io_shift = 1, ctrl_offset = 2, Command = 0x1,
188 BAR0 = 0x18000000, BAR0Size = '16B',
189 BAR1 = 0x18000100, BAR1Size = '1B',
190 BAR0LegacyIO = True, BAR1LegacyIO = True)
191
192
193 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
194 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
195 fake_mem=True)
196 dmac_fake = AmbaFake(pio_addr=0x10030000)
197 uart1_fake = AmbaFake(pio_addr=0x1000a000)
198 uart2_fake = AmbaFake(pio_addr=0x1000b000)
199 uart3_fake = AmbaFake(pio_addr=0x1000c000)
200 smc_fake = AmbaFake(pio_addr=0x100e1000)
201 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
202 watchdog_fake = AmbaFake(pio_addr=0x10010000)
203 gpio0_fake = AmbaFake(pio_addr=0x10013000)
204 gpio1_fake = AmbaFake(pio_addr=0x10014000)
205 gpio2_fake = AmbaFake(pio_addr=0x10015000)
206 ssp_fake = AmbaFake(pio_addr=0x1000d000)
207 sci_fake = AmbaFake(pio_addr=0x1000e000)
208 aaci_fake = AmbaFake(pio_addr=0x10004000)
209 mmc_fake = AmbaFake(pio_addr=0x10005000)
210 rtc = PL031(pio_addr=0x10017000, int_num=42)
211
212
213 # Attach I/O devices that are on chip and also set the appropriate
214 # ranges for the bridge
215 def attachOnChipIO(self, bus, bridge):
216 self.gic.pio = bus.master
217 self.l2x0_fake.pio = bus.master
218 self.a9scu.pio = bus.master
219 self.local_cpu_timer.pio = bus.master
220 # Bridge ranges based on excluding what is part of on-chip I/O
221 # (gic, l2x0, a9scu, local_cpu_timer)
222 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
223 self.a9scu.pio_addr - 1),
224 AddrRange(self.flash_fake.pio_addr,
225 self.flash_fake.pio_addr + \
226 self.flash_fake.pio_size - 1)]
227
228 # Attach I/O devices to specified bus object. Can't do this
229 # earlier, since the bus object itself is typically defined at the
230 # System level.
231 def attachIO(self, bus):
232 self.uart.pio = bus.master
233 self.realview_io.pio = bus.master
234 self.timer0.pio = bus.master
235 self.timer1.pio = bus.master
236 self.clcd.pio = bus.master
237 self.clcd.dma = bus.slave
238 self.kmi0.pio = bus.master
239 self.kmi1.pio = bus.master
240 self.cf_ctrl.pio = bus.master
241 self.cf_ctrl.config = bus.master
242 self.cf_ctrl.dma = bus.slave
243 self.dmac_fake.pio = bus.master
244 self.uart1_fake.pio = bus.master
245 self.uart2_fake.pio = bus.master
246 self.uart3_fake.pio = bus.master
247 self.smc_fake.pio = bus.master
248 self.sp810_fake.pio = bus.master
249 self.watchdog_fake.pio = bus.master
250 self.gpio0_fake.pio = bus.master
251 self.gpio1_fake.pio = bus.master
252 self.gpio2_fake.pio = bus.master
253 self.ssp_fake.pio = bus.master
254 self.sci_fake.pio = bus.master
255 self.aaci_fake.pio = bus.master
256 self.mmc_fake.pio = bus.master
257 self.rtc.pio = bus.master
258 self.flash_fake.pio = bus.master
259
260# Reference for memory map and interrupt number
261# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
262# Chapter 4: Programmer's Reference
263class RealViewEB(RealView):
264 uart = Pl011(pio_addr=0x10009000, int_num=44)
265 realview_io = RealViewCtrl(pio_addr=0x10000000)
266 gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000)
267 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
268 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
269 clcd = Pl111(pio_addr=0x10020000, int_num=23)
270 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
271 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
272
273 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
274 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
275 fake_mem=True)
276 dmac_fake = AmbaFake(pio_addr=0x10030000)
277 uart1_fake = AmbaFake(pio_addr=0x1000a000)
278 uart2_fake = AmbaFake(pio_addr=0x1000b000)
279 uart3_fake = AmbaFake(pio_addr=0x1000c000)
280 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
281 smc_fake = AmbaFake(pio_addr=0x100e1000)
282 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
283 watchdog_fake = AmbaFake(pio_addr=0x10010000)
284 gpio0_fake = AmbaFake(pio_addr=0x10013000)
285 gpio1_fake = AmbaFake(pio_addr=0x10014000)
286 gpio2_fake = AmbaFake(pio_addr=0x10015000)
287 ssp_fake = AmbaFake(pio_addr=0x1000d000)
288 sci_fake = AmbaFake(pio_addr=0x1000e000)
289 aaci_fake = AmbaFake(pio_addr=0x10004000)
290 mmc_fake = AmbaFake(pio_addr=0x10005000)
291 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
292
293
294
295 # Attach I/O devices that are on chip and also set the appropriate
296 # ranges for the bridge
297 def attachOnChipIO(self, bus, bridge):
298 self.gic.pio = bus.master
299 self.l2x0_fake.pio = bus.master
300 # Bridge ranges based on excluding what is part of on-chip I/O
301 # (gic, l2x0)
302 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
303 self.gic.cpu_addr - 1),
304 AddrRange(self.flash_fake.pio_addr, Addr.max)]
305
306 # Attach I/O devices to specified bus object. Can't do this
307 # earlier, since the bus object itself is typically defined at the
308 # System level.
309 def attachIO(self, bus):
310 self.uart.pio = bus.master
311 self.realview_io.pio = bus.master
312 self.timer0.pio = bus.master
313 self.timer1.pio = bus.master
314 self.clcd.pio = bus.master
315 self.clcd.dma = bus.slave
316 self.kmi0.pio = bus.master
317 self.kmi1.pio = bus.master
318 self.dmac_fake.pio = bus.master
319 self.uart1_fake.pio = bus.master
320 self.uart2_fake.pio = bus.master
321 self.uart3_fake.pio = bus.master
322 self.smc_fake.pio = bus.master
323 self.sp810_fake.pio = bus.master
324 self.watchdog_fake.pio = bus.master
325 self.gpio0_fake.pio = bus.master
326 self.gpio1_fake.pio = bus.master
327 self.gpio2_fake.pio = bus.master
328 self.ssp_fake.pio = bus.master
329 self.sci_fake.pio = bus.master
330 self.aaci_fake.pio = bus.master
331 self.mmc_fake.pio = bus.master
332 self.rtc_fake.pio = bus.master
333 self.flash_fake.pio = bus.master
334 self.smcreg_fake.pio = bus.master
335
336class VExpress_EMM(RealView):
337 mem_start_addr = '2GB'
338 max_mem_size = '2GB'
339 pci_cfg_base = 0x30000000
340 uart = Pl011(pio_addr=0x1c090000, int_num=37)
341 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000)
342 gic = Gic(dist_addr=0x2C001000, cpu_addr=0x2C002000)
343 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000)
344 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
345 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
346 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
347 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
348 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
349 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
350 io_shift = 2, ctrl_offset = 2, Command = 0x1,
351 BAR0 = 0x1C1A0000, BAR0Size = '256B',
352 BAR1 = 0x1C1A0100, BAR1Size = '4096B',
353 BAR0LegacyIO = True, BAR1LegacyIO = True)
354
355 pciconfig = PciConfigAll(size='256MB')
356 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
357 InterruptLine=1, InterruptPin=1)
358
359 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
360 InterruptLine=2, InterruptPin=2)
361
362
363 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
364 zero = True)
365 rtc = PL031(pio_addr=0x1C170000, int_num=36)
366
367 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
368 uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
369 uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
370 uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
371 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
372 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
373 aaci_fake = AmbaFake(pio_addr=0x1C040000)
374 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
375 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
376 mmc_fake = AmbaFake(pio_addr=0x1c050000)
377
378 def setupBootLoader(self, mem_bus, cur_sys, loc):
379 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'),
380 zero = True)
381 self.nvmem.port = mem_bus.master
382 cur_sys.boot_loader = loc('boot_emm.arm')
383 cur_sys.atags_addr = 0x80000100
384
385 # Attach I/O devices that are on chip and also set the appropriate
386 # ranges for the bridge
387 def attachOnChipIO(self, bus, bridge):
388 self.gic.pio = bus.master
389 self.local_cpu_timer.pio = bus.master
390 # Bridge ranges based on excluding what is part of on-chip I/O
391 # (gic, a9scu)
392 bridge.ranges = [AddrRange(0x2F000000, size='16MB'),
393 AddrRange(0x30000000, size='256MB'),
394 AddrRange(0x40000000, size='512MB'),
395 AddrRange(0x18000000, size='64MB'),
396 AddrRange(0x1C000000, size='64MB')]
397
398 # Attach I/O devices to specified bus object. Can't do this
399 # earlier, since the bus object itself is typically defined at the
400 # System level.
401 def attachIO(self, bus):
402 self.uart.pio = bus.master
403 self.realview_io.pio = bus.master
404 self.timer0.pio = bus.master
405 self.timer1.pio = bus.master
406 self.clcd.pio = bus.master
407 self.clcd.dma = bus.slave
408 self.kmi0.pio = bus.master
409 self.kmi1.pio = bus.master
410 self.cf_ctrl.pio = bus.master
411 self.cf_ctrl.dma = bus.slave
412 self.cf_ctrl.config = bus.master
413 self.rtc.pio = bus.master
414 bus.use_default_range = True
415 self.vram.port = bus.master
416 self.ide.pio = bus.master
417 self.ide.config = bus.master
418 self.ide.dma = bus.slave
419 self.ethernet.pio = bus.master
420 self.ethernet.config = bus.master
421 self.ethernet.dma = bus.slave
422 self.pciconfig.pio = bus.default
423
424 self.l2x0_fake.pio = bus.master
425 self.uart1_fake.pio = bus.master
426 self.uart2_fake.pio = bus.master
427 self.uart3_fake.pio = bus.master
428 self.sp810_fake.pio = bus.master
429 self.watchdog_fake.pio = bus.master
430 self.aaci_fake.pio = bus.master
431 self.lan_fake.pio = bus.master
432 self.usb_fake.pio = bus.master
433 self.mmc_fake.pio = bus.master
434
| 152 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
153 amba_id = 0x00141111
154
155class RealView(Platform):
156 type = 'RealView'
157 cxx_header = "dev/arm/realview.hh"
158 system = Param.System(Parent.any, "system")
159 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
160 mem_start_addr = Param.Addr(0, "Start address of main memory")
161 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform")
162
163 def setupBootLoader(self, mem_bus, cur_sys, loc):
164 self.nvmem = SimpleMemory(range = AddrRange(Addr('2GB'),
165 size = '64MB'),
166 zero = True)
167 self.nvmem.port = mem_bus.master
168 cur_sys.boot_loader = loc('boot.arm')
169
170
171# Reference for memory map and interrupt number
172# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
173# Chapter 4: Programmer's Reference
174class RealViewPBX(RealView):
175 uart = Pl011(pio_addr=0x10009000, int_num=44)
176 realview_io = RealViewCtrl(pio_addr=0x10000000)
177 gic = Gic()
178 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
179 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
180 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600)
181 clcd = Pl111(pio_addr=0x10020000, int_num=55)
182 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
183 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
184 a9scu = A9SCU(pio_addr=0x1f000000)
185 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
186 io_shift = 1, ctrl_offset = 2, Command = 0x1,
187 BAR0 = 0x18000000, BAR0Size = '16B',
188 BAR1 = 0x18000100, BAR1Size = '1B',
189 BAR0LegacyIO = True, BAR1LegacyIO = True)
190
191
192 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
193 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
194 fake_mem=True)
195 dmac_fake = AmbaFake(pio_addr=0x10030000)
196 uart1_fake = AmbaFake(pio_addr=0x1000a000)
197 uart2_fake = AmbaFake(pio_addr=0x1000b000)
198 uart3_fake = AmbaFake(pio_addr=0x1000c000)
199 smc_fake = AmbaFake(pio_addr=0x100e1000)
200 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
201 watchdog_fake = AmbaFake(pio_addr=0x10010000)
202 gpio0_fake = AmbaFake(pio_addr=0x10013000)
203 gpio1_fake = AmbaFake(pio_addr=0x10014000)
204 gpio2_fake = AmbaFake(pio_addr=0x10015000)
205 ssp_fake = AmbaFake(pio_addr=0x1000d000)
206 sci_fake = AmbaFake(pio_addr=0x1000e000)
207 aaci_fake = AmbaFake(pio_addr=0x10004000)
208 mmc_fake = AmbaFake(pio_addr=0x10005000)
209 rtc = PL031(pio_addr=0x10017000, int_num=42)
210
211
212 # Attach I/O devices that are on chip and also set the appropriate
213 # ranges for the bridge
214 def attachOnChipIO(self, bus, bridge):
215 self.gic.pio = bus.master
216 self.l2x0_fake.pio = bus.master
217 self.a9scu.pio = bus.master
218 self.local_cpu_timer.pio = bus.master
219 # Bridge ranges based on excluding what is part of on-chip I/O
220 # (gic, l2x0, a9scu, local_cpu_timer)
221 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
222 self.a9scu.pio_addr - 1),
223 AddrRange(self.flash_fake.pio_addr,
224 self.flash_fake.pio_addr + \
225 self.flash_fake.pio_size - 1)]
226
227 # Attach I/O devices to specified bus object. Can't do this
228 # earlier, since the bus object itself is typically defined at the
229 # System level.
230 def attachIO(self, bus):
231 self.uart.pio = bus.master
232 self.realview_io.pio = bus.master
233 self.timer0.pio = bus.master
234 self.timer1.pio = bus.master
235 self.clcd.pio = bus.master
236 self.clcd.dma = bus.slave
237 self.kmi0.pio = bus.master
238 self.kmi1.pio = bus.master
239 self.cf_ctrl.pio = bus.master
240 self.cf_ctrl.config = bus.master
241 self.cf_ctrl.dma = bus.slave
242 self.dmac_fake.pio = bus.master
243 self.uart1_fake.pio = bus.master
244 self.uart2_fake.pio = bus.master
245 self.uart3_fake.pio = bus.master
246 self.smc_fake.pio = bus.master
247 self.sp810_fake.pio = bus.master
248 self.watchdog_fake.pio = bus.master
249 self.gpio0_fake.pio = bus.master
250 self.gpio1_fake.pio = bus.master
251 self.gpio2_fake.pio = bus.master
252 self.ssp_fake.pio = bus.master
253 self.sci_fake.pio = bus.master
254 self.aaci_fake.pio = bus.master
255 self.mmc_fake.pio = bus.master
256 self.rtc.pio = bus.master
257 self.flash_fake.pio = bus.master
258
259# Reference for memory map and interrupt number
260# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
261# Chapter 4: Programmer's Reference
262class RealViewEB(RealView):
263 uart = Pl011(pio_addr=0x10009000, int_num=44)
264 realview_io = RealViewCtrl(pio_addr=0x10000000)
265 gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000)
266 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
267 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
268 clcd = Pl111(pio_addr=0x10020000, int_num=23)
269 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
270 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
271
272 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
273 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
274 fake_mem=True)
275 dmac_fake = AmbaFake(pio_addr=0x10030000)
276 uart1_fake = AmbaFake(pio_addr=0x1000a000)
277 uart2_fake = AmbaFake(pio_addr=0x1000b000)
278 uart3_fake = AmbaFake(pio_addr=0x1000c000)
279 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
280 smc_fake = AmbaFake(pio_addr=0x100e1000)
281 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
282 watchdog_fake = AmbaFake(pio_addr=0x10010000)
283 gpio0_fake = AmbaFake(pio_addr=0x10013000)
284 gpio1_fake = AmbaFake(pio_addr=0x10014000)
285 gpio2_fake = AmbaFake(pio_addr=0x10015000)
286 ssp_fake = AmbaFake(pio_addr=0x1000d000)
287 sci_fake = AmbaFake(pio_addr=0x1000e000)
288 aaci_fake = AmbaFake(pio_addr=0x10004000)
289 mmc_fake = AmbaFake(pio_addr=0x10005000)
290 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
291
292
293
294 # Attach I/O devices that are on chip and also set the appropriate
295 # ranges for the bridge
296 def attachOnChipIO(self, bus, bridge):
297 self.gic.pio = bus.master
298 self.l2x0_fake.pio = bus.master
299 # Bridge ranges based on excluding what is part of on-chip I/O
300 # (gic, l2x0)
301 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
302 self.gic.cpu_addr - 1),
303 AddrRange(self.flash_fake.pio_addr, Addr.max)]
304
305 # Attach I/O devices to specified bus object. Can't do this
306 # earlier, since the bus object itself is typically defined at the
307 # System level.
308 def attachIO(self, bus):
309 self.uart.pio = bus.master
310 self.realview_io.pio = bus.master
311 self.timer0.pio = bus.master
312 self.timer1.pio = bus.master
313 self.clcd.pio = bus.master
314 self.clcd.dma = bus.slave
315 self.kmi0.pio = bus.master
316 self.kmi1.pio = bus.master
317 self.dmac_fake.pio = bus.master
318 self.uart1_fake.pio = bus.master
319 self.uart2_fake.pio = bus.master
320 self.uart3_fake.pio = bus.master
321 self.smc_fake.pio = bus.master
322 self.sp810_fake.pio = bus.master
323 self.watchdog_fake.pio = bus.master
324 self.gpio0_fake.pio = bus.master
325 self.gpio1_fake.pio = bus.master
326 self.gpio2_fake.pio = bus.master
327 self.ssp_fake.pio = bus.master
328 self.sci_fake.pio = bus.master
329 self.aaci_fake.pio = bus.master
330 self.mmc_fake.pio = bus.master
331 self.rtc_fake.pio = bus.master
332 self.flash_fake.pio = bus.master
333 self.smcreg_fake.pio = bus.master
334
335class VExpress_EMM(RealView):
336 mem_start_addr = '2GB'
337 max_mem_size = '2GB'
338 pci_cfg_base = 0x30000000
339 uart = Pl011(pio_addr=0x1c090000, int_num=37)
340 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000)
341 gic = Gic(dist_addr=0x2C001000, cpu_addr=0x2C002000)
342 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000)
343 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
344 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
345 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
346 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
347 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
348 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
349 io_shift = 2, ctrl_offset = 2, Command = 0x1,
350 BAR0 = 0x1C1A0000, BAR0Size = '256B',
351 BAR1 = 0x1C1A0100, BAR1Size = '4096B',
352 BAR0LegacyIO = True, BAR1LegacyIO = True)
353
354 pciconfig = PciConfigAll(size='256MB')
355 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
356 InterruptLine=1, InterruptPin=1)
357
358 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
359 InterruptLine=2, InterruptPin=2)
360
361
362 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
363 zero = True)
364 rtc = PL031(pio_addr=0x1C170000, int_num=36)
365
366 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
367 uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
368 uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
369 uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
370 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
371 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
372 aaci_fake = AmbaFake(pio_addr=0x1C040000)
373 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
374 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
375 mmc_fake = AmbaFake(pio_addr=0x1c050000)
376
377 def setupBootLoader(self, mem_bus, cur_sys, loc):
378 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'),
379 zero = True)
380 self.nvmem.port = mem_bus.master
381 cur_sys.boot_loader = loc('boot_emm.arm')
382 cur_sys.atags_addr = 0x80000100
383
384 # Attach I/O devices that are on chip and also set the appropriate
385 # ranges for the bridge
386 def attachOnChipIO(self, bus, bridge):
387 self.gic.pio = bus.master
388 self.local_cpu_timer.pio = bus.master
389 # Bridge ranges based on excluding what is part of on-chip I/O
390 # (gic, a9scu)
391 bridge.ranges = [AddrRange(0x2F000000, size='16MB'),
392 AddrRange(0x30000000, size='256MB'),
393 AddrRange(0x40000000, size='512MB'),
394 AddrRange(0x18000000, size='64MB'),
395 AddrRange(0x1C000000, size='64MB')]
396
397 # Attach I/O devices to specified bus object. Can't do this
398 # earlier, since the bus object itself is typically defined at the
399 # System level.
400 def attachIO(self, bus):
401 self.uart.pio = bus.master
402 self.realview_io.pio = bus.master
403 self.timer0.pio = bus.master
404 self.timer1.pio = bus.master
405 self.clcd.pio = bus.master
406 self.clcd.dma = bus.slave
407 self.kmi0.pio = bus.master
408 self.kmi1.pio = bus.master
409 self.cf_ctrl.pio = bus.master
410 self.cf_ctrl.dma = bus.slave
411 self.cf_ctrl.config = bus.master
412 self.rtc.pio = bus.master
413 bus.use_default_range = True
414 self.vram.port = bus.master
415 self.ide.pio = bus.master
416 self.ide.config = bus.master
417 self.ide.dma = bus.slave
418 self.ethernet.pio = bus.master
419 self.ethernet.config = bus.master
420 self.ethernet.dma = bus.slave
421 self.pciconfig.pio = bus.default
422
423 self.l2x0_fake.pio = bus.master
424 self.uart1_fake.pio = bus.master
425 self.uart2_fake.pio = bus.master
426 self.uart3_fake.pio = bus.master
427 self.sp810_fake.pio = bus.master
428 self.watchdog_fake.pio = bus.master
429 self.aaci_fake.pio = bus.master
430 self.lan_fake.pio = bus.master
431 self.usb_fake.pio = bus.master
432 self.mmc_fake.pio = bus.master
433
|