1# Copyright (c) 2009-2011 ARM Limited
| 1# Copyright (c) 2009-2012 ARM Limited
|
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42
43from m5.params import *
44from m5.proxy import *
45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
46from Pci import PciConfigAll
47from Ethernet import NSGigE, IGbE_e1000, IGbE_igb
48from Ide import *
49from Platform import Platform
50from Terminal import Terminal
51from Uart import Uart
| 2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42
43from m5.params import *
44from m5.proxy import *
45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
46from Pci import PciConfigAll
47from Ethernet import NSGigE, IGbE_e1000, IGbE_igb
48from Ide import *
49from Platform import Platform
50from Terminal import Terminal
51from Uart import Uart
|
| 52from PhysicalMemory import *
|
52
53class AmbaDevice(BasicPioDevice):
54 type = 'AmbaDevice'
55 abstract = True
56 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
57
58class AmbaIntDevice(AmbaDevice):
59 type = 'AmbaIntDevice'
60 abstract = True
61 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
62 int_num = Param.UInt32("Interrupt number that connects to GIC")
63 int_delay = Param.Latency("100ns",
64 "Time between action and interrupt generation by device")
65
66class AmbaDmaDevice(DmaDevice):
67 type = 'AmbaDmaDevice'
68 abstract = True
69 pio_addr = Param.Addr("Address for AMBA slave interface")
70 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
71 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
72 int_num = Param.UInt32("Interrupt number that connects to GIC")
73 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
74
75class A9SCU(BasicPioDevice):
76 type = 'A9SCU'
77
78class RealViewCtrl(BasicPioDevice):
79 type = 'RealViewCtrl'
80 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
81 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
82 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
83
84class Gic(PioDevice):
85 type = 'Gic'
86 platform = Param.Platform(Parent.any, "Platform this device is part of.")
87 dist_addr = Param.Addr(0x1f001000, "Address for distributor")
88 cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
89 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
90 cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
91 int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
92 it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
93
94class AmbaFake(AmbaDevice):
95 type = 'AmbaFake'
96 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
97 amba_id = 0;
98
99class Pl011(Uart):
100 type = 'Pl011'
101 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
102 int_num = Param.UInt32("Interrupt number that connects to GIC")
103 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
104 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
105
106class Sp804(AmbaDevice):
107 type = 'Sp804'
108 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
109 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
110 clock0 = Param.Clock('1MHz', "Clock speed of the input")
111 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
112 clock1 = Param.Clock('1MHz', "Clock speed of the input")
113 amba_id = 0x00141804
114
115class CpuLocalTimer(BasicPioDevice):
116 type = 'CpuLocalTimer'
117 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
118 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
119 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
120 clock = Param.Clock('1GHz', "Clock speed at which the timer counts")
121
| 53
54class AmbaDevice(BasicPioDevice):
55 type = 'AmbaDevice'
56 abstract = True
57 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
58
59class AmbaIntDevice(AmbaDevice):
60 type = 'AmbaIntDevice'
61 abstract = True
62 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
63 int_num = Param.UInt32("Interrupt number that connects to GIC")
64 int_delay = Param.Latency("100ns",
65 "Time between action and interrupt generation by device")
66
67class AmbaDmaDevice(DmaDevice):
68 type = 'AmbaDmaDevice'
69 abstract = True
70 pio_addr = Param.Addr("Address for AMBA slave interface")
71 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
72 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
73 int_num = Param.UInt32("Interrupt number that connects to GIC")
74 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
75
76class A9SCU(BasicPioDevice):
77 type = 'A9SCU'
78
79class RealViewCtrl(BasicPioDevice):
80 type = 'RealViewCtrl'
81 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
82 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
83 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
84
85class Gic(PioDevice):
86 type = 'Gic'
87 platform = Param.Platform(Parent.any, "Platform this device is part of.")
88 dist_addr = Param.Addr(0x1f001000, "Address for distributor")
89 cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
90 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
91 cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
92 int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
93 it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
94
95class AmbaFake(AmbaDevice):
96 type = 'AmbaFake'
97 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
98 amba_id = 0;
99
100class Pl011(Uart):
101 type = 'Pl011'
102 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
103 int_num = Param.UInt32("Interrupt number that connects to GIC")
104 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
105 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
106
107class Sp804(AmbaDevice):
108 type = 'Sp804'
109 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
110 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
111 clock0 = Param.Clock('1MHz', "Clock speed of the input")
112 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
113 clock1 = Param.Clock('1MHz', "Clock speed of the input")
114 amba_id = 0x00141804
115
116class CpuLocalTimer(BasicPioDevice):
117 type = 'CpuLocalTimer'
118 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
119 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
120 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
121 clock = Param.Clock('1GHz', "Clock speed at which the timer counts")
122
|
| 123class PL031(AmbaIntDevice):
124 type = 'PL031'
125 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
126 amba_id = 0x00341031
127
|
122class Pl050(AmbaIntDevice):
123 type = 'Pl050'
124 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display")
125 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
126 int_delay = '1us'
127 amba_id = 0x00141050
128
129class Pl111(AmbaDmaDevice):
130 type = 'Pl111'
131 clock = Param.Clock('24MHz', "Clock speed of the input")
132 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display")
133 amba_id = 0x00141111
134
135class RealView(Platform):
136 type = 'RealView'
137 system = Param.System(Parent.any, "system")
138 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
| 128class Pl050(AmbaIntDevice):
129 type = 'Pl050'
130 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display")
131 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
132 int_delay = '1us'
133 amba_id = 0x00141050
134
135class Pl111(AmbaDmaDevice):
136 type = 'Pl111'
137 clock = Param.Clock('24MHz', "Clock speed of the input")
138 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display")
139 amba_id = 0x00141111
140
141class RealView(Platform):
142 type = 'RealView'
143 system = Param.System(Parent.any, "system")
144 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
|
| 145 mem_start_addr = Param.Addr(0, "Start address of main memory")
146 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform")
|
139
| 147
|
| 148 def setupBootLoader(self, mem_bus, cur_sys, loc):
149 self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'), size = '64MB'), zero = True)
150 self.nvmem.port = mem_bus.master
151 cur_sys.boot_loader = loc('boot.arm')
152 cur_sys.boot_loader_mem = self.nvmem
153
154
|
140# Reference for memory map and interrupt number
141# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
142# Chapter 4: Programmer's Reference
143class RealViewPBX(RealView):
144 uart = Pl011(pio_addr=0x10009000, int_num=44)
145 realview_io = RealViewCtrl(pio_addr=0x10000000)
146 gic = Gic()
147 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
148 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
149 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600)
150 clcd = Pl111(pio_addr=0x10020000, int_num=55)
151 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
152 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
153 a9scu = A9SCU(pio_addr=0x1f000000)
154 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
155 io_shift = 1, ctrl_offset = 2, Command = 0x1,
156 BAR0 = 0x18000000, BAR0Size = '16B',
157 BAR1 = 0x18000100, BAR1Size = '1B',
158 BAR0LegacyIO = True, BAR1LegacyIO = True)
159
160
161 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
162 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
163 fake_mem=True)
164 dmac_fake = AmbaFake(pio_addr=0x10030000)
165 uart1_fake = AmbaFake(pio_addr=0x1000a000)
166 uart2_fake = AmbaFake(pio_addr=0x1000b000)
167 uart3_fake = AmbaFake(pio_addr=0x1000c000)
168 smc_fake = AmbaFake(pio_addr=0x100e1000)
169 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
170 watchdog_fake = AmbaFake(pio_addr=0x10010000)
171 gpio0_fake = AmbaFake(pio_addr=0x10013000)
172 gpio1_fake = AmbaFake(pio_addr=0x10014000)
173 gpio2_fake = AmbaFake(pio_addr=0x10015000)
174 ssp_fake = AmbaFake(pio_addr=0x1000d000)
175 sci_fake = AmbaFake(pio_addr=0x1000e000)
176 aaci_fake = AmbaFake(pio_addr=0x10004000)
177 mmc_fake = AmbaFake(pio_addr=0x10005000)
178 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
179
180
181 # Attach I/O devices that are on chip and also set the appropriate
182 # ranges for the bridge
183 def attachOnChipIO(self, bus, bridge):
184 self.gic.pio = bus.master
185 self.l2x0_fake.pio = bus.master
186 self.a9scu.pio = bus.master
187 self.local_cpu_timer.pio = bus.master
188 # Bridge ranges based on excluding what is part of on-chip I/O
189 # (gic, l2x0, a9scu, local_cpu_timer)
190 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
191 self.a9scu.pio_addr - 1),
| 155# Reference for memory map and interrupt number
156# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
157# Chapter 4: Programmer's Reference
158class RealViewPBX(RealView):
159 uart = Pl011(pio_addr=0x10009000, int_num=44)
160 realview_io = RealViewCtrl(pio_addr=0x10000000)
161 gic = Gic()
162 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
163 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
164 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600)
165 clcd = Pl111(pio_addr=0x10020000, int_num=55)
166 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
167 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
168 a9scu = A9SCU(pio_addr=0x1f000000)
169 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
170 io_shift = 1, ctrl_offset = 2, Command = 0x1,
171 BAR0 = 0x18000000, BAR0Size = '16B',
172 BAR1 = 0x18000100, BAR1Size = '1B',
173 BAR0LegacyIO = True, BAR1LegacyIO = True)
174
175
176 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
177 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
178 fake_mem=True)
179 dmac_fake = AmbaFake(pio_addr=0x10030000)
180 uart1_fake = AmbaFake(pio_addr=0x1000a000)
181 uart2_fake = AmbaFake(pio_addr=0x1000b000)
182 uart3_fake = AmbaFake(pio_addr=0x1000c000)
183 smc_fake = AmbaFake(pio_addr=0x100e1000)
184 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
185 watchdog_fake = AmbaFake(pio_addr=0x10010000)
186 gpio0_fake = AmbaFake(pio_addr=0x10013000)
187 gpio1_fake = AmbaFake(pio_addr=0x10014000)
188 gpio2_fake = AmbaFake(pio_addr=0x10015000)
189 ssp_fake = AmbaFake(pio_addr=0x1000d000)
190 sci_fake = AmbaFake(pio_addr=0x1000e000)
191 aaci_fake = AmbaFake(pio_addr=0x10004000)
192 mmc_fake = AmbaFake(pio_addr=0x10005000)
193 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
194
195
196 # Attach I/O devices that are on chip and also set the appropriate
197 # ranges for the bridge
198 def attachOnChipIO(self, bus, bridge):
199 self.gic.pio = bus.master
200 self.l2x0_fake.pio = bus.master
201 self.a9scu.pio = bus.master
202 self.local_cpu_timer.pio = bus.master
203 # Bridge ranges based on excluding what is part of on-chip I/O
204 # (gic, l2x0, a9scu, local_cpu_timer)
205 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
206 self.a9scu.pio_addr - 1),
|
192 AddrRange(self.flash_fake.pio_addr, Addr.max)]
| 207 AddrRange(self.flash_fake.pio_addr,
208 self.flash_fake.pio_addr + \
209 self.flash_fake.pio_size - 1)]
|
193
194 # Attach I/O devices to specified bus object. Can't do this
195 # earlier, since the bus object itself is typically defined at the
196 # System level.
197 def attachIO(self, bus):
198 self.uart.pio = bus.master
199 self.realview_io.pio = bus.master
200 self.timer0.pio = bus.master
201 self.timer1.pio = bus.master
202 self.clcd.pio = bus.master
203 self.clcd.dma = bus.slave
204 self.kmi0.pio = bus.master
205 self.kmi1.pio = bus.master
206 self.cf_ctrl.pio = bus.master
207 self.cf_ctrl.config = bus.master
208 self.cf_ctrl.dma = bus.slave
209 self.dmac_fake.pio = bus.master
210 self.uart1_fake.pio = bus.master
211 self.uart2_fake.pio = bus.master
212 self.uart3_fake.pio = bus.master
213 self.smc_fake.pio = bus.master
214 self.sp810_fake.pio = bus.master
215 self.watchdog_fake.pio = bus.master
216 self.gpio0_fake.pio = bus.master
217 self.gpio1_fake.pio = bus.master
218 self.gpio2_fake.pio = bus.master
219 self.ssp_fake.pio = bus.master
220 self.sci_fake.pio = bus.master
221 self.aaci_fake.pio = bus.master
222 self.mmc_fake.pio = bus.master
223 self.rtc_fake.pio = bus.master
224 self.flash_fake.pio = bus.master
225
226# Reference for memory map and interrupt number
227# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
228# Chapter 4: Programmer's Reference
229class RealViewEB(RealView):
230 uart = Pl011(pio_addr=0x10009000, int_num=44)
231 realview_io = RealViewCtrl(pio_addr=0x10000000)
232 gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000)
233 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
234 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
235 clcd = Pl111(pio_addr=0x10020000, int_num=23)
236 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
237 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
238
239 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
240 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
241 fake_mem=True)
242 dmac_fake = AmbaFake(pio_addr=0x10030000)
243 uart1_fake = AmbaFake(pio_addr=0x1000a000)
244 uart2_fake = AmbaFake(pio_addr=0x1000b000)
245 uart3_fake = AmbaFake(pio_addr=0x1000c000)
246 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
247 smc_fake = AmbaFake(pio_addr=0x100e1000)
248 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
249 watchdog_fake = AmbaFake(pio_addr=0x10010000)
250 gpio0_fake = AmbaFake(pio_addr=0x10013000)
251 gpio1_fake = AmbaFake(pio_addr=0x10014000)
252 gpio2_fake = AmbaFake(pio_addr=0x10015000)
253 ssp_fake = AmbaFake(pio_addr=0x1000d000)
254 sci_fake = AmbaFake(pio_addr=0x1000e000)
255 aaci_fake = AmbaFake(pio_addr=0x10004000)
256 mmc_fake = AmbaFake(pio_addr=0x10005000)
257 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
258
259
260
261 # Attach I/O devices that are on chip and also set the appropriate
262 # ranges for the bridge
263 def attachOnChipIO(self, bus, bridge):
264 self.gic.pio = bus.master
265 self.l2x0_fake.pio = bus.master
266 # Bridge ranges based on excluding what is part of on-chip I/O
267 # (gic, l2x0)
268 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
269 self.gic.cpu_addr - 1),
270 AddrRange(self.flash_fake.pio_addr, Addr.max)]
271
272 # Attach I/O devices to specified bus object. Can't do this
273 # earlier, since the bus object itself is typically defined at the
274 # System level.
275 def attachIO(self, bus):
276 self.uart.pio = bus.master
277 self.realview_io.pio = bus.master
278 self.timer0.pio = bus.master
279 self.timer1.pio = bus.master
280 self.clcd.pio = bus.master
281 self.clcd.dma = bus.slave
282 self.kmi0.pio = bus.master
283 self.kmi1.pio = bus.master
284 self.dmac_fake.pio = bus.master
285 self.uart1_fake.pio = bus.master
286 self.uart2_fake.pio = bus.master
287 self.uart3_fake.pio = bus.master
288 self.smc_fake.pio = bus.master
289 self.sp810_fake.pio = bus.master
290 self.watchdog_fake.pio = bus.master
291 self.gpio0_fake.pio = bus.master
292 self.gpio1_fake.pio = bus.master
293 self.gpio2_fake.pio = bus.master
294 self.ssp_fake.pio = bus.master
295 self.sci_fake.pio = bus.master
296 self.aaci_fake.pio = bus.master
297 self.mmc_fake.pio = bus.master
298 self.rtc_fake.pio = bus.master
299 self.flash_fake.pio = bus.master
300 self.smcreg_fake.pio = bus.master
301
302class VExpress_ELT(RealView):
| 210
211 # Attach I/O devices to specified bus object. Can't do this
212 # earlier, since the bus object itself is typically defined at the
213 # System level.
214 def attachIO(self, bus):
215 self.uart.pio = bus.master
216 self.realview_io.pio = bus.master
217 self.timer0.pio = bus.master
218 self.timer1.pio = bus.master
219 self.clcd.pio = bus.master
220 self.clcd.dma = bus.slave
221 self.kmi0.pio = bus.master
222 self.kmi1.pio = bus.master
223 self.cf_ctrl.pio = bus.master
224 self.cf_ctrl.config = bus.master
225 self.cf_ctrl.dma = bus.slave
226 self.dmac_fake.pio = bus.master
227 self.uart1_fake.pio = bus.master
228 self.uart2_fake.pio = bus.master
229 self.uart3_fake.pio = bus.master
230 self.smc_fake.pio = bus.master
231 self.sp810_fake.pio = bus.master
232 self.watchdog_fake.pio = bus.master
233 self.gpio0_fake.pio = bus.master
234 self.gpio1_fake.pio = bus.master
235 self.gpio2_fake.pio = bus.master
236 self.ssp_fake.pio = bus.master
237 self.sci_fake.pio = bus.master
238 self.aaci_fake.pio = bus.master
239 self.mmc_fake.pio = bus.master
240 self.rtc_fake.pio = bus.master
241 self.flash_fake.pio = bus.master
242
243# Reference for memory map and interrupt number
244# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
245# Chapter 4: Programmer's Reference
246class RealViewEB(RealView):
247 uart = Pl011(pio_addr=0x10009000, int_num=44)
248 realview_io = RealViewCtrl(pio_addr=0x10000000)
249 gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000)
250 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
251 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
252 clcd = Pl111(pio_addr=0x10020000, int_num=23)
253 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
254 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
255
256 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
257 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
258 fake_mem=True)
259 dmac_fake = AmbaFake(pio_addr=0x10030000)
260 uart1_fake = AmbaFake(pio_addr=0x1000a000)
261 uart2_fake = AmbaFake(pio_addr=0x1000b000)
262 uart3_fake = AmbaFake(pio_addr=0x1000c000)
263 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
264 smc_fake = AmbaFake(pio_addr=0x100e1000)
265 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
266 watchdog_fake = AmbaFake(pio_addr=0x10010000)
267 gpio0_fake = AmbaFake(pio_addr=0x10013000)
268 gpio1_fake = AmbaFake(pio_addr=0x10014000)
269 gpio2_fake = AmbaFake(pio_addr=0x10015000)
270 ssp_fake = AmbaFake(pio_addr=0x1000d000)
271 sci_fake = AmbaFake(pio_addr=0x1000e000)
272 aaci_fake = AmbaFake(pio_addr=0x10004000)
273 mmc_fake = AmbaFake(pio_addr=0x10005000)
274 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
275
276
277
278 # Attach I/O devices that are on chip and also set the appropriate
279 # ranges for the bridge
280 def attachOnChipIO(self, bus, bridge):
281 self.gic.pio = bus.master
282 self.l2x0_fake.pio = bus.master
283 # Bridge ranges based on excluding what is part of on-chip I/O
284 # (gic, l2x0)
285 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
286 self.gic.cpu_addr - 1),
287 AddrRange(self.flash_fake.pio_addr, Addr.max)]
288
289 # Attach I/O devices to specified bus object. Can't do this
290 # earlier, since the bus object itself is typically defined at the
291 # System level.
292 def attachIO(self, bus):
293 self.uart.pio = bus.master
294 self.realview_io.pio = bus.master
295 self.timer0.pio = bus.master
296 self.timer1.pio = bus.master
297 self.clcd.pio = bus.master
298 self.clcd.dma = bus.slave
299 self.kmi0.pio = bus.master
300 self.kmi1.pio = bus.master
301 self.dmac_fake.pio = bus.master
302 self.uart1_fake.pio = bus.master
303 self.uart2_fake.pio = bus.master
304 self.uart3_fake.pio = bus.master
305 self.smc_fake.pio = bus.master
306 self.sp810_fake.pio = bus.master
307 self.watchdog_fake.pio = bus.master
308 self.gpio0_fake.pio = bus.master
309 self.gpio1_fake.pio = bus.master
310 self.gpio2_fake.pio = bus.master
311 self.ssp_fake.pio = bus.master
312 self.sci_fake.pio = bus.master
313 self.aaci_fake.pio = bus.master
314 self.mmc_fake.pio = bus.master
315 self.rtc_fake.pio = bus.master
316 self.flash_fake.pio = bus.master
317 self.smcreg_fake.pio = bus.master
318
319class VExpress_ELT(RealView):
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| 320 max_mem_size = '2GB'
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303 pci_cfg_base = 0xD0000000
304 elba_uart = Pl011(pio_addr=0xE0009000, int_num=42)
305 uart = Pl011(pio_addr=0xFF009000, int_num=121)
306 realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000)
307 gic = Gic(dist_addr=0xE0201000, cpu_addr=0xE0200100)
308 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0xE0200600)
309 v2m_timer0 = Sp804(int_num0=120, int_num1=120, pio_addr=0xFF011000)
310 v2m_timer1 = Sp804(int_num0=121, int_num1=121, pio_addr=0xFF012000)
311 elba_timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0xE0011000, clock0='50MHz', clock1='50MHz')
312 elba_timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0xE0012000, clock0='50MHz', clock1='50MHz')
313 clcd = Pl111(pio_addr=0xE0022000, int_num=46) # CLCD interrupt no. unknown
314 kmi0 = Pl050(pio_addr=0xFF006000, int_num=124)
315 kmi1 = Pl050(pio_addr=0xFF007000, int_num=125)
316 elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52)
317 elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53)
318 a9scu = A9SCU(pio_addr=0xE0200000)
319 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
320 io_shift = 2, ctrl_offset = 2, Command = 0x1,
321 BAR0 = 0xFF01A000, BAR0Size = '256B',
322 BAR1 = 0xFF01A100, BAR1Size = '4096B',
323 BAR0LegacyIO = True, BAR1LegacyIO = True)
324
325 pciconfig = PciConfigAll()
326 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
327 InterruptLine=1, InterruptPin=1)
328
329 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
330 InterruptLine=2, InterruptPin=2)
331
332 l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff)
333 dmac_fake = AmbaFake(pio_addr=0xE0020000)
334 uart1_fake = AmbaFake(pio_addr=0xE000A000)
335 uart2_fake = AmbaFake(pio_addr=0xE000B000)
336 uart3_fake = AmbaFake(pio_addr=0xE000C000)
337 smc_fake = AmbaFake(pio_addr=0xEC000000)
338 sp810_fake = AmbaFake(pio_addr=0xFF001000, ignore_access=True)
339 watchdog_fake = AmbaFake(pio_addr=0xE0010000)
340 aaci_fake = AmbaFake(pio_addr=0xFF004000)
341 elba_aaci_fake = AmbaFake(pio_addr=0xE0004000)
342 mmc_fake = AmbaFake(pio_addr=0xE0005000) # not sure if we need this
343 rtc_fake = AmbaFake(pio_addr=0xE0017000, amba_id=0x41031)
344 spsc_fake = IsaFake(pio_addr=0xE001B000, pio_size=0x2000)
345 lan_fake = IsaFake(pio_addr=0xFA000000, pio_size=0xffff)
346 usb_fake = IsaFake(pio_addr=0xFB000000, pio_size=0x1ffff)
347
348
349 # Attach I/O devices that are on chip and also set the appropriate
350 # ranges for the bridge
351 def attachOnChipIO(self, bus, bridge):
352 self.gic.pio = bus.master
353 self.a9scu.pio = bus.master
354 self.local_cpu_timer.pio = bus.master
355 # Bridge ranges based on excluding what is part of on-chip I/O
356 # (gic, a9scu)
357 bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1),
358 AddrRange(self.l2x0_fake.pio_addr, Addr.max)]
359
360 # Attach I/O devices to specified bus object. Can't do this
361 # earlier, since the bus object itself is typically defined at the
362 # System level.
363 def attachIO(self, bus):
364 self.elba_uart.pio = bus.master
365 self.uart.pio = bus.master
366 self.realview_io.pio = bus.master
367 self.v2m_timer0.pio = bus.master
368 self.v2m_timer1.pio = bus.master
369 self.elba_timer0.pio = bus.master
370 self.elba_timer1.pio = bus.master
371 self.clcd.pio = bus.master
372 self.clcd.dma = bus.slave
373 self.kmi0.pio = bus.master
374 self.kmi1.pio = bus.master
375 self.elba_kmi0.pio = bus.master
376 self.elba_kmi1.pio = bus.master
377 self.cf_ctrl.pio = bus.master
378 self.cf_ctrl.config = bus.master
379 self.cf_ctrl.dma = bus.slave
380 self.ide.pio = bus.master
381 self.ide.config = bus.master
382 self.ide.dma = bus.slave
383 self.ethernet.pio = bus.master
384 self.ethernet.config = bus.master
385 self.ethernet.dma = bus.slave
386 self.pciconfig.pio = bus.default
387 bus.use_default_range = True
388
389 self.l2x0_fake.pio = bus.master
390 self.dmac_fake.pio = bus.master
391 self.uart1_fake.pio = bus.master
392 self.uart2_fake.pio = bus.master
393 self.uart3_fake.pio = bus.master
394 self.smc_fake.pio = bus.master
395 self.sp810_fake.pio = bus.master
396 self.watchdog_fake.pio = bus.master
397 self.aaci_fake.pio = bus.master
398 self.elba_aaci_fake.pio = bus.master
399 self.mmc_fake.pio = bus.master
400 self.rtc_fake.pio = bus.master
401 self.spsc_fake.pio = bus.master
402 self.lan_fake.pio = bus.master
403 self.usb_fake.pio = bus.master
404
| 321 pci_cfg_base = 0xD0000000
322 elba_uart = Pl011(pio_addr=0xE0009000, int_num=42)
323 uart = Pl011(pio_addr=0xFF009000, int_num=121)
324 realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000)
325 gic = Gic(dist_addr=0xE0201000, cpu_addr=0xE0200100)
326 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0xE0200600)
327 v2m_timer0 = Sp804(int_num0=120, int_num1=120, pio_addr=0xFF011000)
328 v2m_timer1 = Sp804(int_num0=121, int_num1=121, pio_addr=0xFF012000)
329 elba_timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0xE0011000, clock0='50MHz', clock1='50MHz')
330 elba_timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0xE0012000, clock0='50MHz', clock1='50MHz')
331 clcd = Pl111(pio_addr=0xE0022000, int_num=46) # CLCD interrupt no. unknown
332 kmi0 = Pl050(pio_addr=0xFF006000, int_num=124)
333 kmi1 = Pl050(pio_addr=0xFF007000, int_num=125)
334 elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52)
335 elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53)
336 a9scu = A9SCU(pio_addr=0xE0200000)
337 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
338 io_shift = 2, ctrl_offset = 2, Command = 0x1,
339 BAR0 = 0xFF01A000, BAR0Size = '256B',
340 BAR1 = 0xFF01A100, BAR1Size = '4096B',
341 BAR0LegacyIO = True, BAR1LegacyIO = True)
342
343 pciconfig = PciConfigAll()
344 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
345 InterruptLine=1, InterruptPin=1)
346
347 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
348 InterruptLine=2, InterruptPin=2)
349
350 l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff)
351 dmac_fake = AmbaFake(pio_addr=0xE0020000)
352 uart1_fake = AmbaFake(pio_addr=0xE000A000)
353 uart2_fake = AmbaFake(pio_addr=0xE000B000)
354 uart3_fake = AmbaFake(pio_addr=0xE000C000)
355 smc_fake = AmbaFake(pio_addr=0xEC000000)
356 sp810_fake = AmbaFake(pio_addr=0xFF001000, ignore_access=True)
357 watchdog_fake = AmbaFake(pio_addr=0xE0010000)
358 aaci_fake = AmbaFake(pio_addr=0xFF004000)
359 elba_aaci_fake = AmbaFake(pio_addr=0xE0004000)
360 mmc_fake = AmbaFake(pio_addr=0xE0005000) # not sure if we need this
361 rtc_fake = AmbaFake(pio_addr=0xE0017000, amba_id=0x41031)
362 spsc_fake = IsaFake(pio_addr=0xE001B000, pio_size=0x2000)
363 lan_fake = IsaFake(pio_addr=0xFA000000, pio_size=0xffff)
364 usb_fake = IsaFake(pio_addr=0xFB000000, pio_size=0x1ffff)
365
366
367 # Attach I/O devices that are on chip and also set the appropriate
368 # ranges for the bridge
369 def attachOnChipIO(self, bus, bridge):
370 self.gic.pio = bus.master
371 self.a9scu.pio = bus.master
372 self.local_cpu_timer.pio = bus.master
373 # Bridge ranges based on excluding what is part of on-chip I/O
374 # (gic, a9scu)
375 bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1),
376 AddrRange(self.l2x0_fake.pio_addr, Addr.max)]
377
378 # Attach I/O devices to specified bus object. Can't do this
379 # earlier, since the bus object itself is typically defined at the
380 # System level.
381 def attachIO(self, bus):
382 self.elba_uart.pio = bus.master
383 self.uart.pio = bus.master
384 self.realview_io.pio = bus.master
385 self.v2m_timer0.pio = bus.master
386 self.v2m_timer1.pio = bus.master
387 self.elba_timer0.pio = bus.master
388 self.elba_timer1.pio = bus.master
389 self.clcd.pio = bus.master
390 self.clcd.dma = bus.slave
391 self.kmi0.pio = bus.master
392 self.kmi1.pio = bus.master
393 self.elba_kmi0.pio = bus.master
394 self.elba_kmi1.pio = bus.master
395 self.cf_ctrl.pio = bus.master
396 self.cf_ctrl.config = bus.master
397 self.cf_ctrl.dma = bus.slave
398 self.ide.pio = bus.master
399 self.ide.config = bus.master
400 self.ide.dma = bus.slave
401 self.ethernet.pio = bus.master
402 self.ethernet.config = bus.master
403 self.ethernet.dma = bus.slave
404 self.pciconfig.pio = bus.default
405 bus.use_default_range = True
406
407 self.l2x0_fake.pio = bus.master
408 self.dmac_fake.pio = bus.master
409 self.uart1_fake.pio = bus.master
410 self.uart2_fake.pio = bus.master
411 self.uart3_fake.pio = bus.master
412 self.smc_fake.pio = bus.master
413 self.sp810_fake.pio = bus.master
414 self.watchdog_fake.pio = bus.master
415 self.aaci_fake.pio = bus.master
416 self.elba_aaci_fake.pio = bus.master
417 self.mmc_fake.pio = bus.master
418 self.rtc_fake.pio = bus.master
419 self.spsc_fake.pio = bus.master
420 self.lan_fake.pio = bus.master
421 self.usb_fake.pio = bus.master
422
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| 423
424class VExpress_EMM(RealView):
425 mem_start_addr = '2GB'
426 max_mem_size = '2GB'
427 uart = Pl011(pio_addr=0x1c090000, int_num=37)
428 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000)
429 gic = Gic(dist_addr=0x2C001000, cpu_addr=0x2C002000)
430 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000)
431 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='50MHz', clock1='50MHz')
432 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='50MHz', clock1='50MHz')
433 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
434 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
435 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45)
436 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
437 io_shift = 2, ctrl_offset = 2, Command = 0x1,
438 BAR0 = 0x1C1A0000, BAR0Size = '256B',
439 BAR1 = 0x1C1A0100, BAR1Size = '4096B',
440 BAR0LegacyIO = True, BAR1LegacyIO = True)
441 vram = PhysicalMemory(range = AddrRange(0x18000000, size='32MB'), zero = True)
442 rtc = PL031(pio_addr=0x1C170000, int_num=36)
443
444 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
445 uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
446 uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
447 uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
448 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
449 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
450 aaci_fake = AmbaFake(pio_addr=0x1C040000)
451 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
452 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
453 mmc_fake = AmbaFake(pio_addr=0x1c050000)
454
455 def setupBootLoader(self, mem_bus, cur_sys, loc):
456 self.nvmem = PhysicalMemory(range = AddrRange(0, size = '64MB'), zero = True)
457 self.nvmem.port = mem_bus.master
458 cur_sys.boot_loader = loc('boot_emm.arm')
459 cur_sys.boot_loader_mem = self.nvmem
460 cur_sys.atags_addr = 0x80000100
461
462 # Attach I/O devices that are on chip and also set the appropriate
463 # ranges for the bridge
464 def attachOnChipIO(self, bus, bridge):
465 self.gic.pio = bus.master
466 self.local_cpu_timer.pio = bus.master
467 # Bridge ranges based on excluding what is part of on-chip I/O
468 # (gic, a9scu)
469 bridge.ranges = [AddrRange(0x2F000000, size='16MB'),
470 AddrRange(0x30000000, size='256MB'),
471 AddrRange(0x40000000, size='512MB'),
472 AddrRange(0x18000000, size='64MB'),
473 AddrRange(0x1C000000, size='64MB')]
474
475 # Attach I/O devices to specified bus object. Can't do this
476 # earlier, since the bus object itself is typically defined at the
477 # System level.
478 def attachIO(self, bus):
479 self.uart.pio = bus.master
480 self.realview_io.pio = bus.master
481 self.timer0.pio = bus.master
482 self.timer1.pio = bus.master
483 self.clcd.pio = bus.master
484 self.clcd.dma = bus.slave
485 self.kmi0.pio = bus.master
486 self.kmi1.pio = bus.master
487 self.cf_ctrl.pio = bus.master
488 self.cf_ctrl.config = bus.master
489 self.rtc.pio = bus.master
490 bus.use_default_range = True
491 self.vram.port = bus.master
492
493 self.l2x0_fake.pio = bus.master
494 self.uart1_fake.pio = bus.master
495 self.uart2_fake.pio = bus.master
496 self.uart3_fake.pio = bus.master
497 self.sp810_fake.pio = bus.master
498 self.watchdog_fake.pio = bus.master
499 self.aaci_fake.pio = bus.master
500 self.lan_fake.pio = bus.master
501 self.usb_fake.pio = bus.master
502 self.mmc_fake.pio = bus.master
503
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