1# Copyright (c) 2009 ARM Limited
| 1# Copyright (c) 2009-2011 ARM Limited
|
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42
43from m5.params import *
44from m5.proxy import *
45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
46from Pci import PciConfigAll
47from Ethernet import NSGigE, IGbE_e1000, IGbE_igb
48from Ide import *
49from Platform import Platform
50from Terminal import Terminal
51from Uart import Uart
52
53class AmbaDevice(BasicPioDevice):
54 type = 'AmbaDevice'
55 abstract = True
56 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
57
58class AmbaIntDevice(AmbaDevice):
59 type = 'AmbaIntDevice'
60 abstract = True
61 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
62 int_num = Param.UInt32("Interrupt number that connects to GIC")
63 int_delay = Param.Latency("100ns",
64 "Time between action and interrupt generation by device")
65
66class AmbaDmaDevice(DmaDevice):
67 type = 'AmbaDmaDevice'
68 abstract = True
69 pio_addr = Param.Addr("Address for AMBA slave interface")
70 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
71 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
72 int_num = Param.UInt32("Interrupt number that connects to GIC")
73 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
74
75class A9SCU(BasicPioDevice):
76 type = 'A9SCU'
77
78class RealViewCtrl(BasicPioDevice):
79 type = 'RealViewCtrl'
80 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
81 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
82 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
83
84class Gic(PioDevice):
85 type = 'Gic'
86 dist_addr = Param.Addr(0x1f001000, "Address for distributor")
87 cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
88 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
89 cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
90 int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
91 it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
92
93class AmbaFake(AmbaDevice):
94 type = 'AmbaFake'
95 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
96 amba_id = 0;
97
98class Pl011(Uart):
99 type = 'Pl011'
100 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
101 int_num = Param.UInt32("Interrupt number that connects to GIC")
102 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
103 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
104
105class Sp804(AmbaDevice):
106 type = 'Sp804'
107 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
108 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
109 clock0 = Param.Clock('1MHz', "Clock speed of the input")
110 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
111 clock1 = Param.Clock('1MHz', "Clock speed of the input")
112 amba_id = 0x00141804
113
114class CpuLocalTimer(BasicPioDevice):
115 type = 'CpuLocalTimer'
116 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
117 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
118 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
119 clock = Param.Clock('1GHz', "Clock speed at which the timer counts")
120
121class Pl050(AmbaIntDevice):
122 type = 'Pl050'
123 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display")
124 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
125 int_delay = '1us'
126 amba_id = 0x00141050
127
128class Pl111(AmbaDmaDevice):
129 type = 'Pl111'
130 clock = Param.Clock('24MHz', "Clock speed of the input")
131 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display")
132 amba_id = 0x00141111
133
134class RealView(Platform):
135 type = 'RealView'
136 system = Param.System(Parent.any, "system")
137 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
138
139# Reference for memory map and interrupt number
140# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
141# Chapter 4: Programmer's Reference
142class RealViewPBX(RealView):
143 uart = Pl011(pio_addr=0x10009000, int_num=44)
144 realview_io = RealViewCtrl(pio_addr=0x10000000)
145 gic = Gic()
146 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
147 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
148 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600)
149 clcd = Pl111(pio_addr=0x10020000, int_num=55)
150 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
151 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
152 a9scu = A9SCU(pio_addr=0x1f000000)
153 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
154 io_shift = 1, ctrl_offset = 2, Command = 0x1,
155 BAR0 = 0x18000000, BAR0Size = '16B',
156 BAR1 = 0x18000100, BAR1Size = '1B',
157 BAR0LegacyIO = True, BAR1LegacyIO = True)
158
159
160 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
161 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
162 fake_mem=True)
163 dmac_fake = AmbaFake(pio_addr=0x10030000)
164 uart1_fake = AmbaFake(pio_addr=0x1000a000)
165 uart2_fake = AmbaFake(pio_addr=0x1000b000)
166 uart3_fake = AmbaFake(pio_addr=0x1000c000)
167 smc_fake = AmbaFake(pio_addr=0x100e1000)
168 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
169 watchdog_fake = AmbaFake(pio_addr=0x10010000)
170 gpio0_fake = AmbaFake(pio_addr=0x10013000)
171 gpio1_fake = AmbaFake(pio_addr=0x10014000)
172 gpio2_fake = AmbaFake(pio_addr=0x10015000)
173 ssp_fake = AmbaFake(pio_addr=0x1000d000)
174 sci_fake = AmbaFake(pio_addr=0x1000e000)
175 aaci_fake = AmbaFake(pio_addr=0x10004000)
176 mmc_fake = AmbaFake(pio_addr=0x10005000)
177 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
178
179
| 2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42
43from m5.params import *
44from m5.proxy import *
45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
46from Pci import PciConfigAll
47from Ethernet import NSGigE, IGbE_e1000, IGbE_igb
48from Ide import *
49from Platform import Platform
50from Terminal import Terminal
51from Uart import Uart
52
53class AmbaDevice(BasicPioDevice):
54 type = 'AmbaDevice'
55 abstract = True
56 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
57
58class AmbaIntDevice(AmbaDevice):
59 type = 'AmbaIntDevice'
60 abstract = True
61 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
62 int_num = Param.UInt32("Interrupt number that connects to GIC")
63 int_delay = Param.Latency("100ns",
64 "Time between action and interrupt generation by device")
65
66class AmbaDmaDevice(DmaDevice):
67 type = 'AmbaDmaDevice'
68 abstract = True
69 pio_addr = Param.Addr("Address for AMBA slave interface")
70 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
71 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
72 int_num = Param.UInt32("Interrupt number that connects to GIC")
73 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
74
75class A9SCU(BasicPioDevice):
76 type = 'A9SCU'
77
78class RealViewCtrl(BasicPioDevice):
79 type = 'RealViewCtrl'
80 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
81 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
82 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
83
84class Gic(PioDevice):
85 type = 'Gic'
86 dist_addr = Param.Addr(0x1f001000, "Address for distributor")
87 cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
88 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
89 cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
90 int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
91 it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
92
93class AmbaFake(AmbaDevice):
94 type = 'AmbaFake'
95 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
96 amba_id = 0;
97
98class Pl011(Uart):
99 type = 'Pl011'
100 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
101 int_num = Param.UInt32("Interrupt number that connects to GIC")
102 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
103 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
104
105class Sp804(AmbaDevice):
106 type = 'Sp804'
107 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
108 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
109 clock0 = Param.Clock('1MHz', "Clock speed of the input")
110 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
111 clock1 = Param.Clock('1MHz', "Clock speed of the input")
112 amba_id = 0x00141804
113
114class CpuLocalTimer(BasicPioDevice):
115 type = 'CpuLocalTimer'
116 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
117 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
118 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
119 clock = Param.Clock('1GHz', "Clock speed at which the timer counts")
120
121class Pl050(AmbaIntDevice):
122 type = 'Pl050'
123 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display")
124 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
125 int_delay = '1us'
126 amba_id = 0x00141050
127
128class Pl111(AmbaDmaDevice):
129 type = 'Pl111'
130 clock = Param.Clock('24MHz', "Clock speed of the input")
131 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display")
132 amba_id = 0x00141111
133
134class RealView(Platform):
135 type = 'RealView'
136 system = Param.System(Parent.any, "system")
137 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
138
139# Reference for memory map and interrupt number
140# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
141# Chapter 4: Programmer's Reference
142class RealViewPBX(RealView):
143 uart = Pl011(pio_addr=0x10009000, int_num=44)
144 realview_io = RealViewCtrl(pio_addr=0x10000000)
145 gic = Gic()
146 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
147 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
148 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600)
149 clcd = Pl111(pio_addr=0x10020000, int_num=55)
150 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
151 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
152 a9scu = A9SCU(pio_addr=0x1f000000)
153 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
154 io_shift = 1, ctrl_offset = 2, Command = 0x1,
155 BAR0 = 0x18000000, BAR0Size = '16B',
156 BAR1 = 0x18000100, BAR1Size = '1B',
157 BAR0LegacyIO = True, BAR1LegacyIO = True)
158
159
160 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
161 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
162 fake_mem=True)
163 dmac_fake = AmbaFake(pio_addr=0x10030000)
164 uart1_fake = AmbaFake(pio_addr=0x1000a000)
165 uart2_fake = AmbaFake(pio_addr=0x1000b000)
166 uart3_fake = AmbaFake(pio_addr=0x1000c000)
167 smc_fake = AmbaFake(pio_addr=0x100e1000)
168 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
169 watchdog_fake = AmbaFake(pio_addr=0x10010000)
170 gpio0_fake = AmbaFake(pio_addr=0x10013000)
171 gpio1_fake = AmbaFake(pio_addr=0x10014000)
172 gpio2_fake = AmbaFake(pio_addr=0x10015000)
173 ssp_fake = AmbaFake(pio_addr=0x1000d000)
174 sci_fake = AmbaFake(pio_addr=0x1000e000)
175 aaci_fake = AmbaFake(pio_addr=0x10004000)
176 mmc_fake = AmbaFake(pio_addr=0x10005000)
177 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
178
179
|
180 # Attach I/O devices that are on chip
181 def attachOnChipIO(self, bus):
| 180 # Attach I/O devices that are on chip and also set the appropriate
181 # ranges for the bridge
182 def attachOnChipIO(self, bus, bridge):
|
182 self.gic.pio = bus.port
183 self.l2x0_fake.pio = bus.port
184 self.a9scu.pio = bus.port
185 self.local_cpu_timer.pio = bus.port
| 183 self.gic.pio = bus.port
184 self.l2x0_fake.pio = bus.port
185 self.a9scu.pio = bus.port
186 self.local_cpu_timer.pio = bus.port
|
| 187 # Bridge ranges based on excluding what is part of on-chip I/O
188 # (gic, l2x0, a9scu, local_cpu_timer)
189 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
190 self.a9scu.pio_addr - 1),
191 AddrRange(self.flash_fake.pio_addr, Addr.max)]
|
186
187 # Attach I/O devices to specified bus object. Can't do this
188 # earlier, since the bus object itself is typically defined at the
189 # System level.
190 def attachIO(self, bus):
191 self.uart.pio = bus.port
192 self.realview_io.pio = bus.port
193 self.timer0.pio = bus.port
194 self.timer1.pio = bus.port
195 self.clcd.pio = bus.port
196 self.kmi0.pio = bus.port
197 self.kmi1.pio = bus.port
198 self.cf_ctrl.pio = bus.port
199 self.dmac_fake.pio = bus.port
200 self.uart1_fake.pio = bus.port
201 self.uart2_fake.pio = bus.port
202 self.uart3_fake.pio = bus.port
203 self.smc_fake.pio = bus.port
204 self.sp810_fake.pio = bus.port
205 self.watchdog_fake.pio = bus.port
206 self.gpio0_fake.pio = bus.port
207 self.gpio1_fake.pio = bus.port
208 self.gpio2_fake.pio = bus.port
209 self.ssp_fake.pio = bus.port
210 self.sci_fake.pio = bus.port
211 self.aaci_fake.pio = bus.port
212 self.mmc_fake.pio = bus.port
213 self.rtc_fake.pio = bus.port
214 self.flash_fake.pio = bus.port
215
216# Reference for memory map and interrupt number
217# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
218# Chapter 4: Programmer's Reference
219class RealViewEB(RealView):
220 uart = Pl011(pio_addr=0x10009000, int_num=44)
221 realview_io = RealViewCtrl(pio_addr=0x10000000)
222 gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000)
223 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
224 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
225 clcd = Pl111(pio_addr=0x10020000, int_num=23)
226 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
227 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
228
229 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
230 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
231 fake_mem=True)
232 dmac_fake = AmbaFake(pio_addr=0x10030000)
233 uart1_fake = AmbaFake(pio_addr=0x1000a000)
234 uart2_fake = AmbaFake(pio_addr=0x1000b000)
235 uart3_fake = AmbaFake(pio_addr=0x1000c000)
236 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
237 smc_fake = AmbaFake(pio_addr=0x100e1000)
238 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
239 watchdog_fake = AmbaFake(pio_addr=0x10010000)
240 gpio0_fake = AmbaFake(pio_addr=0x10013000)
241 gpio1_fake = AmbaFake(pio_addr=0x10014000)
242 gpio2_fake = AmbaFake(pio_addr=0x10015000)
243 ssp_fake = AmbaFake(pio_addr=0x1000d000)
244 sci_fake = AmbaFake(pio_addr=0x1000e000)
245 aaci_fake = AmbaFake(pio_addr=0x10004000)
246 mmc_fake = AmbaFake(pio_addr=0x10005000)
247 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
248
249
250
| 192
193 # Attach I/O devices to specified bus object. Can't do this
194 # earlier, since the bus object itself is typically defined at the
195 # System level.
196 def attachIO(self, bus):
197 self.uart.pio = bus.port
198 self.realview_io.pio = bus.port
199 self.timer0.pio = bus.port
200 self.timer1.pio = bus.port
201 self.clcd.pio = bus.port
202 self.kmi0.pio = bus.port
203 self.kmi1.pio = bus.port
204 self.cf_ctrl.pio = bus.port
205 self.dmac_fake.pio = bus.port
206 self.uart1_fake.pio = bus.port
207 self.uart2_fake.pio = bus.port
208 self.uart3_fake.pio = bus.port
209 self.smc_fake.pio = bus.port
210 self.sp810_fake.pio = bus.port
211 self.watchdog_fake.pio = bus.port
212 self.gpio0_fake.pio = bus.port
213 self.gpio1_fake.pio = bus.port
214 self.gpio2_fake.pio = bus.port
215 self.ssp_fake.pio = bus.port
216 self.sci_fake.pio = bus.port
217 self.aaci_fake.pio = bus.port
218 self.mmc_fake.pio = bus.port
219 self.rtc_fake.pio = bus.port
220 self.flash_fake.pio = bus.port
221
222# Reference for memory map and interrupt number
223# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
224# Chapter 4: Programmer's Reference
225class RealViewEB(RealView):
226 uart = Pl011(pio_addr=0x10009000, int_num=44)
227 realview_io = RealViewCtrl(pio_addr=0x10000000)
228 gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000)
229 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
230 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
231 clcd = Pl111(pio_addr=0x10020000, int_num=23)
232 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
233 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
234
235 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
236 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
237 fake_mem=True)
238 dmac_fake = AmbaFake(pio_addr=0x10030000)
239 uart1_fake = AmbaFake(pio_addr=0x1000a000)
240 uart2_fake = AmbaFake(pio_addr=0x1000b000)
241 uart3_fake = AmbaFake(pio_addr=0x1000c000)
242 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
243 smc_fake = AmbaFake(pio_addr=0x100e1000)
244 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
245 watchdog_fake = AmbaFake(pio_addr=0x10010000)
246 gpio0_fake = AmbaFake(pio_addr=0x10013000)
247 gpio1_fake = AmbaFake(pio_addr=0x10014000)
248 gpio2_fake = AmbaFake(pio_addr=0x10015000)
249 ssp_fake = AmbaFake(pio_addr=0x1000d000)
250 sci_fake = AmbaFake(pio_addr=0x1000e000)
251 aaci_fake = AmbaFake(pio_addr=0x10004000)
252 mmc_fake = AmbaFake(pio_addr=0x10005000)
253 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
254
255
256
|
251 # Attach I/O devices that are on chip
252 def attachOnChipIO(self, bus):
| 257 # Attach I/O devices that are on chip and also set the appropriate
258 # ranges for the bridge
259 def attachOnChipIO(self, bus, bridge):
|
253 self.gic.pio = bus.port
254 self.l2x0_fake.pio = bus.port
| 260 self.gic.pio = bus.port
261 self.l2x0_fake.pio = bus.port
|
| 262 # Bridge ranges based on excluding what is part of on-chip I/O
263 # (gic, l2x0)
264 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
265 self.gic.cpu_addr - 1),
266 AddrRange(self.flash_fake.pio_addr, Addr.max)]
|
255
256 # Attach I/O devices to specified bus object. Can't do this
257 # earlier, since the bus object itself is typically defined at the
258 # System level.
259 def attachIO(self, bus):
260 self.uart.pio = bus.port
261 self.realview_io.pio = bus.port
262 self.timer0.pio = bus.port
263 self.timer1.pio = bus.port
264 self.clcd.pio = bus.port
265 self.kmi0.pio = bus.port
266 self.kmi1.pio = bus.port
267 self.dmac_fake.pio = bus.port
268 self.uart1_fake.pio = bus.port
269 self.uart2_fake.pio = bus.port
270 self.uart3_fake.pio = bus.port
271 self.smc_fake.pio = bus.port
272 self.sp810_fake.pio = bus.port
273 self.watchdog_fake.pio = bus.port
274 self.gpio0_fake.pio = bus.port
275 self.gpio1_fake.pio = bus.port
276 self.gpio2_fake.pio = bus.port
277 self.ssp_fake.pio = bus.port
278 self.sci_fake.pio = bus.port
279 self.aaci_fake.pio = bus.port
280 self.mmc_fake.pio = bus.port
281 self.rtc_fake.pio = bus.port
282 self.flash_fake.pio = bus.port
283 self.smcreg_fake.pio = bus.port
284
285class VExpress_ELT(RealView):
286 pci_cfg_base = 0xD0000000
287 elba_uart = Pl011(pio_addr=0xE0009000, int_num=42)
288 uart = Pl011(pio_addr=0xFF009000, int_num=121)
289 realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000)
290 gic = Gic(dist_addr=0xE0201000, cpu_addr=0xE0200100)
291 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0xE0200600)
292 v2m_timer0 = Sp804(int_num0=120, int_num1=120, pio_addr=0xFF011000)
293 v2m_timer1 = Sp804(int_num0=121, int_num1=121, pio_addr=0xFF012000)
294 elba_timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0xE0011000, clock0='50MHz', clock1='50MHz')
295 elba_timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0xE0012000, clock0='50MHz', clock1='50MHz')
296 clcd = Pl111(pio_addr=0xE0022000, int_num=46) # CLCD interrupt no. unknown
297 kmi0 = Pl050(pio_addr=0xFF006000, int_num=124)
298 kmi1 = Pl050(pio_addr=0xFF007000, int_num=125)
299 elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52)
300 elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53)
301 a9scu = A9SCU(pio_addr=0xE0200000)
302 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
303 io_shift = 2, ctrl_offset = 2, Command = 0x1,
304 BAR0 = 0xFF01A000, BAR0Size = '256B',
305 BAR1 = 0xFF01A100, BAR1Size = '4096B',
306 BAR0LegacyIO = True, BAR1LegacyIO = True)
307
308 pciconfig = PciConfigAll()
309 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
310 InterruptLine=1, InterruptPin=1)
311
312 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
313 InterruptLine=2, InterruptPin=2)
314
315 l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff)
316 dmac_fake = AmbaFake(pio_addr=0xE0020000)
317 uart1_fake = AmbaFake(pio_addr=0xE000A000)
318 uart2_fake = AmbaFake(pio_addr=0xE000B000)
319 uart3_fake = AmbaFake(pio_addr=0xE000C000)
320 smc_fake = AmbaFake(pio_addr=0xEC000000)
321 sp810_fake = AmbaFake(pio_addr=0xFF001000, ignore_access=True)
322 watchdog_fake = AmbaFake(pio_addr=0xE0010000)
323 aaci_fake = AmbaFake(pio_addr=0xFF004000)
324 elba_aaci_fake = AmbaFake(pio_addr=0xE0004000)
325 mmc_fake = AmbaFake(pio_addr=0xE0005000) # not sure if we need this
326 rtc_fake = AmbaFake(pio_addr=0xE0017000, amba_id=0x41031)
327 spsc_fake = IsaFake(pio_addr=0xE001B000, pio_size=0x2000)
328 lan_fake = IsaFake(pio_addr=0xFA000000, pio_size=0xffff)
329 usb_fake = IsaFake(pio_addr=0xFB000000, pio_size=0x1ffff)
330
331
| 267
268 # Attach I/O devices to specified bus object. Can't do this
269 # earlier, since the bus object itself is typically defined at the
270 # System level.
271 def attachIO(self, bus):
272 self.uart.pio = bus.port
273 self.realview_io.pio = bus.port
274 self.timer0.pio = bus.port
275 self.timer1.pio = bus.port
276 self.clcd.pio = bus.port
277 self.kmi0.pio = bus.port
278 self.kmi1.pio = bus.port
279 self.dmac_fake.pio = bus.port
280 self.uart1_fake.pio = bus.port
281 self.uart2_fake.pio = bus.port
282 self.uart3_fake.pio = bus.port
283 self.smc_fake.pio = bus.port
284 self.sp810_fake.pio = bus.port
285 self.watchdog_fake.pio = bus.port
286 self.gpio0_fake.pio = bus.port
287 self.gpio1_fake.pio = bus.port
288 self.gpio2_fake.pio = bus.port
289 self.ssp_fake.pio = bus.port
290 self.sci_fake.pio = bus.port
291 self.aaci_fake.pio = bus.port
292 self.mmc_fake.pio = bus.port
293 self.rtc_fake.pio = bus.port
294 self.flash_fake.pio = bus.port
295 self.smcreg_fake.pio = bus.port
296
297class VExpress_ELT(RealView):
298 pci_cfg_base = 0xD0000000
299 elba_uart = Pl011(pio_addr=0xE0009000, int_num=42)
300 uart = Pl011(pio_addr=0xFF009000, int_num=121)
301 realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000)
302 gic = Gic(dist_addr=0xE0201000, cpu_addr=0xE0200100)
303 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0xE0200600)
304 v2m_timer0 = Sp804(int_num0=120, int_num1=120, pio_addr=0xFF011000)
305 v2m_timer1 = Sp804(int_num0=121, int_num1=121, pio_addr=0xFF012000)
306 elba_timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0xE0011000, clock0='50MHz', clock1='50MHz')
307 elba_timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0xE0012000, clock0='50MHz', clock1='50MHz')
308 clcd = Pl111(pio_addr=0xE0022000, int_num=46) # CLCD interrupt no. unknown
309 kmi0 = Pl050(pio_addr=0xFF006000, int_num=124)
310 kmi1 = Pl050(pio_addr=0xFF007000, int_num=125)
311 elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52)
312 elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53)
313 a9scu = A9SCU(pio_addr=0xE0200000)
314 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
315 io_shift = 2, ctrl_offset = 2, Command = 0x1,
316 BAR0 = 0xFF01A000, BAR0Size = '256B',
317 BAR1 = 0xFF01A100, BAR1Size = '4096B',
318 BAR0LegacyIO = True, BAR1LegacyIO = True)
319
320 pciconfig = PciConfigAll()
321 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
322 InterruptLine=1, InterruptPin=1)
323
324 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
325 InterruptLine=2, InterruptPin=2)
326
327 l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff)
328 dmac_fake = AmbaFake(pio_addr=0xE0020000)
329 uart1_fake = AmbaFake(pio_addr=0xE000A000)
330 uart2_fake = AmbaFake(pio_addr=0xE000B000)
331 uart3_fake = AmbaFake(pio_addr=0xE000C000)
332 smc_fake = AmbaFake(pio_addr=0xEC000000)
333 sp810_fake = AmbaFake(pio_addr=0xFF001000, ignore_access=True)
334 watchdog_fake = AmbaFake(pio_addr=0xE0010000)
335 aaci_fake = AmbaFake(pio_addr=0xFF004000)
336 elba_aaci_fake = AmbaFake(pio_addr=0xE0004000)
337 mmc_fake = AmbaFake(pio_addr=0xE0005000) # not sure if we need this
338 rtc_fake = AmbaFake(pio_addr=0xE0017000, amba_id=0x41031)
339 spsc_fake = IsaFake(pio_addr=0xE001B000, pio_size=0x2000)
340 lan_fake = IsaFake(pio_addr=0xFA000000, pio_size=0xffff)
341 usb_fake = IsaFake(pio_addr=0xFB000000, pio_size=0x1ffff)
342
343
|
332 # Attach I/O devices that are on chip
333 def attachOnChipIO(self, bus):
| 344 # Attach I/O devices that are on chip and also set the appropriate
345 # ranges for the bridge
346 def attachOnChipIO(self, bus, bridge):
|
334 self.gic.pio = bus.port
335 self.a9scu.pio = bus.port
| 347 self.gic.pio = bus.port
348 self.a9scu.pio = bus.port
|
| 349 # Bridge ranges based on excluding what is part of on-chip I/O
350 # (gic, a9scu)
351 bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1),
352 AddrRange(self.local_cpu_timer.pio_addr, Addr.max)]
|
336
337 # Attach I/O devices to specified bus object. Can't do this
338 # earlier, since the bus object itself is typically defined at the
339 # System level.
340 def attachIO(self, bus):
341 self.elba_uart.pio = bus.port
342 self.uart.pio = bus.port
343 self.realview_io.pio = bus.port
344 self.local_cpu_timer.pio = bus.port
345 self.v2m_timer0.pio = bus.port
346 self.v2m_timer1.pio = bus.port
347 self.elba_timer0.pio = bus.port
348 self.elba_timer1.pio = bus.port
349 self.clcd.pio = bus.port
350 self.kmi0.pio = bus.port
351 self.kmi1.pio = bus.port
352 self.elba_kmi0.pio = bus.port
353 self.elba_kmi1.pio = bus.port
354 self.cf_ctrl.pio = bus.port
355 self.ide.pio = bus.port
356 self.ethernet.pio = bus.port
357 self.pciconfig.pio = bus.default
358 bus.use_default_range = True
359
360 self.l2x0_fake.pio = bus.port
361 self.dmac_fake.pio = bus.port
362 self.uart1_fake.pio = bus.port
363 self.uart2_fake.pio = bus.port
364 self.uart3_fake.pio = bus.port
365 self.smc_fake.pio = bus.port
366 self.sp810_fake.pio = bus.port
367 self.watchdog_fake.pio = bus.port
368 self.aaci_fake.pio = bus.port
369 self.elba_aaci_fake.pio = bus.port
370 self.mmc_fake.pio = bus.port
371 self.rtc_fake.pio = bus.port
372 self.spsc_fake.pio = bus.port
373 self.lan_fake.pio = bus.port
374 self.usb_fake.pio = bus.port
375
| 353
354 # Attach I/O devices to specified bus object. Can't do this
355 # earlier, since the bus object itself is typically defined at the
356 # System level.
357 def attachIO(self, bus):
358 self.elba_uart.pio = bus.port
359 self.uart.pio = bus.port
360 self.realview_io.pio = bus.port
361 self.local_cpu_timer.pio = bus.port
362 self.v2m_timer0.pio = bus.port
363 self.v2m_timer1.pio = bus.port
364 self.elba_timer0.pio = bus.port
365 self.elba_timer1.pio = bus.port
366 self.clcd.pio = bus.port
367 self.kmi0.pio = bus.port
368 self.kmi1.pio = bus.port
369 self.elba_kmi0.pio = bus.port
370 self.elba_kmi1.pio = bus.port
371 self.cf_ctrl.pio = bus.port
372 self.ide.pio = bus.port
373 self.ethernet.pio = bus.port
374 self.pciconfig.pio = bus.default
375 bus.use_default_range = True
376
377 self.l2x0_fake.pio = bus.port
378 self.dmac_fake.pio = bus.port
379 self.uart1_fake.pio = bus.port
380 self.uart2_fake.pio = bus.port
381 self.uart3_fake.pio = bus.port
382 self.smc_fake.pio = bus.port
383 self.sp810_fake.pio = bus.port
384 self.watchdog_fake.pio = bus.port
385 self.aaci_fake.pio = bus.port
386 self.elba_aaci_fake.pio = bus.port
387 self.mmc_fake.pio = bus.port
388 self.rtc_fake.pio = bus.port
389 self.spsc_fake.pio = bus.port
390 self.lan_fake.pio = bus.port
391 self.usb_fake.pio = bus.port
392
|