1# Copyright (c) 2009-2018 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42# Glenn Bergmans
43
44from m5.defines import buildEnv
45from m5.params import *
46from m5.proxy import *
47from m5.util.fdthelper import *
48from ClockDomain import ClockDomain
49from VoltageDomain import VoltageDomain
50from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
51from PciHost import *
52from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
53from Ide import *
54from Platform import Platform
55from Terminal import Terminal
56from Uart import Uart
57from SimpleMemory import SimpleMemory
58from Gic import *
59from EnergyCtrl import EnergyCtrl
60from ClockedObject import ClockedObject
61from ClockDomain import SrcClockDomain
62from SubSystem import SubSystem
63from Graphics import ImageFormat
64from ClockedObject import ClockedObject
65from PS2 import *
66from VirtIOMMIO import MmioVirtIO
67
68# Platforms with KVM support should generally use in-kernel GIC
69# emulation. Use a GIC model that automatically switches between
70# gem5's GIC model and KVM's GIC model if KVM is available.
71try:
72 from KvmGic import MuxingKvmGic
73 kvm_gicv2_class = MuxingKvmGic
74except ImportError:
75 # KVM support wasn't compiled into gem5. Fallback to a
76 # software-only GIC.
77 kvm_gicv2_class = Pl390
78 pass
79
80class AmbaPioDevice(BasicPioDevice):
81 type = 'AmbaPioDevice'
82 abstract = True
83 cxx_header = "dev/arm/amba_device.hh"
84 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
85
86class AmbaIntDevice(AmbaPioDevice):
87 type = 'AmbaIntDevice'
88 abstract = True
89 cxx_header = "dev/arm/amba_device.hh"
90 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
91 int_num = Param.UInt32("Interrupt number that connects to GIC")
92 int_delay = Param.Latency("100ns",
93 "Time between action and interrupt generation by device")
94
95class AmbaDmaDevice(DmaDevice):
96 type = 'AmbaDmaDevice'
97 abstract = True
98 cxx_header = "dev/arm/amba_device.hh"
99 pio_addr = Param.Addr("Address for AMBA slave interface")
100 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
101 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
102 int_num = Param.UInt32("Interrupt number that connects to GIC")
103 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
104
105class A9SCU(BasicPioDevice):
106 type = 'A9SCU'
107 cxx_header = "dev/arm/a9scu.hh"
108
109class ArmPciIntRouting(Enum): vals = [
110 'ARM_PCI_INT_STATIC',
111 'ARM_PCI_INT_DEV',
112 'ARM_PCI_INT_PIN',
113 ]
114
115class GenericArmPciHost(GenericPciHost):
116 type = 'GenericArmPciHost'
117 cxx_header = "dev/arm/pci_host.hh"
118
119 int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy")
120 int_base = Param.Unsigned("PCI interrupt base")
121 int_count = Param.Unsigned("Maximum number of interrupts used by this host")
122
123 def generateDeviceTree(self, state):
124 local_state = FdtState(addr_cells=3, size_cells=2, cpu_cells=1)
125 intterrupt_cells = 1
126
127 node = FdtNode("pci")
128
129 if int(self.conf_device_bits) == 8:
130 node.appendCompatible("pci-host-cam-generic")
131 elif int(self.conf_device_bits) == 12:
132 node.appendCompatible("pci-host-ecam-generic")
133 else:
134 m5.fatal("No compatibility string for the set conf_device_width")
135
136 node.append(FdtPropertyStrings("device_type", ["pci"]))
137
138 # Cell sizes of child nodes/peripherals
139 node.append(local_state.addrCellsProperty())
140 node.append(local_state.sizeCellsProperty())
141 node.append(FdtPropertyWords("#interrupt-cells", intterrupt_cells))
142 # PCI address for CPU
143 node.append(FdtPropertyWords("reg",
144 state.addrCells(self.conf_base) +
145 state.sizeCells(self.conf_size) ))
146
147 # Ranges mapping
148 # For now some of this is hard coded, because the PCI module does not
149 # have a proper full understanding of the memory map, but adapting the
150 # PCI module is beyond the scope of what I'm trying to do here.
151 # Values are taken from the VExpress_GEM5_V1 platform.
152 ranges = []
153 # Pio address range
154 ranges += self.pciFdtAddr(space=1, addr=0)
155 ranges += state.addrCells(self.pci_pio_base)
156 ranges += local_state.sizeCells(0x10000) # Fixed size
157
158 # AXI memory address range
159 ranges += self.pciFdtAddr(space=2, addr=0)
160 ranges += state.addrCells(0x40000000) # Fixed offset
161 ranges += local_state.sizeCells(0x40000000) # Fixed size
162 node.append(FdtPropertyWords("ranges", ranges))
163
164 if str(self.int_policy) == 'ARM_PCI_INT_DEV':
165 int_phandle = state.phandle(self._parent.unproxy(self).gic)
166 # Interrupt mapping
167 interrupts = []
168 for i in range(int(self.int_count)):
169 interrupts += self.pciFdtAddr(device=i, addr=0) + \
170 [0x0, int_phandle, 0, int(self.int_base) - 32 + i, 1]
171
172 node.append(FdtPropertyWords("interrupt-map", interrupts))
173
174 int_count = int(self.int_count)
175 if int_count & (int_count - 1):
176 fatal("PCI interrupt count should be power of 2")
177
178 intmask = self.pciFdtAddr(device=int_count - 1, addr=0) + [0x0]
179 node.append(FdtPropertyWords("interrupt-map-mask", intmask))
180 else:
181 m5.fatal("Unsupported PCI interrupt policy " +
182 "for Device Tree generation")
183
184 node.append(FdtProperty("dma-coherent"))
185
186 yield node
187
188class RealViewCtrl(BasicPioDevice):
189 type = 'RealViewCtrl'
190 cxx_header = "dev/arm/rv_ctrl.hh"
191 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
192 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
193 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
194
195 def generateDeviceTree(self, state):
196 node = FdtNode("sysreg@%x" % long(self.pio_addr))
197 node.appendCompatible("arm,vexpress-sysreg")
198 node.append(FdtPropertyWords("reg",
199 state.addrCells(self.pio_addr) +
200 state.sizeCells(0x1000) ))
201 node.append(FdtProperty("gpio-controller"))
202 node.append(FdtPropertyWords("#gpio-cells", [2]))
203 node.appendPhandle(self)
204
205 yield node
206
207class RealViewOsc(ClockDomain):
208 type = 'RealViewOsc'
209 cxx_header = "dev/arm/rv_ctrl.hh"
210
211 parent = Param.RealViewCtrl(Parent.any, "RealView controller")
212
213 # TODO: We currently don't have the notion of a clock source,
214 # which means we have to associate oscillators with a voltage
215 # source.
216 voltage_domain = Param.VoltageDomain(Parent.voltage_domain,
217 "Voltage domain")
218
219 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
220 # the individual core/logic tile reference manuals for details
221 # about the site/position/dcc/device allocation.
222 site = Param.UInt8("Board Site")
223 position = Param.UInt8("Position in device stack")
224 dcc = Param.UInt8("Daughterboard Configuration Controller")
225 device = Param.UInt8("Device ID")
226
227 freq = Param.Clock("Default frequency")
228
229 def generateDeviceTree(self, state):
230 phandle = state.phandle(self)
231 node = FdtNode("osc@" + format(long(phandle), 'x'))
232 node.appendCompatible("arm,vexpress-osc")
233 node.append(FdtPropertyWords("arm,vexpress-sysreg,func",
234 [0x1, int(self.device)]))
235 node.append(FdtPropertyWords("#clock-cells", [0]))
236 freq = int(1.0/self.freq.value) # Values are stored as a clock period
237 node.append(FdtPropertyWords("freq-range", [freq, freq]))
238 node.append(FdtPropertyStrings("clock-output-names",
239 ["oscclk" + str(phandle)]))
240 node.appendPhandle(self)
241 yield node
242
243class RealViewTemperatureSensor(SimObject):
244 type = 'RealViewTemperatureSensor'
245 cxx_header = "dev/arm/rv_ctrl.hh"
246
247 parent = Param.RealViewCtrl(Parent.any, "RealView controller")
248
249 system = Param.System(Parent.any, "system")
250
251 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
252 # the individual core/logic tile reference manuals for details
253 # about the site/position/dcc/device allocation.
254 site = Param.UInt8("Board Site")
255 position = Param.UInt8("Position in device stack")
256 dcc = Param.UInt8("Daughterboard Configuration Controller")
257 device = Param.UInt8("Device ID")
258
259class VExpressMCC(SubSystem):
260 """ARM V2M-P1 Motherboard Configuration Controller
261
262This subsystem describes a subset of the devices that sit behind the
263motherboard configuration controller on the the ARM Motherboard
264Express (V2M-P1) motherboard. See ARM DUI 0447J for details.
265 """
266
267 class Osc(RealViewOsc):
268 site, position, dcc = (0, 0, 0)
269
270 class Temperature(RealViewTemperatureSensor):
271 site, position, dcc = (0, 0, 0)
272
273 osc_mcc = Osc(device=0, freq="50MHz")
274 osc_clcd = Osc(device=1, freq="23.75MHz")
275 osc_peripheral = Osc(device=2, freq="24MHz")
276 osc_system_bus = Osc(device=4, freq="24MHz")
277
278 # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM).
279 temp_crtl = Temperature(device=0)
280
281 def generateDeviceTree(self, state):
282 node = FdtNode("mcc")
283 node.appendCompatible("arm,vexpress,config-bus")
284 node.append(FdtPropertyWords("arm,vexpress,site", [0]))
285
286 for obj in self._children.values():
287 if issubclass(type(obj), SimObject):
288 node.append(obj.generateDeviceTree(state))
289
290 io_phandle = state.phandle(self.osc_mcc.parent.unproxy(self))
291 node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle))
292
293 yield node
294
295class CoreTile2A15DCC(SubSystem):
296 """ARM CoreTile Express A15x2 Daughterboard Configuration Controller
297
298This subsystem describes a subset of the devices that sit behind the
299daughterboard configuration controller on a CoreTile Express A15x2. See
300ARM DUI 0604E for details.
301 """
302
303 class Osc(RealViewOsc):
304 site, position, dcc = (1, 0, 0)
305
306 # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM)
307 osc_cpu = Osc(device=0, freq="60MHz")
308 osc_hsbm = Osc(device=4, freq="40MHz")
309 osc_pxl = Osc(device=5, freq="23.75MHz")
310 osc_smb = Osc(device=6, freq="50MHz")
311 osc_sys = Osc(device=7, freq="60MHz")
312 osc_ddr = Osc(device=8, freq="40MHz")
313
314 def generateDeviceTree(self, state):
315 node = FdtNode("dcc")
316 node.appendCompatible("arm,vexpress,config-bus")
317
318 for obj in self._children.values():
319 if isinstance(obj, SimObject):
320 node.append(obj.generateDeviceTree(state))
321
322 io_phandle = state.phandle(self.osc_cpu.parent.unproxy(self))
323 node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle))
324
325 yield node
326
327class VGic(PioDevice):
328 type = 'VGic'
329 cxx_header = "dev/arm/vgic.hh"
330 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
331 platform = Param.Platform(Parent.any, "Platform this device is part of.")
332 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
333 hv_addr = Param.Addr(0, "Address for hv control")
334 pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
335 # The number of list registers is not currently configurable at runtime.
336 ppint = Param.UInt32("HV maintenance interrupt number")
337
338 def generateDeviceTree(self, state):
339 gic = self.gic.unproxy(self)
340
341 node = FdtNode("interrupt-controller")
342 node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic",
343 "arm,cortex-a9-gic"])
344 node.append(FdtPropertyWords("#interrupt-cells", [3]))
345 node.append(FdtPropertyWords("#address-cells", [0]))
346 node.append(FdtProperty("interrupt-controller"))
347
348 regs = (
349 state.addrCells(gic.dist_addr) +
350 state.sizeCells(0x1000) +
351 state.addrCells(gic.cpu_addr) +
352 state.sizeCells(0x1000) +
353 state.addrCells(self.hv_addr) +
354 state.sizeCells(0x2000) +
355 state.addrCells(self.vcpu_addr) +
356 state.sizeCells(0x2000) )
357
358 node.append(FdtPropertyWords("reg", regs))
359 node.append(FdtPropertyWords("interrupts",
360 [1, int(self.ppint)-16, 0xf04]))
361
362 node.appendPhandle(gic)
363
364 yield node
365
366class AmbaFake(AmbaPioDevice):
367 type = 'AmbaFake'
368 cxx_header = "dev/arm/amba_fake.hh"
369 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
370 amba_id = 0;
371
372class Pl011(Uart):
373 type = 'Pl011'
374 cxx_header = "dev/arm/pl011.hh"
375 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
376 int_num = Param.UInt32("Interrupt number that connects to GIC")
377 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
378 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
379
380 def generateDeviceTree(self, state):
381 node = self.generateBasicPioDeviceNode(state, 'uart', self.pio_addr,
382 0x1000, [int(self.int_num)])
383 node.appendCompatible(["arm,pl011", "arm,primecell"])
384
385 # Hardcoded reference to the realview platform clocks, because the
386 # clk_domain can only store one clock (i.e. it is not a VectorParam)
387 realview = self._parent.unproxy(self)
388 node.append(FdtPropertyWords("clocks",
389 [state.phandle(realview.mcc.osc_peripheral),
390 state.phandle(realview.dcc.osc_smb)]))
391 node.append(FdtPropertyStrings("clock-names", ["uartclk", "apb_pclk"]))
392 yield node
393
394class Sp804(AmbaPioDevice):
395 type = 'Sp804'
396 cxx_header = "dev/arm/timer_sp804.hh"
397 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
398 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
399 clock0 = Param.Clock('1MHz', "Clock speed of the input")
400 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
401 clock1 = Param.Clock('1MHz', "Clock speed of the input")
402 amba_id = 0x00141804
403
404class A9GlobalTimer(BasicPioDevice):
405 type = 'A9GlobalTimer'
406 cxx_header = "dev/arm/timer_a9global.hh"
407 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
408 int_num = Param.UInt32("Interrrupt number that connects to GIC")
409
410class CpuLocalTimer(BasicPioDevice):
411 type = 'CpuLocalTimer'
412 cxx_header = "dev/arm/timer_cpulocal.hh"
413 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
414 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
415 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
416
417class GenericTimer(ClockedObject):
418 type = 'GenericTimer'
419 cxx_header = "dev/arm/generic_timer.hh"
420 system = Param.ArmSystem(Parent.any, "system")
421 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
422 int_phys_s = Param.UInt32("Physical (S) timer interrupt number")
423 int_phys_ns = Param.UInt32("Physical (NS) timer interrupt number")
424 int_virt = Param.UInt32("Virtual timer interrupt number")
425 int_hyp = Param.UInt32("Hypervisor timer interrupt number")
426
427 def generateDeviceTree(self, state):
428 node = FdtNode("timer")
429
430 node.appendCompatible(["arm,cortex-a15-timer",
431 "arm,armv7-timer",
432 "arm,armv8-timer"])
433 node.append(FdtPropertyWords("interrupts", [
434 1, int(self.int_phys_s) - 16, 0xf08,
435 1, int(self.int_phys_ns) - 16, 0xf08,
436 1, int(self.int_virt) - 16, 0xf08,
437 1, int(self.int_hyp) - 16, 0xf08,
438 ]))
439 clock = state.phandle(self.clk_domain.unproxy(self))
440 node.append(FdtPropertyWords("clocks", clock))
441
442 yield node
443
444class GenericTimerMem(PioDevice):
445 type = 'GenericTimerMem'
446 cxx_header = "dev/arm/generic_timer.hh"
447 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
448
449 base = Param.Addr(0, "Base address")
450
451 int_phys = Param.UInt32("Interrupt number")
452 int_virt = Param.UInt32("Interrupt number")
453
454class PL031(AmbaIntDevice):
455 type = 'PL031'
456 cxx_header = "dev/arm/rtc_pl031.hh"
457 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
458 amba_id = 0x00341031
459
460 def generateDeviceTree(self, state):
461 node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr,
462 0x1000, [int(self.int_num)])
463
464 node.appendCompatible(["arm,pl031", "arm,primecell"])
465 clock = state.phandle(self.clk_domain.unproxy(self))
466 node.append(FdtPropertyWords("clocks", clock))
467
468 yield node
469
470class Pl050(AmbaIntDevice):
471 type = 'Pl050'
472 cxx_header = "dev/arm/kmi.hh"
473 amba_id = 0x00141050
474
475 ps2 = Param.PS2Device("PS/2 device")
476
477 def generateDeviceTree(self, state):
478 node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr,
479 0x1000, [int(self.int_num)])
480
481 node.appendCompatible(["arm,pl050", "arm,primecell"])
482 clock = state.phandle(self.clk_domain.unproxy(self))
483 node.append(FdtPropertyWords("clocks", clock))
484
485 yield node
486
487class Pl111(AmbaDmaDevice):
488 type = 'Pl111'
489 cxx_header = "dev/arm/pl111.hh"
490 pixel_clock = Param.Clock('24MHz', "Pixel clock")
491 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
492 amba_id = 0x00141111
493 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
494
495class HDLcd(AmbaDmaDevice):
496 type = 'HDLcd'
497 cxx_header = "dev/arm/hdlcd.hh"
498 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer "
499 "display")
500 amba_id = 0x00141000
501 workaround_swap_rb = Param.Bool(False, "Workaround incorrect color "
502 "selector order in some kernels")
503 workaround_dma_line_count = Param.Bool(True, "Workaround incorrect "
504 "DMA line count (off by 1)")
505 enable_capture = Param.Bool(True, "capture frame to "
506 "system.framebuffer.{extension}")
507 frame_format = Param.ImageFormat("Auto",
508 "image format of the captured frame")
509
510 pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range")
511
512 pxl_clk = Param.ClockDomain("Pixel clock source")
513 pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch")
514 virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate "
515 "in KVM mode")
516
517 def generateDeviceTree(self, state):
518 # Interrupt number is hardcoded; it is not a property of this class
519 node = self.generateBasicPioDeviceNode(state, 'hdlcd',
520 self.pio_addr, 0x1000, [63])
521
522 node.appendCompatible(["arm,hdlcd"])
523 node.append(FdtPropertyWords("clocks", state.phandle(self.pxl_clk)))
524 node.append(FdtPropertyStrings("clock-names", ["pxlclk"]))
525
526 # This driver is disabled by default since the required DT nodes
527 # haven't been standardized yet. To use it, override this status to
528 # "ok" and add the display configuration nodes required by the driver.
529 # See the driver for more information.
530 node.append(FdtPropertyStrings("status", ["disabled"]))
531
532 yield node
533
534class RealView(Platform):
535 type = 'RealView'
536 cxx_header = "dev/arm/realview.hh"
537 system = Param.System(Parent.any, "system")
538 _mem_regions = [(Addr(0), Addr('256MB'))]
539
540 def _on_chip_devices(self):
541 return []
542
543 def _off_chip_devices(self):
544 return []
545
546 _off_chip_ranges = []
547
548 def _attach_device(self, device, bus, dma_ports=None):
549 if hasattr(device, "pio"):
550 device.pio = bus.master
551 if hasattr(device, "dma"):
552 if dma_ports is None:
553 device.dma = bus.slave
554 else:
555 dma_ports.append(device.dma)
556
557 def _attach_io(self, devices, *args, **kwargs):
558 for d in devices:
559 self._attach_device(d, *args, **kwargs)
560
561 def _attach_clk(self, devices, clkdomain):
562 for d in devices:
563 if hasattr(d, "clk_domain"):
564 d.clk_domain = clkdomain
565
566 def attachPciDevices(self):
567 pass
568
569 def enableMSIX(self):
570 pass
571
572 def onChipIOClkDomain(self, clkdomain):
573 self._attach_clk(self._on_chip_devices(), clkdomain)
574
575 def offChipIOClkDomain(self, clkdomain):
576 self._attach_clk(self._off_chip_devices(), clkdomain)
577
578 def attachOnChipIO(self, bus, bridge=None, *args, **kwargs):
579 self._attach_io(self._on_chip_devices(), bus, *args, **kwargs)
580 if bridge:
581 bridge.ranges = self._off_chip_ranges
582
583 def attachIO(self, *args, **kwargs):
584 self._attach_io(self._off_chip_devices(), *args, **kwargs)
585
586 def setupBootLoader(self, mem_bus, cur_sys, loc):
587 cur_sys.bootmem = SimpleMemory(
588 range = AddrRange('2GB', size = '64MB'),
589 conf_table_reported = False)
590 if mem_bus is not None:
591 cur_sys.bootmem.port = mem_bus.master
592 cur_sys.boot_loader = loc('boot.arm')
593 cur_sys.atags_addr = 0x100
594 cur_sys.load_offset = 0
595
596 def generateDeviceTree(self, state):
597 node = FdtNode("/") # Things in this module need to end up in the root
598 node.append(FdtPropertyWords("interrupt-parent",
599 state.phandle(self.gic)))
600
601 for subnode in self.recurseDeviceTree(state):
602 node.append(subnode)
603
604 yield node
605
606 def annotateCpuDeviceNode(self, cpu, state):
607 cpu.append(FdtPropertyStrings("enable-method", "spin-table"))
608 cpu.append(FdtPropertyWords("cpu-release-addr", \
609 state.addrCells(0x8000fff8)))
610
611# Reference for memory map and interrupt number
612# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
613# Chapter 4: Programmer's Reference
614class RealViewPBX(RealView):
615 uart = Pl011(pio_addr=0x10009000, int_num=44)
616 realview_io = RealViewCtrl(pio_addr=0x10000000)
617 mcc = VExpressMCC()
618 dcc = CoreTile2A15DCC()
619 gic = Pl390()
620 pci_host = GenericPciHost(
621 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
622 pci_pio_base=0)
623 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
624 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
625 global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200)
626 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
627 pio_addr=0x1f000600)
628 clcd = Pl111(pio_addr=0x10020000, int_num=55)
629 kmi0 = Pl050(pio_addr=0x10006000, int_num=52, ps2=PS2Keyboard())
630 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, ps2=PS2TouchKit())
631 a9scu = A9SCU(pio_addr=0x1f000000)
632 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
633 io_shift = 1, ctrl_offset = 2, Command = 0x1,
634 BAR0 = 0x18000000, BAR0Size = '16B',
635 BAR1 = 0x18000100, BAR1Size = '1B',
636 BAR0LegacyIO = True, BAR1LegacyIO = True)
637
638
639 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
640 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
641 fake_mem=True)
642 dmac_fake = AmbaFake(pio_addr=0x10030000)
643 uart1_fake = AmbaFake(pio_addr=0x1000a000)
644 uart2_fake = AmbaFake(pio_addr=0x1000b000)
645 uart3_fake = AmbaFake(pio_addr=0x1000c000)
646 smc_fake = AmbaFake(pio_addr=0x100e1000)
647 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
648 watchdog_fake = AmbaFake(pio_addr=0x10010000)
649 gpio0_fake = AmbaFake(pio_addr=0x10013000)
650 gpio1_fake = AmbaFake(pio_addr=0x10014000)
651 gpio2_fake = AmbaFake(pio_addr=0x10015000)
652 ssp_fake = AmbaFake(pio_addr=0x1000d000)
653 sci_fake = AmbaFake(pio_addr=0x1000e000)
654 aaci_fake = AmbaFake(pio_addr=0x10004000)
655 mmc_fake = AmbaFake(pio_addr=0x10005000)
656 rtc = PL031(pio_addr=0x10017000, int_num=42)
657 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
658
659
660 # Attach I/O devices that are on chip and also set the appropriate
661 # ranges for the bridge
662 def attachOnChipIO(self, bus, bridge):
663 self.gic.pio = bus.master
664 self.l2x0_fake.pio = bus.master
665 self.a9scu.pio = bus.master
666 self.global_timer.pio = bus.master
667 self.local_cpu_timer.pio = bus.master
668 # Bridge ranges based on excluding what is part of on-chip I/O
669 # (gic, l2x0, a9scu, local_cpu_timer)
670 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
671 self.a9scu.pio_addr - 1),
672 AddrRange(self.flash_fake.pio_addr,
673 self.flash_fake.pio_addr + \
674 self.flash_fake.pio_size - 1)]
675
676 # Set the clock domain for IO objects that are considered
677 # to be "close" to the cores.
678 def onChipIOClkDomain(self, clkdomain):
679 self.gic.clk_domain = clkdomain
680 self.l2x0_fake.clk_domain = clkdomain
681 self.a9scu.clkdomain = clkdomain
682 self.local_cpu_timer.clk_domain = clkdomain
683
684 # Attach I/O devices to specified bus object. Can't do this
685 # earlier, since the bus object itself is typically defined at the
686 # System level.
687 def attachIO(self, bus):
688 self.uart.pio = bus.master
689 self.realview_io.pio = bus.master
690 self.pci_host.pio = bus.master
691 self.timer0.pio = bus.master
692 self.timer1.pio = bus.master
693 self.clcd.pio = bus.master
694 self.clcd.dma = bus.slave
695 self.kmi0.pio = bus.master
696 self.kmi1.pio = bus.master
697 self.cf_ctrl.pio = bus.master
698 self.cf_ctrl.dma = bus.slave
699 self.dmac_fake.pio = bus.master
700 self.uart1_fake.pio = bus.master
701 self.uart2_fake.pio = bus.master
702 self.uart3_fake.pio = bus.master
703 self.smc_fake.pio = bus.master
704 self.sp810_fake.pio = bus.master
705 self.watchdog_fake.pio = bus.master
706 self.gpio0_fake.pio = bus.master
707 self.gpio1_fake.pio = bus.master
708 self.gpio2_fake.pio = bus.master
709 self.ssp_fake.pio = bus.master
710 self.sci_fake.pio = bus.master
711 self.aaci_fake.pio = bus.master
712 self.mmc_fake.pio = bus.master
713 self.rtc.pio = bus.master
714 self.flash_fake.pio = bus.master
715 self.energy_ctrl.pio = bus.master
716
717 # Set the clock domain for IO objects that are considered
718 # to be "far" away from the cores.
719 def offChipIOClkDomain(self, clkdomain):
720 self.uart.clk_domain = clkdomain
721 self.realview_io.clk_domain = clkdomain
722 self.timer0.clk_domain = clkdomain
723 self.timer1.clk_domain = clkdomain
724 self.clcd.clk_domain = clkdomain
725 self.kmi0.clk_domain = clkdomain
726 self.kmi1.clk_domain = clkdomain
727 self.cf_ctrl.clk_domain = clkdomain
728 self.dmac_fake.clk_domain = clkdomain
729 self.uart1_fake.clk_domain = clkdomain
730 self.uart2_fake.clk_domain = clkdomain
731 self.uart3_fake.clk_domain = clkdomain
732 self.smc_fake.clk_domain = clkdomain
733 self.sp810_fake.clk_domain = clkdomain
734 self.watchdog_fake.clk_domain = clkdomain
735 self.gpio0_fake.clk_domain = clkdomain
736 self.gpio1_fake.clk_domain = clkdomain
737 self.gpio2_fake.clk_domain = clkdomain
738 self.ssp_fake.clk_domain = clkdomain
739 self.sci_fake.clk_domain = clkdomain
740 self.aaci_fake.clk_domain = clkdomain
741 self.mmc_fake.clk_domain = clkdomain
742 self.rtc.clk_domain = clkdomain
743 self.flash_fake.clk_domain = clkdomain
744 self.energy_ctrl.clk_domain = clkdomain
745
746# Reference for memory map and interrupt number
747# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
748# Chapter 4: Programmer's Reference
749class RealViewEB(RealView):
750 uart = Pl011(pio_addr=0x10009000, int_num=44)
751 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
752 mcc = VExpressMCC()
753 dcc = CoreTile2A15DCC()
754 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
755 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
756 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
757 clcd = Pl111(pio_addr=0x10020000, int_num=23)
758 kmi0 = Pl050(pio_addr=0x10006000, int_num=20, ps2=PS2Keyboard())
759 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, ps2=PS2TouchKit())
760
761 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
762 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
763 fake_mem=True)
764 dmac_fake = AmbaFake(pio_addr=0x10030000)
765 uart1_fake = AmbaFake(pio_addr=0x1000a000)
766 uart2_fake = AmbaFake(pio_addr=0x1000b000)
767 uart3_fake = AmbaFake(pio_addr=0x1000c000)
768 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
769 smc_fake = AmbaFake(pio_addr=0x100e1000)
770 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
771 watchdog_fake = AmbaFake(pio_addr=0x10010000)
772 gpio0_fake = AmbaFake(pio_addr=0x10013000)
773 gpio1_fake = AmbaFake(pio_addr=0x10014000)
774 gpio2_fake = AmbaFake(pio_addr=0x10015000)
775 ssp_fake = AmbaFake(pio_addr=0x1000d000)
776 sci_fake = AmbaFake(pio_addr=0x1000e000)
777 aaci_fake = AmbaFake(pio_addr=0x10004000)
778 mmc_fake = AmbaFake(pio_addr=0x10005000)
779 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
780 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
781
782 # Attach I/O devices that are on chip and also set the appropriate
783 # ranges for the bridge
784 def attachOnChipIO(self, bus, bridge):
785 self.gic.pio = bus.master
786 self.l2x0_fake.pio = bus.master
787 # Bridge ranges based on excluding what is part of on-chip I/O
788 # (gic, l2x0)
789 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
790 self.gic.cpu_addr - 1),
791 AddrRange(self.flash_fake.pio_addr, Addr.max)]
792
793 # Set the clock domain for IO objects that are considered
794 # to be "close" to the cores.
795 def onChipIOClkDomain(self, clkdomain):
796 self.gic.clk_domain = clkdomain
797 self.l2x0_fake.clk_domain = clkdomain
798
799 # Attach I/O devices to specified bus object. Can't do this
800 # earlier, since the bus object itself is typically defined at the
801 # System level.
802 def attachIO(self, bus):
803 self.uart.pio = bus.master
804 self.realview_io.pio = bus.master
805 self.pci_host.pio = bus.master
806 self.timer0.pio = bus.master
807 self.timer1.pio = bus.master
808 self.clcd.pio = bus.master
809 self.clcd.dma = bus.slave
810 self.kmi0.pio = bus.master
811 self.kmi1.pio = bus.master
812 self.dmac_fake.pio = bus.master
813 self.uart1_fake.pio = bus.master
814 self.uart2_fake.pio = bus.master
815 self.uart3_fake.pio = bus.master
816 self.smc_fake.pio = bus.master
817 self.sp810_fake.pio = bus.master
818 self.watchdog_fake.pio = bus.master
819 self.gpio0_fake.pio = bus.master
820 self.gpio1_fake.pio = bus.master
821 self.gpio2_fake.pio = bus.master
822 self.ssp_fake.pio = bus.master
823 self.sci_fake.pio = bus.master
824 self.aaci_fake.pio = bus.master
825 self.mmc_fake.pio = bus.master
826 self.rtc_fake.pio = bus.master
827 self.flash_fake.pio = bus.master
828 self.smcreg_fake.pio = bus.master
829 self.energy_ctrl.pio = bus.master
830
831 # Set the clock domain for IO objects that are considered
832 # to be "far" away from the cores.
833 def offChipIOClkDomain(self, clkdomain):
834 self.uart.clk_domain = clkdomain
835 self.realview_io.clk_domain = clkdomain
836 self.timer0.clk_domain = clkdomain
837 self.timer1.clk_domain = clkdomain
838 self.clcd.clk_domain = clkdomain
839 self.kmi0.clk_domain = clkdomain
840 self.kmi1.clk_domain = clkdomain
841 self.dmac_fake.clk_domain = clkdomain
842 self.uart1_fake.clk_domain = clkdomain
843 self.uart2_fake.clk_domain = clkdomain
844 self.uart3_fake.clk_domain = clkdomain
845 self.smc_fake.clk_domain = clkdomain
846 self.sp810_fake.clk_domain = clkdomain
847 self.watchdog_fake.clk_domain = clkdomain
848 self.gpio0_fake.clk_domain = clkdomain
849 self.gpio1_fake.clk_domain = clkdomain
850 self.gpio2_fake.clk_domain = clkdomain
851 self.ssp_fake.clk_domain = clkdomain
852 self.sci_fake.clk_domain = clkdomain
853 self.aaci_fake.clk_domain = clkdomain
854 self.mmc_fake.clk_domain = clkdomain
855 self.rtc.clk_domain = clkdomain
856 self.flash_fake.clk_domain = clkdomain
857 self.smcreg_fake.clk_domain = clkdomain
858 self.energy_ctrl.clk_domain = clkdomain
859
860class VExpress_EMM(RealView):
861 _mem_regions = [(Addr('2GB'), Addr('2GB'))]
862
863 # Ranges based on excluding what is part of on-chip I/O (gic,
864 # a9scu)
865 _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'),
866 AddrRange(0x30000000, size='256MB'),
867 AddrRange(0x40000000, size='512MB'),
868 AddrRange(0x18000000, size='64MB'),
869 AddrRange(0x1C000000, size='64MB')]
870
871 # Platform control device (off-chip)
872 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
873 idreg=0x02250000, pio_addr=0x1C010000)
874
875 mcc = VExpressMCC()
876 dcc = CoreTile2A15DCC()
877
878 ### On-chip devices ###
879 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
880 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
881
882 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
883 pio_addr=0x2C080000)
884
885 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
886 pio_addr=0x2b000000, int_num=117,
887 workaround_swap_rb=True)
888
889 def _on_chip_devices(self):
890 devices = [
891 self.gic, self.vgic,
892 self.local_cpu_timer
893 ]
894 if hasattr(self, "gicv2m"):
895 devices.append(self.gicv2m)
896 devices.append(self.hdlcd)
897 return devices
898
899 ### Off-chip devices ###
900 uart = Pl011(pio_addr=0x1c090000, int_num=37)
901 pci_host = GenericPciHost(
902 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
903 pci_pio_base=0)
904
905 generic_timer = GenericTimer(int_phys_s=29, int_phys_ns=30,
906 int_virt=27, int_hyp=26)
907 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
908 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
909 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
910 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard())
911 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit())
912 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
913 io_shift = 2, ctrl_offset = 2, Command = 0x1,
914 BAR0 = 0x1C1A0000, BAR0Size = '256B',
915 BAR1 = 0x1C1A0100, BAR1Size = '4096B',
916 BAR0LegacyIO = True, BAR1LegacyIO = True)
917
918 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
919 conf_table_reported = False)
920 rtc = PL031(pio_addr=0x1C170000, int_num=36)
921
922 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
923 uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
924 uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
925 uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
926 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
927 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
928 aaci_fake = AmbaFake(pio_addr=0x1C040000)
929 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
930 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
931 mmc_fake = AmbaFake(pio_addr=0x1c050000)
932 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000)
933
934 def _off_chip_devices(self):
935 devices = [
936 self.uart,
937 self.realview_io,
938 self.pci_host,
939 self.timer0,
940 self.timer1,
941 self.clcd,
942 self.kmi0,
943 self.kmi1,
944 self.cf_ctrl,
945 self.rtc,
946 self.vram,
947 self.l2x0_fake,
948 self.uart1_fake,
949 self.uart2_fake,
950 self.uart3_fake,
951 self.sp810_fake,
952 self.watchdog_fake,
953 self.aaci_fake,
954 self.lan_fake,
955 self.usb_fake,
956 self.mmc_fake,
957 self.energy_ctrl,
958 ]
959 # Try to attach the I/O if it exists
960 if hasattr(self, "ide"):
961 devices.append(self.ide)
962 if hasattr(self, "ethernet"):
963 devices.append(self.ethernet)
964 return devices
965
966 # Attach any PCI devices that are supported
967 def attachPciDevices(self):
968 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
969 InterruptLine=1, InterruptPin=1)
970 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
971 InterruptLine=2, InterruptPin=2)
972
973 def enableMSIX(self):
974 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
975 self.gicv2m = Gicv2m()
976 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
977
978 def setupBootLoader(self, mem_bus, cur_sys, loc):
979 cur_sys.bootmem = SimpleMemory(range = AddrRange('64MB'),
980 conf_table_reported = False)
981 if mem_bus is not None:
982 cur_sys.bootmem.port = mem_bus.master
983 if not cur_sys.boot_loader:
984 cur_sys.boot_loader = loc('boot_emm.arm')
985 cur_sys.atags_addr = 0x8000000
986 cur_sys.load_offset = 0x80000000
987
988class VExpress_EMM64(VExpress_EMM):
989 # Three memory regions are specified totalling 512GB
990 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
991 (Addr('512GB'), Addr('480GB'))]
992 pci_host = GenericPciHost(
993 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
994 pci_pio_base=0x2f000000)
995
996 def setupBootLoader(self, mem_bus, cur_sys, loc):
997 cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'),
998 conf_table_reported=False)
999 if mem_bus is not None:
1000 cur_sys.bootmem.port = mem_bus.master
1001 if not cur_sys.boot_loader:
1002 cur_sys.boot_loader = loc('boot_emm.arm64')
1003 cur_sys.atags_addr = 0x8000000
1004 cur_sys.load_offset = 0x80000000
1005
1006class VExpress_GEM5_V1_Base(RealView):
1007 """
1008The VExpress gem5 memory map is loosely based on a modified
1009Versatile Express RS1 memory map.
1010
1011The gem5 platform has been designed to implement a subset of the
1012original Versatile Express RS1 memory map. Off-chip peripherals should,
1013when possible, adhere to the Versatile Express memory map. Non-PCI
1014off-chip devices that are gem5-specific should live in the CS5 memory
1015space to avoid conflicts with existing devices that we might want to
1016model in the future. Such devices should normally have interrupts in
1017the gem5-specific SPI range.
1018
1019On-chip peripherals are loosely modeled after the ARM CoreTile Express
1020A15x2 A7x3 memory and interrupt map. In particular, the GIC and
1021Generic Timer have the same interrupt lines and base addresses. Other
1022on-chip devices are gem5 specific.
1023
1024Unlike the original Versatile Express RS2 extended platform, gem5 implements a
1025large contigious DRAM space, without aliases or holes, starting at the
10262GiB boundary. This means that PCI memory is limited to 1GiB.
1027
1028Memory map:
1029 0x00000000-0x03ffffff: Boot memory (CS0)
1030 0x04000000-0x07ffffff: Reserved
1031 0x08000000-0x0bffffff: Reserved (CS0 alias)
1032 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4)
1033 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
1034 0x10000000-0x1000ffff: gem5 energy controller
1035 0x10010000-0x1001ffff: gem5 pseudo-ops
1036
1037 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1)
1038 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2)
1039 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3):
1040 0x1c010000-0x1c01ffff: realview_io (VE system control regs.)
1041 0x1c060000-0x1c06ffff: KMI0 (keyboard)
1042 0x1c070000-0x1c07ffff: KMI1 (mouse)
1043 0x1c090000-0x1c09ffff: UART0
1044 0x1c0a0000-0x1c0affff: UART1 (reserved)
1045 0x1c0b0000-0x1c0bffff: UART2 (reserved)
1046 0x1c0c0000-0x1c0cffff: UART3 (reserved)
1047 0x1c130000-0x1c13ffff: VirtIO (gem5/FM extension)
1048 0x1c140000-0x1c14ffff: VirtIO (gem5/FM extension)
1049 0x1c170000-0x1c17ffff: RTC
1050
1051 0x20000000-0x3fffffff: On-chip peripherals:
1052 0x2b000000-0x2b00ffff: HDLCD
1053
1054 0x2c001000-0x2c001fff: GIC (distributor)
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31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42# Glenn Bergmans
43
44from m5.defines import buildEnv
45from m5.params import *
46from m5.proxy import *
47from m5.util.fdthelper import *
48from ClockDomain import ClockDomain
49from VoltageDomain import VoltageDomain
50from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
51from PciHost import *
52from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
53from Ide import *
54from Platform import Platform
55from Terminal import Terminal
56from Uart import Uart
57from SimpleMemory import SimpleMemory
58from Gic import *
59from EnergyCtrl import EnergyCtrl
60from ClockedObject import ClockedObject
61from ClockDomain import SrcClockDomain
62from SubSystem import SubSystem
63from Graphics import ImageFormat
64from ClockedObject import ClockedObject
65from PS2 import *
66from VirtIOMMIO import MmioVirtIO
67
68# Platforms with KVM support should generally use in-kernel GIC
69# emulation. Use a GIC model that automatically switches between
70# gem5's GIC model and KVM's GIC model if KVM is available.
71try:
72 from KvmGic import MuxingKvmGic
73 kvm_gicv2_class = MuxingKvmGic
74except ImportError:
75 # KVM support wasn't compiled into gem5. Fallback to a
76 # software-only GIC.
77 kvm_gicv2_class = Pl390
78 pass
79
80class AmbaPioDevice(BasicPioDevice):
81 type = 'AmbaPioDevice'
82 abstract = True
83 cxx_header = "dev/arm/amba_device.hh"
84 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
85
86class AmbaIntDevice(AmbaPioDevice):
87 type = 'AmbaIntDevice'
88 abstract = True
89 cxx_header = "dev/arm/amba_device.hh"
90 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
91 int_num = Param.UInt32("Interrupt number that connects to GIC")
92 int_delay = Param.Latency("100ns",
93 "Time between action and interrupt generation by device")
94
95class AmbaDmaDevice(DmaDevice):
96 type = 'AmbaDmaDevice'
97 abstract = True
98 cxx_header = "dev/arm/amba_device.hh"
99 pio_addr = Param.Addr("Address for AMBA slave interface")
100 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
101 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
102 int_num = Param.UInt32("Interrupt number that connects to GIC")
103 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
104
105class A9SCU(BasicPioDevice):
106 type = 'A9SCU'
107 cxx_header = "dev/arm/a9scu.hh"
108
109class ArmPciIntRouting(Enum): vals = [
110 'ARM_PCI_INT_STATIC',
111 'ARM_PCI_INT_DEV',
112 'ARM_PCI_INT_PIN',
113 ]
114
115class GenericArmPciHost(GenericPciHost):
116 type = 'GenericArmPciHost'
117 cxx_header = "dev/arm/pci_host.hh"
118
119 int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy")
120 int_base = Param.Unsigned("PCI interrupt base")
121 int_count = Param.Unsigned("Maximum number of interrupts used by this host")
122
123 def generateDeviceTree(self, state):
124 local_state = FdtState(addr_cells=3, size_cells=2, cpu_cells=1)
125 intterrupt_cells = 1
126
127 node = FdtNode("pci")
128
129 if int(self.conf_device_bits) == 8:
130 node.appendCompatible("pci-host-cam-generic")
131 elif int(self.conf_device_bits) == 12:
132 node.appendCompatible("pci-host-ecam-generic")
133 else:
134 m5.fatal("No compatibility string for the set conf_device_width")
135
136 node.append(FdtPropertyStrings("device_type", ["pci"]))
137
138 # Cell sizes of child nodes/peripherals
139 node.append(local_state.addrCellsProperty())
140 node.append(local_state.sizeCellsProperty())
141 node.append(FdtPropertyWords("#interrupt-cells", intterrupt_cells))
142 # PCI address for CPU
143 node.append(FdtPropertyWords("reg",
144 state.addrCells(self.conf_base) +
145 state.sizeCells(self.conf_size) ))
146
147 # Ranges mapping
148 # For now some of this is hard coded, because the PCI module does not
149 # have a proper full understanding of the memory map, but adapting the
150 # PCI module is beyond the scope of what I'm trying to do here.
151 # Values are taken from the VExpress_GEM5_V1 platform.
152 ranges = []
153 # Pio address range
154 ranges += self.pciFdtAddr(space=1, addr=0)
155 ranges += state.addrCells(self.pci_pio_base)
156 ranges += local_state.sizeCells(0x10000) # Fixed size
157
158 # AXI memory address range
159 ranges += self.pciFdtAddr(space=2, addr=0)
160 ranges += state.addrCells(0x40000000) # Fixed offset
161 ranges += local_state.sizeCells(0x40000000) # Fixed size
162 node.append(FdtPropertyWords("ranges", ranges))
163
164 if str(self.int_policy) == 'ARM_PCI_INT_DEV':
165 int_phandle = state.phandle(self._parent.unproxy(self).gic)
166 # Interrupt mapping
167 interrupts = []
168 for i in range(int(self.int_count)):
169 interrupts += self.pciFdtAddr(device=i, addr=0) + \
170 [0x0, int_phandle, 0, int(self.int_base) - 32 + i, 1]
171
172 node.append(FdtPropertyWords("interrupt-map", interrupts))
173
174 int_count = int(self.int_count)
175 if int_count & (int_count - 1):
176 fatal("PCI interrupt count should be power of 2")
177
178 intmask = self.pciFdtAddr(device=int_count - 1, addr=0) + [0x0]
179 node.append(FdtPropertyWords("interrupt-map-mask", intmask))
180 else:
181 m5.fatal("Unsupported PCI interrupt policy " +
182 "for Device Tree generation")
183
184 node.append(FdtProperty("dma-coherent"))
185
186 yield node
187
188class RealViewCtrl(BasicPioDevice):
189 type = 'RealViewCtrl'
190 cxx_header = "dev/arm/rv_ctrl.hh"
191 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
192 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
193 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
194
195 def generateDeviceTree(self, state):
196 node = FdtNode("sysreg@%x" % long(self.pio_addr))
197 node.appendCompatible("arm,vexpress-sysreg")
198 node.append(FdtPropertyWords("reg",
199 state.addrCells(self.pio_addr) +
200 state.sizeCells(0x1000) ))
201 node.append(FdtProperty("gpio-controller"))
202 node.append(FdtPropertyWords("#gpio-cells", [2]))
203 node.appendPhandle(self)
204
205 yield node
206
207class RealViewOsc(ClockDomain):
208 type = 'RealViewOsc'
209 cxx_header = "dev/arm/rv_ctrl.hh"
210
211 parent = Param.RealViewCtrl(Parent.any, "RealView controller")
212
213 # TODO: We currently don't have the notion of a clock source,
214 # which means we have to associate oscillators with a voltage
215 # source.
216 voltage_domain = Param.VoltageDomain(Parent.voltage_domain,
217 "Voltage domain")
218
219 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
220 # the individual core/logic tile reference manuals for details
221 # about the site/position/dcc/device allocation.
222 site = Param.UInt8("Board Site")
223 position = Param.UInt8("Position in device stack")
224 dcc = Param.UInt8("Daughterboard Configuration Controller")
225 device = Param.UInt8("Device ID")
226
227 freq = Param.Clock("Default frequency")
228
229 def generateDeviceTree(self, state):
230 phandle = state.phandle(self)
231 node = FdtNode("osc@" + format(long(phandle), 'x'))
232 node.appendCompatible("arm,vexpress-osc")
233 node.append(FdtPropertyWords("arm,vexpress-sysreg,func",
234 [0x1, int(self.device)]))
235 node.append(FdtPropertyWords("#clock-cells", [0]))
236 freq = int(1.0/self.freq.value) # Values are stored as a clock period
237 node.append(FdtPropertyWords("freq-range", [freq, freq]))
238 node.append(FdtPropertyStrings("clock-output-names",
239 ["oscclk" + str(phandle)]))
240 node.appendPhandle(self)
241 yield node
242
243class RealViewTemperatureSensor(SimObject):
244 type = 'RealViewTemperatureSensor'
245 cxx_header = "dev/arm/rv_ctrl.hh"
246
247 parent = Param.RealViewCtrl(Parent.any, "RealView controller")
248
249 system = Param.System(Parent.any, "system")
250
251 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
252 # the individual core/logic tile reference manuals for details
253 # about the site/position/dcc/device allocation.
254 site = Param.UInt8("Board Site")
255 position = Param.UInt8("Position in device stack")
256 dcc = Param.UInt8("Daughterboard Configuration Controller")
257 device = Param.UInt8("Device ID")
258
259class VExpressMCC(SubSystem):
260 """ARM V2M-P1 Motherboard Configuration Controller
261
262This subsystem describes a subset of the devices that sit behind the
263motherboard configuration controller on the the ARM Motherboard
264Express (V2M-P1) motherboard. See ARM DUI 0447J for details.
265 """
266
267 class Osc(RealViewOsc):
268 site, position, dcc = (0, 0, 0)
269
270 class Temperature(RealViewTemperatureSensor):
271 site, position, dcc = (0, 0, 0)
272
273 osc_mcc = Osc(device=0, freq="50MHz")
274 osc_clcd = Osc(device=1, freq="23.75MHz")
275 osc_peripheral = Osc(device=2, freq="24MHz")
276 osc_system_bus = Osc(device=4, freq="24MHz")
277
278 # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM).
279 temp_crtl = Temperature(device=0)
280
281 def generateDeviceTree(self, state):
282 node = FdtNode("mcc")
283 node.appendCompatible("arm,vexpress,config-bus")
284 node.append(FdtPropertyWords("arm,vexpress,site", [0]))
285
286 for obj in self._children.values():
287 if issubclass(type(obj), SimObject):
288 node.append(obj.generateDeviceTree(state))
289
290 io_phandle = state.phandle(self.osc_mcc.parent.unproxy(self))
291 node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle))
292
293 yield node
294
295class CoreTile2A15DCC(SubSystem):
296 """ARM CoreTile Express A15x2 Daughterboard Configuration Controller
297
298This subsystem describes a subset of the devices that sit behind the
299daughterboard configuration controller on a CoreTile Express A15x2. See
300ARM DUI 0604E for details.
301 """
302
303 class Osc(RealViewOsc):
304 site, position, dcc = (1, 0, 0)
305
306 # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM)
307 osc_cpu = Osc(device=0, freq="60MHz")
308 osc_hsbm = Osc(device=4, freq="40MHz")
309 osc_pxl = Osc(device=5, freq="23.75MHz")
310 osc_smb = Osc(device=6, freq="50MHz")
311 osc_sys = Osc(device=7, freq="60MHz")
312 osc_ddr = Osc(device=8, freq="40MHz")
313
314 def generateDeviceTree(self, state):
315 node = FdtNode("dcc")
316 node.appendCompatible("arm,vexpress,config-bus")
317
318 for obj in self._children.values():
319 if isinstance(obj, SimObject):
320 node.append(obj.generateDeviceTree(state))
321
322 io_phandle = state.phandle(self.osc_cpu.parent.unproxy(self))
323 node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle))
324
325 yield node
326
327class VGic(PioDevice):
328 type = 'VGic'
329 cxx_header = "dev/arm/vgic.hh"
330 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
331 platform = Param.Platform(Parent.any, "Platform this device is part of.")
332 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
333 hv_addr = Param.Addr(0, "Address for hv control")
334 pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
335 # The number of list registers is not currently configurable at runtime.
336 ppint = Param.UInt32("HV maintenance interrupt number")
337
338 def generateDeviceTree(self, state):
339 gic = self.gic.unproxy(self)
340
341 node = FdtNode("interrupt-controller")
342 node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic",
343 "arm,cortex-a9-gic"])
344 node.append(FdtPropertyWords("#interrupt-cells", [3]))
345 node.append(FdtPropertyWords("#address-cells", [0]))
346 node.append(FdtProperty("interrupt-controller"))
347
348 regs = (
349 state.addrCells(gic.dist_addr) +
350 state.sizeCells(0x1000) +
351 state.addrCells(gic.cpu_addr) +
352 state.sizeCells(0x1000) +
353 state.addrCells(self.hv_addr) +
354 state.sizeCells(0x2000) +
355 state.addrCells(self.vcpu_addr) +
356 state.sizeCells(0x2000) )
357
358 node.append(FdtPropertyWords("reg", regs))
359 node.append(FdtPropertyWords("interrupts",
360 [1, int(self.ppint)-16, 0xf04]))
361
362 node.appendPhandle(gic)
363
364 yield node
365
366class AmbaFake(AmbaPioDevice):
367 type = 'AmbaFake'
368 cxx_header = "dev/arm/amba_fake.hh"
369 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
370 amba_id = 0;
371
372class Pl011(Uart):
373 type = 'Pl011'
374 cxx_header = "dev/arm/pl011.hh"
375 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
376 int_num = Param.UInt32("Interrupt number that connects to GIC")
377 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
378 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
379
380 def generateDeviceTree(self, state):
381 node = self.generateBasicPioDeviceNode(state, 'uart', self.pio_addr,
382 0x1000, [int(self.int_num)])
383 node.appendCompatible(["arm,pl011", "arm,primecell"])
384
385 # Hardcoded reference to the realview platform clocks, because the
386 # clk_domain can only store one clock (i.e. it is not a VectorParam)
387 realview = self._parent.unproxy(self)
388 node.append(FdtPropertyWords("clocks",
389 [state.phandle(realview.mcc.osc_peripheral),
390 state.phandle(realview.dcc.osc_smb)]))
391 node.append(FdtPropertyStrings("clock-names", ["uartclk", "apb_pclk"]))
392 yield node
393
394class Sp804(AmbaPioDevice):
395 type = 'Sp804'
396 cxx_header = "dev/arm/timer_sp804.hh"
397 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
398 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
399 clock0 = Param.Clock('1MHz', "Clock speed of the input")
400 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
401 clock1 = Param.Clock('1MHz', "Clock speed of the input")
402 amba_id = 0x00141804
403
404class A9GlobalTimer(BasicPioDevice):
405 type = 'A9GlobalTimer'
406 cxx_header = "dev/arm/timer_a9global.hh"
407 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
408 int_num = Param.UInt32("Interrrupt number that connects to GIC")
409
410class CpuLocalTimer(BasicPioDevice):
411 type = 'CpuLocalTimer'
412 cxx_header = "dev/arm/timer_cpulocal.hh"
413 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
414 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
415 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
416
417class GenericTimer(ClockedObject):
418 type = 'GenericTimer'
419 cxx_header = "dev/arm/generic_timer.hh"
420 system = Param.ArmSystem(Parent.any, "system")
421 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
422 int_phys_s = Param.UInt32("Physical (S) timer interrupt number")
423 int_phys_ns = Param.UInt32("Physical (NS) timer interrupt number")
424 int_virt = Param.UInt32("Virtual timer interrupt number")
425 int_hyp = Param.UInt32("Hypervisor timer interrupt number")
426
427 def generateDeviceTree(self, state):
428 node = FdtNode("timer")
429
430 node.appendCompatible(["arm,cortex-a15-timer",
431 "arm,armv7-timer",
432 "arm,armv8-timer"])
433 node.append(FdtPropertyWords("interrupts", [
434 1, int(self.int_phys_s) - 16, 0xf08,
435 1, int(self.int_phys_ns) - 16, 0xf08,
436 1, int(self.int_virt) - 16, 0xf08,
437 1, int(self.int_hyp) - 16, 0xf08,
438 ]))
439 clock = state.phandle(self.clk_domain.unproxy(self))
440 node.append(FdtPropertyWords("clocks", clock))
441
442 yield node
443
444class GenericTimerMem(PioDevice):
445 type = 'GenericTimerMem'
446 cxx_header = "dev/arm/generic_timer.hh"
447 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
448
449 base = Param.Addr(0, "Base address")
450
451 int_phys = Param.UInt32("Interrupt number")
452 int_virt = Param.UInt32("Interrupt number")
453
454class PL031(AmbaIntDevice):
455 type = 'PL031'
456 cxx_header = "dev/arm/rtc_pl031.hh"
457 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
458 amba_id = 0x00341031
459
460 def generateDeviceTree(self, state):
461 node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr,
462 0x1000, [int(self.int_num)])
463
464 node.appendCompatible(["arm,pl031", "arm,primecell"])
465 clock = state.phandle(self.clk_domain.unproxy(self))
466 node.append(FdtPropertyWords("clocks", clock))
467
468 yield node
469
470class Pl050(AmbaIntDevice):
471 type = 'Pl050'
472 cxx_header = "dev/arm/kmi.hh"
473 amba_id = 0x00141050
474
475 ps2 = Param.PS2Device("PS/2 device")
476
477 def generateDeviceTree(self, state):
478 node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr,
479 0x1000, [int(self.int_num)])
480
481 node.appendCompatible(["arm,pl050", "arm,primecell"])
482 clock = state.phandle(self.clk_domain.unproxy(self))
483 node.append(FdtPropertyWords("clocks", clock))
484
485 yield node
486
487class Pl111(AmbaDmaDevice):
488 type = 'Pl111'
489 cxx_header = "dev/arm/pl111.hh"
490 pixel_clock = Param.Clock('24MHz', "Pixel clock")
491 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
492 amba_id = 0x00141111
493 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
494
495class HDLcd(AmbaDmaDevice):
496 type = 'HDLcd'
497 cxx_header = "dev/arm/hdlcd.hh"
498 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer "
499 "display")
500 amba_id = 0x00141000
501 workaround_swap_rb = Param.Bool(False, "Workaround incorrect color "
502 "selector order in some kernels")
503 workaround_dma_line_count = Param.Bool(True, "Workaround incorrect "
504 "DMA line count (off by 1)")
505 enable_capture = Param.Bool(True, "capture frame to "
506 "system.framebuffer.{extension}")
507 frame_format = Param.ImageFormat("Auto",
508 "image format of the captured frame")
509
510 pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range")
511
512 pxl_clk = Param.ClockDomain("Pixel clock source")
513 pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch")
514 virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate "
515 "in KVM mode")
516
517 def generateDeviceTree(self, state):
518 # Interrupt number is hardcoded; it is not a property of this class
519 node = self.generateBasicPioDeviceNode(state, 'hdlcd',
520 self.pio_addr, 0x1000, [63])
521
522 node.appendCompatible(["arm,hdlcd"])
523 node.append(FdtPropertyWords("clocks", state.phandle(self.pxl_clk)))
524 node.append(FdtPropertyStrings("clock-names", ["pxlclk"]))
525
526 # This driver is disabled by default since the required DT nodes
527 # haven't been standardized yet. To use it, override this status to
528 # "ok" and add the display configuration nodes required by the driver.
529 # See the driver for more information.
530 node.append(FdtPropertyStrings("status", ["disabled"]))
531
532 yield node
533
534class RealView(Platform):
535 type = 'RealView'
536 cxx_header = "dev/arm/realview.hh"
537 system = Param.System(Parent.any, "system")
538 _mem_regions = [(Addr(0), Addr('256MB'))]
539
540 def _on_chip_devices(self):
541 return []
542
543 def _off_chip_devices(self):
544 return []
545
546 _off_chip_ranges = []
547
548 def _attach_device(self, device, bus, dma_ports=None):
549 if hasattr(device, "pio"):
550 device.pio = bus.master
551 if hasattr(device, "dma"):
552 if dma_ports is None:
553 device.dma = bus.slave
554 else:
555 dma_ports.append(device.dma)
556
557 def _attach_io(self, devices, *args, **kwargs):
558 for d in devices:
559 self._attach_device(d, *args, **kwargs)
560
561 def _attach_clk(self, devices, clkdomain):
562 for d in devices:
563 if hasattr(d, "clk_domain"):
564 d.clk_domain = clkdomain
565
566 def attachPciDevices(self):
567 pass
568
569 def enableMSIX(self):
570 pass
571
572 def onChipIOClkDomain(self, clkdomain):
573 self._attach_clk(self._on_chip_devices(), clkdomain)
574
575 def offChipIOClkDomain(self, clkdomain):
576 self._attach_clk(self._off_chip_devices(), clkdomain)
577
578 def attachOnChipIO(self, bus, bridge=None, *args, **kwargs):
579 self._attach_io(self._on_chip_devices(), bus, *args, **kwargs)
580 if bridge:
581 bridge.ranges = self._off_chip_ranges
582
583 def attachIO(self, *args, **kwargs):
584 self._attach_io(self._off_chip_devices(), *args, **kwargs)
585
586 def setupBootLoader(self, mem_bus, cur_sys, loc):
587 cur_sys.bootmem = SimpleMemory(
588 range = AddrRange('2GB', size = '64MB'),
589 conf_table_reported = False)
590 if mem_bus is not None:
591 cur_sys.bootmem.port = mem_bus.master
592 cur_sys.boot_loader = loc('boot.arm')
593 cur_sys.atags_addr = 0x100
594 cur_sys.load_offset = 0
595
596 def generateDeviceTree(self, state):
597 node = FdtNode("/") # Things in this module need to end up in the root
598 node.append(FdtPropertyWords("interrupt-parent",
599 state.phandle(self.gic)))
600
601 for subnode in self.recurseDeviceTree(state):
602 node.append(subnode)
603
604 yield node
605
606 def annotateCpuDeviceNode(self, cpu, state):
607 cpu.append(FdtPropertyStrings("enable-method", "spin-table"))
608 cpu.append(FdtPropertyWords("cpu-release-addr", \
609 state.addrCells(0x8000fff8)))
610
611# Reference for memory map and interrupt number
612# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
613# Chapter 4: Programmer's Reference
614class RealViewPBX(RealView):
615 uart = Pl011(pio_addr=0x10009000, int_num=44)
616 realview_io = RealViewCtrl(pio_addr=0x10000000)
617 mcc = VExpressMCC()
618 dcc = CoreTile2A15DCC()
619 gic = Pl390()
620 pci_host = GenericPciHost(
621 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
622 pci_pio_base=0)
623 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
624 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
625 global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200)
626 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
627 pio_addr=0x1f000600)
628 clcd = Pl111(pio_addr=0x10020000, int_num=55)
629 kmi0 = Pl050(pio_addr=0x10006000, int_num=52, ps2=PS2Keyboard())
630 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, ps2=PS2TouchKit())
631 a9scu = A9SCU(pio_addr=0x1f000000)
632 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
633 io_shift = 1, ctrl_offset = 2, Command = 0x1,
634 BAR0 = 0x18000000, BAR0Size = '16B',
635 BAR1 = 0x18000100, BAR1Size = '1B',
636 BAR0LegacyIO = True, BAR1LegacyIO = True)
637
638
639 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
640 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
641 fake_mem=True)
642 dmac_fake = AmbaFake(pio_addr=0x10030000)
643 uart1_fake = AmbaFake(pio_addr=0x1000a000)
644 uart2_fake = AmbaFake(pio_addr=0x1000b000)
645 uart3_fake = AmbaFake(pio_addr=0x1000c000)
646 smc_fake = AmbaFake(pio_addr=0x100e1000)
647 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
648 watchdog_fake = AmbaFake(pio_addr=0x10010000)
649 gpio0_fake = AmbaFake(pio_addr=0x10013000)
650 gpio1_fake = AmbaFake(pio_addr=0x10014000)
651 gpio2_fake = AmbaFake(pio_addr=0x10015000)
652 ssp_fake = AmbaFake(pio_addr=0x1000d000)
653 sci_fake = AmbaFake(pio_addr=0x1000e000)
654 aaci_fake = AmbaFake(pio_addr=0x10004000)
655 mmc_fake = AmbaFake(pio_addr=0x10005000)
656 rtc = PL031(pio_addr=0x10017000, int_num=42)
657 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
658
659
660 # Attach I/O devices that are on chip and also set the appropriate
661 # ranges for the bridge
662 def attachOnChipIO(self, bus, bridge):
663 self.gic.pio = bus.master
664 self.l2x0_fake.pio = bus.master
665 self.a9scu.pio = bus.master
666 self.global_timer.pio = bus.master
667 self.local_cpu_timer.pio = bus.master
668 # Bridge ranges based on excluding what is part of on-chip I/O
669 # (gic, l2x0, a9scu, local_cpu_timer)
670 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
671 self.a9scu.pio_addr - 1),
672 AddrRange(self.flash_fake.pio_addr,
673 self.flash_fake.pio_addr + \
674 self.flash_fake.pio_size - 1)]
675
676 # Set the clock domain for IO objects that are considered
677 # to be "close" to the cores.
678 def onChipIOClkDomain(self, clkdomain):
679 self.gic.clk_domain = clkdomain
680 self.l2x0_fake.clk_domain = clkdomain
681 self.a9scu.clkdomain = clkdomain
682 self.local_cpu_timer.clk_domain = clkdomain
683
684 # Attach I/O devices to specified bus object. Can't do this
685 # earlier, since the bus object itself is typically defined at the
686 # System level.
687 def attachIO(self, bus):
688 self.uart.pio = bus.master
689 self.realview_io.pio = bus.master
690 self.pci_host.pio = bus.master
691 self.timer0.pio = bus.master
692 self.timer1.pio = bus.master
693 self.clcd.pio = bus.master
694 self.clcd.dma = bus.slave
695 self.kmi0.pio = bus.master
696 self.kmi1.pio = bus.master
697 self.cf_ctrl.pio = bus.master
698 self.cf_ctrl.dma = bus.slave
699 self.dmac_fake.pio = bus.master
700 self.uart1_fake.pio = bus.master
701 self.uart2_fake.pio = bus.master
702 self.uart3_fake.pio = bus.master
703 self.smc_fake.pio = bus.master
704 self.sp810_fake.pio = bus.master
705 self.watchdog_fake.pio = bus.master
706 self.gpio0_fake.pio = bus.master
707 self.gpio1_fake.pio = bus.master
708 self.gpio2_fake.pio = bus.master
709 self.ssp_fake.pio = bus.master
710 self.sci_fake.pio = bus.master
711 self.aaci_fake.pio = bus.master
712 self.mmc_fake.pio = bus.master
713 self.rtc.pio = bus.master
714 self.flash_fake.pio = bus.master
715 self.energy_ctrl.pio = bus.master
716
717 # Set the clock domain for IO objects that are considered
718 # to be "far" away from the cores.
719 def offChipIOClkDomain(self, clkdomain):
720 self.uart.clk_domain = clkdomain
721 self.realview_io.clk_domain = clkdomain
722 self.timer0.clk_domain = clkdomain
723 self.timer1.clk_domain = clkdomain
724 self.clcd.clk_domain = clkdomain
725 self.kmi0.clk_domain = clkdomain
726 self.kmi1.clk_domain = clkdomain
727 self.cf_ctrl.clk_domain = clkdomain
728 self.dmac_fake.clk_domain = clkdomain
729 self.uart1_fake.clk_domain = clkdomain
730 self.uart2_fake.clk_domain = clkdomain
731 self.uart3_fake.clk_domain = clkdomain
732 self.smc_fake.clk_domain = clkdomain
733 self.sp810_fake.clk_domain = clkdomain
734 self.watchdog_fake.clk_domain = clkdomain
735 self.gpio0_fake.clk_domain = clkdomain
736 self.gpio1_fake.clk_domain = clkdomain
737 self.gpio2_fake.clk_domain = clkdomain
738 self.ssp_fake.clk_domain = clkdomain
739 self.sci_fake.clk_domain = clkdomain
740 self.aaci_fake.clk_domain = clkdomain
741 self.mmc_fake.clk_domain = clkdomain
742 self.rtc.clk_domain = clkdomain
743 self.flash_fake.clk_domain = clkdomain
744 self.energy_ctrl.clk_domain = clkdomain
745
746# Reference for memory map and interrupt number
747# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
748# Chapter 4: Programmer's Reference
749class RealViewEB(RealView):
750 uart = Pl011(pio_addr=0x10009000, int_num=44)
751 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
752 mcc = VExpressMCC()
753 dcc = CoreTile2A15DCC()
754 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
755 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
756 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
757 clcd = Pl111(pio_addr=0x10020000, int_num=23)
758 kmi0 = Pl050(pio_addr=0x10006000, int_num=20, ps2=PS2Keyboard())
759 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, ps2=PS2TouchKit())
760
761 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
762 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
763 fake_mem=True)
764 dmac_fake = AmbaFake(pio_addr=0x10030000)
765 uart1_fake = AmbaFake(pio_addr=0x1000a000)
766 uart2_fake = AmbaFake(pio_addr=0x1000b000)
767 uart3_fake = AmbaFake(pio_addr=0x1000c000)
768 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
769 smc_fake = AmbaFake(pio_addr=0x100e1000)
770 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
771 watchdog_fake = AmbaFake(pio_addr=0x10010000)
772 gpio0_fake = AmbaFake(pio_addr=0x10013000)
773 gpio1_fake = AmbaFake(pio_addr=0x10014000)
774 gpio2_fake = AmbaFake(pio_addr=0x10015000)
775 ssp_fake = AmbaFake(pio_addr=0x1000d000)
776 sci_fake = AmbaFake(pio_addr=0x1000e000)
777 aaci_fake = AmbaFake(pio_addr=0x10004000)
778 mmc_fake = AmbaFake(pio_addr=0x10005000)
779 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
780 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
781
782 # Attach I/O devices that are on chip and also set the appropriate
783 # ranges for the bridge
784 def attachOnChipIO(self, bus, bridge):
785 self.gic.pio = bus.master
786 self.l2x0_fake.pio = bus.master
787 # Bridge ranges based on excluding what is part of on-chip I/O
788 # (gic, l2x0)
789 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
790 self.gic.cpu_addr - 1),
791 AddrRange(self.flash_fake.pio_addr, Addr.max)]
792
793 # Set the clock domain for IO objects that are considered
794 # to be "close" to the cores.
795 def onChipIOClkDomain(self, clkdomain):
796 self.gic.clk_domain = clkdomain
797 self.l2x0_fake.clk_domain = clkdomain
798
799 # Attach I/O devices to specified bus object. Can't do this
800 # earlier, since the bus object itself is typically defined at the
801 # System level.
802 def attachIO(self, bus):
803 self.uart.pio = bus.master
804 self.realview_io.pio = bus.master
805 self.pci_host.pio = bus.master
806 self.timer0.pio = bus.master
807 self.timer1.pio = bus.master
808 self.clcd.pio = bus.master
809 self.clcd.dma = bus.slave
810 self.kmi0.pio = bus.master
811 self.kmi1.pio = bus.master
812 self.dmac_fake.pio = bus.master
813 self.uart1_fake.pio = bus.master
814 self.uart2_fake.pio = bus.master
815 self.uart3_fake.pio = bus.master
816 self.smc_fake.pio = bus.master
817 self.sp810_fake.pio = bus.master
818 self.watchdog_fake.pio = bus.master
819 self.gpio0_fake.pio = bus.master
820 self.gpio1_fake.pio = bus.master
821 self.gpio2_fake.pio = bus.master
822 self.ssp_fake.pio = bus.master
823 self.sci_fake.pio = bus.master
824 self.aaci_fake.pio = bus.master
825 self.mmc_fake.pio = bus.master
826 self.rtc_fake.pio = bus.master
827 self.flash_fake.pio = bus.master
828 self.smcreg_fake.pio = bus.master
829 self.energy_ctrl.pio = bus.master
830
831 # Set the clock domain for IO objects that are considered
832 # to be "far" away from the cores.
833 def offChipIOClkDomain(self, clkdomain):
834 self.uart.clk_domain = clkdomain
835 self.realview_io.clk_domain = clkdomain
836 self.timer0.clk_domain = clkdomain
837 self.timer1.clk_domain = clkdomain
838 self.clcd.clk_domain = clkdomain
839 self.kmi0.clk_domain = clkdomain
840 self.kmi1.clk_domain = clkdomain
841 self.dmac_fake.clk_domain = clkdomain
842 self.uart1_fake.clk_domain = clkdomain
843 self.uart2_fake.clk_domain = clkdomain
844 self.uart3_fake.clk_domain = clkdomain
845 self.smc_fake.clk_domain = clkdomain
846 self.sp810_fake.clk_domain = clkdomain
847 self.watchdog_fake.clk_domain = clkdomain
848 self.gpio0_fake.clk_domain = clkdomain
849 self.gpio1_fake.clk_domain = clkdomain
850 self.gpio2_fake.clk_domain = clkdomain
851 self.ssp_fake.clk_domain = clkdomain
852 self.sci_fake.clk_domain = clkdomain
853 self.aaci_fake.clk_domain = clkdomain
854 self.mmc_fake.clk_domain = clkdomain
855 self.rtc.clk_domain = clkdomain
856 self.flash_fake.clk_domain = clkdomain
857 self.smcreg_fake.clk_domain = clkdomain
858 self.energy_ctrl.clk_domain = clkdomain
859
860class VExpress_EMM(RealView):
861 _mem_regions = [(Addr('2GB'), Addr('2GB'))]
862
863 # Ranges based on excluding what is part of on-chip I/O (gic,
864 # a9scu)
865 _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'),
866 AddrRange(0x30000000, size='256MB'),
867 AddrRange(0x40000000, size='512MB'),
868 AddrRange(0x18000000, size='64MB'),
869 AddrRange(0x1C000000, size='64MB')]
870
871 # Platform control device (off-chip)
872 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
873 idreg=0x02250000, pio_addr=0x1C010000)
874
875 mcc = VExpressMCC()
876 dcc = CoreTile2A15DCC()
877
878 ### On-chip devices ###
879 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
880 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
881
882 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
883 pio_addr=0x2C080000)
884
885 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
886 pio_addr=0x2b000000, int_num=117,
887 workaround_swap_rb=True)
888
889 def _on_chip_devices(self):
890 devices = [
891 self.gic, self.vgic,
892 self.local_cpu_timer
893 ]
894 if hasattr(self, "gicv2m"):
895 devices.append(self.gicv2m)
896 devices.append(self.hdlcd)
897 return devices
898
899 ### Off-chip devices ###
900 uart = Pl011(pio_addr=0x1c090000, int_num=37)
901 pci_host = GenericPciHost(
902 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
903 pci_pio_base=0)
904
905 generic_timer = GenericTimer(int_phys_s=29, int_phys_ns=30,
906 int_virt=27, int_hyp=26)
907 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
908 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
909 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
910 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard())
911 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit())
912 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
913 io_shift = 2, ctrl_offset = 2, Command = 0x1,
914 BAR0 = 0x1C1A0000, BAR0Size = '256B',
915 BAR1 = 0x1C1A0100, BAR1Size = '4096B',
916 BAR0LegacyIO = True, BAR1LegacyIO = True)
917
918 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
919 conf_table_reported = False)
920 rtc = PL031(pio_addr=0x1C170000, int_num=36)
921
922 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
923 uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
924 uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
925 uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
926 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
927 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
928 aaci_fake = AmbaFake(pio_addr=0x1C040000)
929 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
930 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
931 mmc_fake = AmbaFake(pio_addr=0x1c050000)
932 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000)
933
934 def _off_chip_devices(self):
935 devices = [
936 self.uart,
937 self.realview_io,
938 self.pci_host,
939 self.timer0,
940 self.timer1,
941 self.clcd,
942 self.kmi0,
943 self.kmi1,
944 self.cf_ctrl,
945 self.rtc,
946 self.vram,
947 self.l2x0_fake,
948 self.uart1_fake,
949 self.uart2_fake,
950 self.uart3_fake,
951 self.sp810_fake,
952 self.watchdog_fake,
953 self.aaci_fake,
954 self.lan_fake,
955 self.usb_fake,
956 self.mmc_fake,
957 self.energy_ctrl,
958 ]
959 # Try to attach the I/O if it exists
960 if hasattr(self, "ide"):
961 devices.append(self.ide)
962 if hasattr(self, "ethernet"):
963 devices.append(self.ethernet)
964 return devices
965
966 # Attach any PCI devices that are supported
967 def attachPciDevices(self):
968 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
969 InterruptLine=1, InterruptPin=1)
970 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
971 InterruptLine=2, InterruptPin=2)
972
973 def enableMSIX(self):
974 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
975 self.gicv2m = Gicv2m()
976 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
977
978 def setupBootLoader(self, mem_bus, cur_sys, loc):
979 cur_sys.bootmem = SimpleMemory(range = AddrRange('64MB'),
980 conf_table_reported = False)
981 if mem_bus is not None:
982 cur_sys.bootmem.port = mem_bus.master
983 if not cur_sys.boot_loader:
984 cur_sys.boot_loader = loc('boot_emm.arm')
985 cur_sys.atags_addr = 0x8000000
986 cur_sys.load_offset = 0x80000000
987
988class VExpress_EMM64(VExpress_EMM):
989 # Three memory regions are specified totalling 512GB
990 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
991 (Addr('512GB'), Addr('480GB'))]
992 pci_host = GenericPciHost(
993 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
994 pci_pio_base=0x2f000000)
995
996 def setupBootLoader(self, mem_bus, cur_sys, loc):
997 cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'),
998 conf_table_reported=False)
999 if mem_bus is not None:
1000 cur_sys.bootmem.port = mem_bus.master
1001 if not cur_sys.boot_loader:
1002 cur_sys.boot_loader = loc('boot_emm.arm64')
1003 cur_sys.atags_addr = 0x8000000
1004 cur_sys.load_offset = 0x80000000
1005
1006class VExpress_GEM5_V1_Base(RealView):
1007 """
1008The VExpress gem5 memory map is loosely based on a modified
1009Versatile Express RS1 memory map.
1010
1011The gem5 platform has been designed to implement a subset of the
1012original Versatile Express RS1 memory map. Off-chip peripherals should,
1013when possible, adhere to the Versatile Express memory map. Non-PCI
1014off-chip devices that are gem5-specific should live in the CS5 memory
1015space to avoid conflicts with existing devices that we might want to
1016model in the future. Such devices should normally have interrupts in
1017the gem5-specific SPI range.
1018
1019On-chip peripherals are loosely modeled after the ARM CoreTile Express
1020A15x2 A7x3 memory and interrupt map. In particular, the GIC and
1021Generic Timer have the same interrupt lines and base addresses. Other
1022on-chip devices are gem5 specific.
1023
1024Unlike the original Versatile Express RS2 extended platform, gem5 implements a
1025large contigious DRAM space, without aliases or holes, starting at the
10262GiB boundary. This means that PCI memory is limited to 1GiB.
1027
1028Memory map:
1029 0x00000000-0x03ffffff: Boot memory (CS0)
1030 0x04000000-0x07ffffff: Reserved
1031 0x08000000-0x0bffffff: Reserved (CS0 alias)
1032 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4)
1033 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
1034 0x10000000-0x1000ffff: gem5 energy controller
1035 0x10010000-0x1001ffff: gem5 pseudo-ops
1036
1037 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1)
1038 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2)
1039 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3):
1040 0x1c010000-0x1c01ffff: realview_io (VE system control regs.)
1041 0x1c060000-0x1c06ffff: KMI0 (keyboard)
1042 0x1c070000-0x1c07ffff: KMI1 (mouse)
1043 0x1c090000-0x1c09ffff: UART0
1044 0x1c0a0000-0x1c0affff: UART1 (reserved)
1045 0x1c0b0000-0x1c0bffff: UART2 (reserved)
1046 0x1c0c0000-0x1c0cffff: UART3 (reserved)
1047 0x1c130000-0x1c13ffff: VirtIO (gem5/FM extension)
1048 0x1c140000-0x1c14ffff: VirtIO (gem5/FM extension)
1049 0x1c170000-0x1c17ffff: RTC
1050
1051 0x20000000-0x3fffffff: On-chip peripherals:
1052 0x2b000000-0x2b00ffff: HDLCD
1053
1054 0x2c001000-0x2c001fff: GIC (distributor)
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