1# Copyright (c) 2009-2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
| 1# Copyright (c) 2009-2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
|
| 42# Glenn Bergmans
|
42
| 43
|
| 44from m5.defines import buildEnv
|
43from m5.params import *
44from m5.proxy import *
| 45from m5.params import *
46from m5.proxy import *
|
| 47from m5.util.fdthelper import *
|
45from ClockDomain import ClockDomain
46from VoltageDomain import VoltageDomain
47from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
48from PciHost import *
49from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
50from Ide import *
51from Platform import Platform
52from Terminal import Terminal
53from Uart import Uart
54from SimpleMemory import SimpleMemory
55from Gic import *
56from EnergyCtrl import EnergyCtrl
57from ClockedObject import ClockedObject
58from ClockDomain import SrcClockDomain
59from SubSystem import SubSystem
60from Graphics import ImageFormat
| 48from ClockDomain import ClockDomain
49from VoltageDomain import VoltageDomain
50from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
51from PciHost import *
52from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
53from Ide import *
54from Platform import Platform
55from Terminal import Terminal
56from Uart import Uart
57from SimpleMemory import SimpleMemory
58from Gic import *
59from EnergyCtrl import EnergyCtrl
60from ClockedObject import ClockedObject
61from ClockDomain import SrcClockDomain
62from SubSystem import SubSystem
63from Graphics import ImageFormat
|
| 64from ClockedObject import ClockedObject
|
61
62# Platforms with KVM support should generally use in-kernel GIC
63# emulation. Use a GIC model that automatically switches between
64# gem5's GIC model and KVM's GIC model if KVM is available.
65try:
66 from KvmGic import MuxingKvmGic
67 kvm_gicv2_class = MuxingKvmGic
68except ImportError:
69 # KVM support wasn't compiled into gem5. Fallback to a
70 # software-only GIC.
71 kvm_gicv2_class = Pl390
72 pass
73
74class AmbaPioDevice(BasicPioDevice):
75 type = 'AmbaPioDevice'
76 abstract = True
77 cxx_header = "dev/arm/amba_device.hh"
78 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
79
80class AmbaIntDevice(AmbaPioDevice):
81 type = 'AmbaIntDevice'
82 abstract = True
83 cxx_header = "dev/arm/amba_device.hh"
84 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
85 int_num = Param.UInt32("Interrupt number that connects to GIC")
86 int_delay = Param.Latency("100ns",
87 "Time between action and interrupt generation by device")
88
89class AmbaDmaDevice(DmaDevice):
90 type = 'AmbaDmaDevice'
91 abstract = True
92 cxx_header = "dev/arm/amba_device.hh"
93 pio_addr = Param.Addr("Address for AMBA slave interface")
94 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
95 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
96 int_num = Param.UInt32("Interrupt number that connects to GIC")
97 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
98
99class A9SCU(BasicPioDevice):
100 type = 'A9SCU'
101 cxx_header = "dev/arm/a9scu.hh"
102
103class ArmPciIntRouting(Enum): vals = [
104 'ARM_PCI_INT_STATIC',
105 'ARM_PCI_INT_DEV',
106 'ARM_PCI_INT_PIN',
107 ]
108
109class GenericArmPciHost(GenericPciHost):
110 type = 'GenericArmPciHost'
111 cxx_header = "dev/arm/pci_host.hh"
112
113 int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy")
114 int_base = Param.Unsigned("PCI interrupt base")
115 int_count = Param.Unsigned("Maximum number of interrupts used by this host")
116
117class RealViewCtrl(BasicPioDevice):
118 type = 'RealViewCtrl'
119 cxx_header = "dev/arm/rv_ctrl.hh"
120 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
121 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
122 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
123
| 65
66# Platforms with KVM support should generally use in-kernel GIC
67# emulation. Use a GIC model that automatically switches between
68# gem5's GIC model and KVM's GIC model if KVM is available.
69try:
70 from KvmGic import MuxingKvmGic
71 kvm_gicv2_class = MuxingKvmGic
72except ImportError:
73 # KVM support wasn't compiled into gem5. Fallback to a
74 # software-only GIC.
75 kvm_gicv2_class = Pl390
76 pass
77
78class AmbaPioDevice(BasicPioDevice):
79 type = 'AmbaPioDevice'
80 abstract = True
81 cxx_header = "dev/arm/amba_device.hh"
82 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
83
84class AmbaIntDevice(AmbaPioDevice):
85 type = 'AmbaIntDevice'
86 abstract = True
87 cxx_header = "dev/arm/amba_device.hh"
88 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
89 int_num = Param.UInt32("Interrupt number that connects to GIC")
90 int_delay = Param.Latency("100ns",
91 "Time between action and interrupt generation by device")
92
93class AmbaDmaDevice(DmaDevice):
94 type = 'AmbaDmaDevice'
95 abstract = True
96 cxx_header = "dev/arm/amba_device.hh"
97 pio_addr = Param.Addr("Address for AMBA slave interface")
98 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
99 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
100 int_num = Param.UInt32("Interrupt number that connects to GIC")
101 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
102
103class A9SCU(BasicPioDevice):
104 type = 'A9SCU'
105 cxx_header = "dev/arm/a9scu.hh"
106
107class ArmPciIntRouting(Enum): vals = [
108 'ARM_PCI_INT_STATIC',
109 'ARM_PCI_INT_DEV',
110 'ARM_PCI_INT_PIN',
111 ]
112
113class GenericArmPciHost(GenericPciHost):
114 type = 'GenericArmPciHost'
115 cxx_header = "dev/arm/pci_host.hh"
116
117 int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy")
118 int_base = Param.Unsigned("PCI interrupt base")
119 int_count = Param.Unsigned("Maximum number of interrupts used by this host")
120
121class RealViewCtrl(BasicPioDevice):
122 type = 'RealViewCtrl'
123 cxx_header = "dev/arm/rv_ctrl.hh"
124 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
125 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
126 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
127
|
| 128 def generateDeviceTree(self, state):
129 node = FdtNode("sysreg@%x" % long(self.pio_addr))
130 node.appendCompatible("arm,vexpress-sysreg")
131 node.append(FdtPropertyWords("reg",
132 state.addrCells(self.pio_addr) +
133 state.sizeCells(0x1000) ))
134 node.append(FdtProperty("gpio-controller"))
135 node.append(FdtPropertyWords("#gpio-cells", [2]))
136 node.appendPhandle(self)
137
138 yield node
139
|
124class RealViewOsc(ClockDomain):
125 type = 'RealViewOsc'
126 cxx_header = "dev/arm/rv_ctrl.hh"
127
128 parent = Param.RealViewCtrl(Parent.any, "RealView controller")
129
130 # TODO: We currently don't have the notion of a clock source,
131 # which means we have to associate oscillators with a voltage
132 # source.
133 voltage_domain = Param.VoltageDomain(Parent.voltage_domain,
134 "Voltage domain")
135
136 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
137 # the individual core/logic tile reference manuals for details
138 # about the site/position/dcc/device allocation.
139 site = Param.UInt8("Board Site")
140 position = Param.UInt8("Position in device stack")
141 dcc = Param.UInt8("Daughterboard Configuration Controller")
142 device = Param.UInt8("Device ID")
143
144 freq = Param.Clock("Default frequency")
145
| 140class RealViewOsc(ClockDomain):
141 type = 'RealViewOsc'
142 cxx_header = "dev/arm/rv_ctrl.hh"
143
144 parent = Param.RealViewCtrl(Parent.any, "RealView controller")
145
146 # TODO: We currently don't have the notion of a clock source,
147 # which means we have to associate oscillators with a voltage
148 # source.
149 voltage_domain = Param.VoltageDomain(Parent.voltage_domain,
150 "Voltage domain")
151
152 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
153 # the individual core/logic tile reference manuals for details
154 # about the site/position/dcc/device allocation.
155 site = Param.UInt8("Board Site")
156 position = Param.UInt8("Position in device stack")
157 dcc = Param.UInt8("Daughterboard Configuration Controller")
158 device = Param.UInt8("Device ID")
159
160 freq = Param.Clock("Default frequency")
161
|
| 162 def generateDeviceTree(self, state):
163 phandle = state.phandle(self)
164 node = FdtNode("osc@" + format(long(phandle), 'x'))
165 node.appendCompatible("arm,vexpress-osc")
166 node.append(FdtPropertyWords("arm,vexpress-sysreg,func",
167 [0x1, int(self.device)]))
168 node.append(FdtPropertyWords("#clock-cells", [0]))
169 freq = int(1.0/self.freq.value) # Values are stored as a clock period
170 node.append(FdtPropertyWords("freq-range", [freq, freq]))
171 node.append(FdtPropertyStrings("clock-output-names",
172 ["oscclk" + str(phandle)]))
173 node.appendPhandle(self)
174 yield node
175
|
146class RealViewTemperatureSensor(SimObject):
147 type = 'RealViewTemperatureSensor'
148 cxx_header = "dev/arm/rv_ctrl.hh"
149
150 parent = Param.RealViewCtrl(Parent.any, "RealView controller")
151
152 system = Param.System(Parent.any, "system")
153
154 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
155 # the individual core/logic tile reference manuals for details
156 # about the site/position/dcc/device allocation.
157 site = Param.UInt8("Board Site")
158 position = Param.UInt8("Position in device stack")
159 dcc = Param.UInt8("Daughterboard Configuration Controller")
160 device = Param.UInt8("Device ID")
161
162class VExpressMCC(SubSystem):
163 """ARM V2M-P1 Motherboard Configuration Controller
164
165This subsystem describes a subset of the devices that sit behind the
166motherboard configuration controller on the the ARM Motherboard
167Express (V2M-P1) motherboard. See ARM DUI 0447J for details.
168 """
169
170 class Osc(RealViewOsc):
171 site, position, dcc = (0, 0, 0)
172
173 class Temperature(RealViewTemperatureSensor):
174 site, position, dcc = (0, 0, 0)
175
176 osc_mcc = Osc(device=0, freq="50MHz")
177 osc_clcd = Osc(device=1, freq="23.75MHz")
178 osc_peripheral = Osc(device=2, freq="24MHz")
179 osc_system_bus = Osc(device=4, freq="24MHz")
180
181 # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM).
182 temp_crtl = Temperature(device=0)
183
| 176class RealViewTemperatureSensor(SimObject):
177 type = 'RealViewTemperatureSensor'
178 cxx_header = "dev/arm/rv_ctrl.hh"
179
180 parent = Param.RealViewCtrl(Parent.any, "RealView controller")
181
182 system = Param.System(Parent.any, "system")
183
184 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
185 # the individual core/logic tile reference manuals for details
186 # about the site/position/dcc/device allocation.
187 site = Param.UInt8("Board Site")
188 position = Param.UInt8("Position in device stack")
189 dcc = Param.UInt8("Daughterboard Configuration Controller")
190 device = Param.UInt8("Device ID")
191
192class VExpressMCC(SubSystem):
193 """ARM V2M-P1 Motherboard Configuration Controller
194
195This subsystem describes a subset of the devices that sit behind the
196motherboard configuration controller on the the ARM Motherboard
197Express (V2M-P1) motherboard. See ARM DUI 0447J for details.
198 """
199
200 class Osc(RealViewOsc):
201 site, position, dcc = (0, 0, 0)
202
203 class Temperature(RealViewTemperatureSensor):
204 site, position, dcc = (0, 0, 0)
205
206 osc_mcc = Osc(device=0, freq="50MHz")
207 osc_clcd = Osc(device=1, freq="23.75MHz")
208 osc_peripheral = Osc(device=2, freq="24MHz")
209 osc_system_bus = Osc(device=4, freq="24MHz")
210
211 # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM).
212 temp_crtl = Temperature(device=0)
213
|
| 214 def generateDeviceTree(self, state):
215 node = FdtNode("mcc")
216 node.appendCompatible("arm,vexpress,config-bus")
217 node.append(FdtPropertyWords("arm,vexpress,site", [0]))
218
219 for obj in self._children.values():
220 if issubclass(type(obj), SimObject):
221 node.append(obj.generateDeviceTree(state))
222
223 io_phandle = state.phandle(self.osc_mcc.parent.unproxy(self))
224 node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle))
225
226 yield node
227
|
184class CoreTile2A15DCC(SubSystem):
185 """ARM CoreTile Express A15x2 Daughterboard Configuration Controller
186
187This subsystem describes a subset of the devices that sit behind the
188daughterboard configuration controller on a CoreTile Express A15x2. See
189ARM DUI 0604E for details.
190 """
191
192 class Osc(RealViewOsc):
193 site, position, dcc = (1, 0, 0)
194
195 # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM)
196 osc_cpu = Osc(device=0, freq="60MHz")
197 osc_hsbm = Osc(device=4, freq="40MHz")
198 osc_pxl = Osc(device=5, freq="23.75MHz")
199 osc_smb = Osc(device=6, freq="50MHz")
200 osc_sys = Osc(device=7, freq="60MHz")
201 osc_ddr = Osc(device=8, freq="40MHz")
202
| 228class CoreTile2A15DCC(SubSystem):
229 """ARM CoreTile Express A15x2 Daughterboard Configuration Controller
230
231This subsystem describes a subset of the devices that sit behind the
232daughterboard configuration controller on a CoreTile Express A15x2. See
233ARM DUI 0604E for details.
234 """
235
236 class Osc(RealViewOsc):
237 site, position, dcc = (1, 0, 0)
238
239 # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM)
240 osc_cpu = Osc(device=0, freq="60MHz")
241 osc_hsbm = Osc(device=4, freq="40MHz")
242 osc_pxl = Osc(device=5, freq="23.75MHz")
243 osc_smb = Osc(device=6, freq="50MHz")
244 osc_sys = Osc(device=7, freq="60MHz")
245 osc_ddr = Osc(device=8, freq="40MHz")
246
|
| 247 def generateDeviceTree(self, state):
248 node = FdtNode("dcc")
249 node.appendCompatible("arm,vexpress,config-bus")
250
251 for obj in self._children.values():
252 if isinstance(obj, SimObject):
253 node.append(obj.generateDeviceTree(state))
254
255 io_phandle = state.phandle(self.osc_cpu.parent.unproxy(self))
256 node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle))
257
258 yield node
259
|
203class VGic(PioDevice):
204 type = 'VGic'
205 cxx_header = "dev/arm/vgic.hh"
206 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
207 platform = Param.Platform(Parent.any, "Platform this device is part of.")
208 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
209 hv_addr = Param.Addr(0, "Address for hv control")
210 pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
211 # The number of list registers is not currently configurable at runtime.
212 ppint = Param.UInt32("HV maintenance interrupt number")
213
| 260class VGic(PioDevice):
261 type = 'VGic'
262 cxx_header = "dev/arm/vgic.hh"
263 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
264 platform = Param.Platform(Parent.any, "Platform this device is part of.")
265 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
266 hv_addr = Param.Addr(0, "Address for hv control")
267 pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
268 # The number of list registers is not currently configurable at runtime.
269 ppint = Param.UInt32("HV maintenance interrupt number")
270
|
| 271 def generateDeviceTree(self, state):
272 gic = self.gic.unproxy(self)
273
274 node = FdtNode("interrupt-controller")
275 node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic",
276 "arm,cortex-a9-gic"])
277 node.append(FdtPropertyWords("#interrupt-cells", [3]))
278 node.append(FdtPropertyWords("#address-cells", [0]))
279 node.append(FdtProperty("interrupt-controller"))
280
281 regs = (
282 state.addrCells(gic.dist_addr) +
283 state.sizeCells(0x1000) +
284 state.addrCells(gic.cpu_addr) +
285 state.sizeCells(0x1000) +
286 state.addrCells(self.hv_addr) +
287 state.sizeCells(0x2000) +
288 state.addrCells(self.vcpu_addr) +
289 state.sizeCells(0x2000) )
290
291 node.append(FdtPropertyWords("reg", regs))
292 node.append(FdtPropertyWords("interrupts",
293 [1, int(self.ppint)-16, 0xf04]))
294
295 node.appendPhandle(gic)
296
297 yield node
298
|
214class AmbaFake(AmbaPioDevice):
215 type = 'AmbaFake'
216 cxx_header = "dev/arm/amba_fake.hh"
217 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
218 amba_id = 0;
219
220class Pl011(Uart):
221 type = 'Pl011'
222 cxx_header = "dev/arm/pl011.hh"
223 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
224 int_num = Param.UInt32("Interrupt number that connects to GIC")
225 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
226 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
227
| 299class AmbaFake(AmbaPioDevice):
300 type = 'AmbaFake'
301 cxx_header = "dev/arm/amba_fake.hh"
302 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
303 amba_id = 0;
304
305class Pl011(Uart):
306 type = 'Pl011'
307 cxx_header = "dev/arm/pl011.hh"
308 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
309 int_num = Param.UInt32("Interrupt number that connects to GIC")
310 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
311 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
312
|
| 313 def generateDeviceTree(self, state):
314 node = self.generateBasicPioDeviceNode(state, 'uart', self.pio_addr,
315 0x1000, [int(self.int_num)])
316 node.appendCompatible(["arm,pl011", "arm,primecell"])
317
318 # Hardcoded reference to the realview platform clocks, because the
319 # clk_domain can only store one clock (i.e. it is not a VectorParam)
320 realview = self._parent.unproxy(self)
321 node.append(FdtPropertyWords("clocks",
322 [state.phandle(realview.mcc.osc_peripheral),
323 state.phandle(realview.dcc.osc_smb)]))
324 node.append(FdtPropertyStrings("clock-names", ["uartclk", "apb_pclk"]))
325 yield node
326
|
228class Sp804(AmbaPioDevice):
229 type = 'Sp804'
230 cxx_header = "dev/arm/timer_sp804.hh"
231 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
232 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
233 clock0 = Param.Clock('1MHz', "Clock speed of the input")
234 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
235 clock1 = Param.Clock('1MHz', "Clock speed of the input")
236 amba_id = 0x00141804
237
238class A9GlobalTimer(BasicPioDevice):
239 type = 'A9GlobalTimer'
240 cxx_header = "dev/arm/timer_a9global.hh"
241 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
242 int_num = Param.UInt32("Interrrupt number that connects to GIC")
243
244class CpuLocalTimer(BasicPioDevice):
245 type = 'CpuLocalTimer'
246 cxx_header = "dev/arm/timer_cpulocal.hh"
247 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
248 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
249 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
250
251class GenericTimer(ClockedObject):
252 type = 'GenericTimer'
253 cxx_header = "dev/arm/generic_timer.hh"
254 system = Param.ArmSystem(Parent.any, "system")
255 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
256 # @todo: for now only two timers per CPU is supported, which is the
257 # normal behaviour when security extensions are disabled.
258 int_phys = Param.UInt32("Physical timer interrupt number")
259 int_virt = Param.UInt32("Virtual timer interrupt number")
260
| 327class Sp804(AmbaPioDevice):
328 type = 'Sp804'
329 cxx_header = "dev/arm/timer_sp804.hh"
330 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
331 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
332 clock0 = Param.Clock('1MHz', "Clock speed of the input")
333 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
334 clock1 = Param.Clock('1MHz', "Clock speed of the input")
335 amba_id = 0x00141804
336
337class A9GlobalTimer(BasicPioDevice):
338 type = 'A9GlobalTimer'
339 cxx_header = "dev/arm/timer_a9global.hh"
340 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
341 int_num = Param.UInt32("Interrrupt number that connects to GIC")
342
343class CpuLocalTimer(BasicPioDevice):
344 type = 'CpuLocalTimer'
345 cxx_header = "dev/arm/timer_cpulocal.hh"
346 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
347 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
348 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
349
350class GenericTimer(ClockedObject):
351 type = 'GenericTimer'
352 cxx_header = "dev/arm/generic_timer.hh"
353 system = Param.ArmSystem(Parent.any, "system")
354 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
355 # @todo: for now only two timers per CPU is supported, which is the
356 # normal behaviour when security extensions are disabled.
357 int_phys = Param.UInt32("Physical timer interrupt number")
358 int_virt = Param.UInt32("Virtual timer interrupt number")
359
|
| 360 def generateDeviceTree(self, state):
361 node = FdtNode("timer")
362
363 node.appendCompatible(["arm,cortex-a15-timer",
364 "arm,armv7-timer",
365 "arm,armv8-timer"])
366 node.append(FdtPropertyWords("interrupts",
367 [1, int(self.int_phys) - 16, 0xf08,
368 1, int(self.int_virt) - 16, 0xf08]))
369 clock = state.phandle(self.clk_domain.unproxy(self))
370 node.append(FdtPropertyWords("clocks", clock))
371
372 yield node
373
|
261class GenericTimerMem(PioDevice):
262 type = 'GenericTimerMem'
263 cxx_header = "dev/arm/generic_timer.hh"
264 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
265
266 base = Param.Addr(0, "Base address")
267
268 int_phys = Param.UInt32("Interrupt number")
269 int_virt = Param.UInt32("Interrupt number")
270
271class PL031(AmbaIntDevice):
272 type = 'PL031'
273 cxx_header = "dev/arm/rtc_pl031.hh"
274 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
275 amba_id = 0x00341031
276
| 374class GenericTimerMem(PioDevice):
375 type = 'GenericTimerMem'
376 cxx_header = "dev/arm/generic_timer.hh"
377 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
378
379 base = Param.Addr(0, "Base address")
380
381 int_phys = Param.UInt32("Interrupt number")
382 int_virt = Param.UInt32("Interrupt number")
383
384class PL031(AmbaIntDevice):
385 type = 'PL031'
386 cxx_header = "dev/arm/rtc_pl031.hh"
387 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
388 amba_id = 0x00341031
389
|
| 390 def generateDeviceTree(self, state):
391 node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr,
392 0x1000, [int(self.int_num)])
393
394 node.appendCompatible(["arm,pl031", "arm,primecell"])
395 clock = state.phandle(self.clk_domain.unproxy(self))
396 node.append(FdtPropertyWords("clocks", clock))
397
398 yield node
399
|
277class Pl050(AmbaIntDevice):
278 type = 'Pl050'
279 cxx_header = "dev/arm/kmi.hh"
280 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
281 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
282 int_delay = '1us'
283 amba_id = 0x00141050
284
| 400class Pl050(AmbaIntDevice):
401 type = 'Pl050'
402 cxx_header = "dev/arm/kmi.hh"
403 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
404 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
405 int_delay = '1us'
406 amba_id = 0x00141050
407
|
| 408 def generateDeviceTree(self, state):
409 node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr,
410 0x1000, [int(self.int_num)])
411
412 node.appendCompatible(["arm,pl050", "arm,primecell"])
413 clock = state.phandle(self.clk_domain.unproxy(self))
414 node.append(FdtPropertyWords("clocks", clock))
415
416 yield node
417
|
285class Pl111(AmbaDmaDevice):
286 type = 'Pl111'
287 cxx_header = "dev/arm/pl111.hh"
288 pixel_clock = Param.Clock('24MHz', "Pixel clock")
289 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
290 amba_id = 0x00141111
291 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
292
293class HDLcd(AmbaDmaDevice):
294 type = 'HDLcd'
295 cxx_header = "dev/arm/hdlcd.hh"
296 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer "
297 "display")
298 amba_id = 0x00141000
299 workaround_swap_rb = Param.Bool(False, "Workaround incorrect color "
300 "selector order in some kernels")
301 workaround_dma_line_count = Param.Bool(True, "Workaround incorrect "
302 "DMA line count (off by 1)")
303 enable_capture = Param.Bool(True, "capture frame to "
304 "system.framebuffer.{extension}")
305 frame_format = Param.ImageFormat("Auto",
306 "image format of the captured frame")
307
308 pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range")
309
310 pxl_clk = Param.ClockDomain("Pixel clock source")
311 pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch")
312 virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate "
313 "in KVM mode")
314
| 418class Pl111(AmbaDmaDevice):
419 type = 'Pl111'
420 cxx_header = "dev/arm/pl111.hh"
421 pixel_clock = Param.Clock('24MHz', "Pixel clock")
422 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
423 amba_id = 0x00141111
424 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
425
426class HDLcd(AmbaDmaDevice):
427 type = 'HDLcd'
428 cxx_header = "dev/arm/hdlcd.hh"
429 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer "
430 "display")
431 amba_id = 0x00141000
432 workaround_swap_rb = Param.Bool(False, "Workaround incorrect color "
433 "selector order in some kernels")
434 workaround_dma_line_count = Param.Bool(True, "Workaround incorrect "
435 "DMA line count (off by 1)")
436 enable_capture = Param.Bool(True, "capture frame to "
437 "system.framebuffer.{extension}")
438 frame_format = Param.ImageFormat("Auto",
439 "image format of the captured frame")
440
441 pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range")
442
443 pxl_clk = Param.ClockDomain("Pixel clock source")
444 pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch")
445 virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate "
446 "in KVM mode")
447
|
| 448 def generateDeviceTree(self, state):
449 # Interrupt number is hardcoded; it is not a property of this class
450 node = self.generateBasicPioDeviceNode(state, 'hdlcd',
451 self.pio_addr, 0x1000, [63])
452
453 node.appendCompatible(["arm,hdlcd"])
454 node.append(FdtPropertyWords("clocks", state.phandle(self.pxl_clk)))
455 node.append(FdtPropertyStrings("clock-names", ["pxlclk"]))
456
457 # This driver is disabled by default since the required DT nodes
458 # haven't been standardized yet. To use it, override this status to
459 # "ok" and add the display configuration nodes required by the driver.
460 # See the driver for more information.
461 node.append(FdtPropertyStrings("status", ["disabled"]))
462
463 yield node
464
|
315class RealView(Platform):
316 type = 'RealView'
317 cxx_header = "dev/arm/realview.hh"
318 system = Param.System(Parent.any, "system")
319 _mem_regions = [(Addr(0), Addr('256MB'))]
320
321 def _on_chip_devices(self):
322 return []
323
324 def _off_chip_devices(self):
325 return []
326
327 _off_chip_ranges = []
328
329 def _attach_device(self, device, bus, dma_ports=None):
330 if hasattr(device, "pio"):
331 device.pio = bus.master
332 if hasattr(device, "dma"):
333 if dma_ports is None:
334 device.dma = bus.slave
335 else:
336 dma_ports.append(device.dma)
337
338 def _attach_io(self, devices, *args, **kwargs):
339 for d in devices:
340 self._attach_device(d, *args, **kwargs)
341
342 def _attach_clk(self, devices, clkdomain):
343 for d in devices:
344 if hasattr(d, "clk_domain"):
345 d.clk_domain = clkdomain
346
347 def attachPciDevices(self):
348 pass
349
350 def enableMSIX(self):
351 pass
352
353 def onChipIOClkDomain(self, clkdomain):
354 self._attach_clk(self._on_chip_devices(), clkdomain)
355
356 def offChipIOClkDomain(self, clkdomain):
357 self._attach_clk(self._off_chip_devices(), clkdomain)
358
359 def attachOnChipIO(self, bus, bridge=None, *args, **kwargs):
360 self._attach_io(self._on_chip_devices(), bus, *args, **kwargs)
361 if bridge:
362 bridge.ranges = self._off_chip_ranges
363
364 def attachIO(self, *args, **kwargs):
365 self._attach_io(self._off_chip_devices(), *args, **kwargs)
366
367 def setupBootLoader(self, mem_bus, cur_sys, loc):
368 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
369 conf_table_reported = False)
370 self.nvmem.port = mem_bus.master
371 cur_sys.boot_loader = loc('boot.arm')
372 cur_sys.atags_addr = 0x100
373 cur_sys.load_offset = 0
374
| 465class RealView(Platform):
466 type = 'RealView'
467 cxx_header = "dev/arm/realview.hh"
468 system = Param.System(Parent.any, "system")
469 _mem_regions = [(Addr(0), Addr('256MB'))]
470
471 def _on_chip_devices(self):
472 return []
473
474 def _off_chip_devices(self):
475 return []
476
477 _off_chip_ranges = []
478
479 def _attach_device(self, device, bus, dma_ports=None):
480 if hasattr(device, "pio"):
481 device.pio = bus.master
482 if hasattr(device, "dma"):
483 if dma_ports is None:
484 device.dma = bus.slave
485 else:
486 dma_ports.append(device.dma)
487
488 def _attach_io(self, devices, *args, **kwargs):
489 for d in devices:
490 self._attach_device(d, *args, **kwargs)
491
492 def _attach_clk(self, devices, clkdomain):
493 for d in devices:
494 if hasattr(d, "clk_domain"):
495 d.clk_domain = clkdomain
496
497 def attachPciDevices(self):
498 pass
499
500 def enableMSIX(self):
501 pass
502
503 def onChipIOClkDomain(self, clkdomain):
504 self._attach_clk(self._on_chip_devices(), clkdomain)
505
506 def offChipIOClkDomain(self, clkdomain):
507 self._attach_clk(self._off_chip_devices(), clkdomain)
508
509 def attachOnChipIO(self, bus, bridge=None, *args, **kwargs):
510 self._attach_io(self._on_chip_devices(), bus, *args, **kwargs)
511 if bridge:
512 bridge.ranges = self._off_chip_ranges
513
514 def attachIO(self, *args, **kwargs):
515 self._attach_io(self._off_chip_devices(), *args, **kwargs)
516
517 def setupBootLoader(self, mem_bus, cur_sys, loc):
518 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
519 conf_table_reported = False)
520 self.nvmem.port = mem_bus.master
521 cur_sys.boot_loader = loc('boot.arm')
522 cur_sys.atags_addr = 0x100
523 cur_sys.load_offset = 0
524
|
| 525 def generateDeviceTree(self, state):
526 node = FdtNode("/") # Things in this module need to end up in the root
527 node.append(FdtPropertyWords("interrupt-parent",
528 state.phandle(self.gic)))
|
375
| 529
|
| 530 for device in [getattr(self, c) for c in self._children]:
531 if issubclass(type(device), SimObject):
532 subnode = device.generateDeviceTree(state)
533 node.append(subnode)
534
535 yield node
536
537 def annotateCpuDeviceNode(self, cpu, state):
538 cpu.append(FdtPropertyStrings("enable-method", "spin-table"))
539 cpu.append(FdtPropertyWords("cpu-release-addr", \
540 state.addrCells(0x8000fff8)))
541
|
376# Reference for memory map and interrupt number
377# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
378# Chapter 4: Programmer's Reference
379class RealViewPBX(RealView):
380 uart = Pl011(pio_addr=0x10009000, int_num=44)
381 realview_io = RealViewCtrl(pio_addr=0x10000000)
382 mcc = VExpressMCC()
383 dcc = CoreTile2A15DCC()
384 gic = Pl390()
385 pci_host = GenericPciHost(
386 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
387 pci_pio_base=0)
388 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
389 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
390 global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200)
391 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
392 pio_addr=0x1f000600)
393 clcd = Pl111(pio_addr=0x10020000, int_num=55)
394 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
395 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
396 a9scu = A9SCU(pio_addr=0x1f000000)
397 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
398 io_shift = 1, ctrl_offset = 2, Command = 0x1,
399 BAR0 = 0x18000000, BAR0Size = '16B',
400 BAR1 = 0x18000100, BAR1Size = '1B',
401 BAR0LegacyIO = True, BAR1LegacyIO = True)
402
403
404 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
405 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
406 fake_mem=True)
407 dmac_fake = AmbaFake(pio_addr=0x10030000)
408 uart1_fake = AmbaFake(pio_addr=0x1000a000)
409 uart2_fake = AmbaFake(pio_addr=0x1000b000)
410 uart3_fake = AmbaFake(pio_addr=0x1000c000)
411 smc_fake = AmbaFake(pio_addr=0x100e1000)
412 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
413 watchdog_fake = AmbaFake(pio_addr=0x10010000)
414 gpio0_fake = AmbaFake(pio_addr=0x10013000)
415 gpio1_fake = AmbaFake(pio_addr=0x10014000)
416 gpio2_fake = AmbaFake(pio_addr=0x10015000)
417 ssp_fake = AmbaFake(pio_addr=0x1000d000)
418 sci_fake = AmbaFake(pio_addr=0x1000e000)
419 aaci_fake = AmbaFake(pio_addr=0x10004000)
420 mmc_fake = AmbaFake(pio_addr=0x10005000)
421 rtc = PL031(pio_addr=0x10017000, int_num=42)
422 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
423
424
425 # Attach I/O devices that are on chip and also set the appropriate
426 # ranges for the bridge
427 def attachOnChipIO(self, bus, bridge):
428 self.gic.pio = bus.master
429 self.l2x0_fake.pio = bus.master
430 self.a9scu.pio = bus.master
431 self.global_timer.pio = bus.master
432 self.local_cpu_timer.pio = bus.master
433 # Bridge ranges based on excluding what is part of on-chip I/O
434 # (gic, l2x0, a9scu, local_cpu_timer)
435 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
436 self.a9scu.pio_addr - 1),
437 AddrRange(self.flash_fake.pio_addr,
438 self.flash_fake.pio_addr + \
439 self.flash_fake.pio_size - 1)]
440
441 # Set the clock domain for IO objects that are considered
442 # to be "close" to the cores.
443 def onChipIOClkDomain(self, clkdomain):
444 self.gic.clk_domain = clkdomain
445 self.l2x0_fake.clk_domain = clkdomain
446 self.a9scu.clkdomain = clkdomain
447 self.local_cpu_timer.clk_domain = clkdomain
448
449 # Attach I/O devices to specified bus object. Can't do this
450 # earlier, since the bus object itself is typically defined at the
451 # System level.
452 def attachIO(self, bus):
453 self.uart.pio = bus.master
454 self.realview_io.pio = bus.master
455 self.pci_host.pio = bus.master
456 self.timer0.pio = bus.master
457 self.timer1.pio = bus.master
458 self.clcd.pio = bus.master
459 self.clcd.dma = bus.slave
460 self.kmi0.pio = bus.master
461 self.kmi1.pio = bus.master
462 self.cf_ctrl.pio = bus.master
463 self.cf_ctrl.dma = bus.slave
464 self.dmac_fake.pio = bus.master
465 self.uart1_fake.pio = bus.master
466 self.uart2_fake.pio = bus.master
467 self.uart3_fake.pio = bus.master
468 self.smc_fake.pio = bus.master
469 self.sp810_fake.pio = bus.master
470 self.watchdog_fake.pio = bus.master
471 self.gpio0_fake.pio = bus.master
472 self.gpio1_fake.pio = bus.master
473 self.gpio2_fake.pio = bus.master
474 self.ssp_fake.pio = bus.master
475 self.sci_fake.pio = bus.master
476 self.aaci_fake.pio = bus.master
477 self.mmc_fake.pio = bus.master
478 self.rtc.pio = bus.master
479 self.flash_fake.pio = bus.master
480 self.energy_ctrl.pio = bus.master
481
482 # Set the clock domain for IO objects that are considered
483 # to be "far" away from the cores.
484 def offChipIOClkDomain(self, clkdomain):
485 self.uart.clk_domain = clkdomain
486 self.realview_io.clk_domain = clkdomain
487 self.timer0.clk_domain = clkdomain
488 self.timer1.clk_domain = clkdomain
489 self.clcd.clk_domain = clkdomain
490 self.kmi0.clk_domain = clkdomain
491 self.kmi1.clk_domain = clkdomain
492 self.cf_ctrl.clk_domain = clkdomain
493 self.dmac_fake.clk_domain = clkdomain
494 self.uart1_fake.clk_domain = clkdomain
495 self.uart2_fake.clk_domain = clkdomain
496 self.uart3_fake.clk_domain = clkdomain
497 self.smc_fake.clk_domain = clkdomain
498 self.sp810_fake.clk_domain = clkdomain
499 self.watchdog_fake.clk_domain = clkdomain
500 self.gpio0_fake.clk_domain = clkdomain
501 self.gpio1_fake.clk_domain = clkdomain
502 self.gpio2_fake.clk_domain = clkdomain
503 self.ssp_fake.clk_domain = clkdomain
504 self.sci_fake.clk_domain = clkdomain
505 self.aaci_fake.clk_domain = clkdomain
506 self.mmc_fake.clk_domain = clkdomain
507 self.rtc.clk_domain = clkdomain
508 self.flash_fake.clk_domain = clkdomain
509 self.energy_ctrl.clk_domain = clkdomain
510
511# Reference for memory map and interrupt number
512# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
513# Chapter 4: Programmer's Reference
514class RealViewEB(RealView):
515 uart = Pl011(pio_addr=0x10009000, int_num=44)
516 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
517 mcc = VExpressMCC()
518 dcc = CoreTile2A15DCC()
519 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
520 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
521 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
522 clcd = Pl111(pio_addr=0x10020000, int_num=23)
523 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
524 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
525
526 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
527 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
528 fake_mem=True)
529 dmac_fake = AmbaFake(pio_addr=0x10030000)
530 uart1_fake = AmbaFake(pio_addr=0x1000a000)
531 uart2_fake = AmbaFake(pio_addr=0x1000b000)
532 uart3_fake = AmbaFake(pio_addr=0x1000c000)
533 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
534 smc_fake = AmbaFake(pio_addr=0x100e1000)
535 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
536 watchdog_fake = AmbaFake(pio_addr=0x10010000)
537 gpio0_fake = AmbaFake(pio_addr=0x10013000)
538 gpio1_fake = AmbaFake(pio_addr=0x10014000)
539 gpio2_fake = AmbaFake(pio_addr=0x10015000)
540 ssp_fake = AmbaFake(pio_addr=0x1000d000)
541 sci_fake = AmbaFake(pio_addr=0x1000e000)
542 aaci_fake = AmbaFake(pio_addr=0x10004000)
543 mmc_fake = AmbaFake(pio_addr=0x10005000)
544 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
545 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
546
547 # Attach I/O devices that are on chip and also set the appropriate
548 # ranges for the bridge
549 def attachOnChipIO(self, bus, bridge):
550 self.gic.pio = bus.master
551 self.l2x0_fake.pio = bus.master
552 # Bridge ranges based on excluding what is part of on-chip I/O
553 # (gic, l2x0)
554 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
555 self.gic.cpu_addr - 1),
556 AddrRange(self.flash_fake.pio_addr, Addr.max)]
557
558 # Set the clock domain for IO objects that are considered
559 # to be "close" to the cores.
560 def onChipIOClkDomain(self, clkdomain):
561 self.gic.clk_domain = clkdomain
562 self.l2x0_fake.clk_domain = clkdomain
563
564 # Attach I/O devices to specified bus object. Can't do this
565 # earlier, since the bus object itself is typically defined at the
566 # System level.
567 def attachIO(self, bus):
568 self.uart.pio = bus.master
569 self.realview_io.pio = bus.master
570 self.pci_host.pio = bus.master
571 self.timer0.pio = bus.master
572 self.timer1.pio = bus.master
573 self.clcd.pio = bus.master
574 self.clcd.dma = bus.slave
575 self.kmi0.pio = bus.master
576 self.kmi1.pio = bus.master
577 self.dmac_fake.pio = bus.master
578 self.uart1_fake.pio = bus.master
579 self.uart2_fake.pio = bus.master
580 self.uart3_fake.pio = bus.master
581 self.smc_fake.pio = bus.master
582 self.sp810_fake.pio = bus.master
583 self.watchdog_fake.pio = bus.master
584 self.gpio0_fake.pio = bus.master
585 self.gpio1_fake.pio = bus.master
586 self.gpio2_fake.pio = bus.master
587 self.ssp_fake.pio = bus.master
588 self.sci_fake.pio = bus.master
589 self.aaci_fake.pio = bus.master
590 self.mmc_fake.pio = bus.master
591 self.rtc_fake.pio = bus.master
592 self.flash_fake.pio = bus.master
593 self.smcreg_fake.pio = bus.master
594 self.energy_ctrl.pio = bus.master
595
596 # Set the clock domain for IO objects that are considered
597 # to be "far" away from the cores.
598 def offChipIOClkDomain(self, clkdomain):
599 self.uart.clk_domain = clkdomain
600 self.realview_io.clk_domain = clkdomain
601 self.timer0.clk_domain = clkdomain
602 self.timer1.clk_domain = clkdomain
603 self.clcd.clk_domain = clkdomain
604 self.kmi0.clk_domain = clkdomain
605 self.kmi1.clk_domain = clkdomain
606 self.dmac_fake.clk_domain = clkdomain
607 self.uart1_fake.clk_domain = clkdomain
608 self.uart2_fake.clk_domain = clkdomain
609 self.uart3_fake.clk_domain = clkdomain
610 self.smc_fake.clk_domain = clkdomain
611 self.sp810_fake.clk_domain = clkdomain
612 self.watchdog_fake.clk_domain = clkdomain
613 self.gpio0_fake.clk_domain = clkdomain
614 self.gpio1_fake.clk_domain = clkdomain
615 self.gpio2_fake.clk_domain = clkdomain
616 self.ssp_fake.clk_domain = clkdomain
617 self.sci_fake.clk_domain = clkdomain
618 self.aaci_fake.clk_domain = clkdomain
619 self.mmc_fake.clk_domain = clkdomain
620 self.rtc.clk_domain = clkdomain
621 self.flash_fake.clk_domain = clkdomain
622 self.smcreg_fake.clk_domain = clkdomain
623 self.energy_ctrl.clk_domain = clkdomain
624
625class VExpress_EMM(RealView):
626 _mem_regions = [(Addr('2GB'), Addr('2GB'))]
627
628 # Ranges based on excluding what is part of on-chip I/O (gic,
629 # a9scu)
630 _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'),
631 AddrRange(0x30000000, size='256MB'),
632 AddrRange(0x40000000, size='512MB'),
633 AddrRange(0x18000000, size='64MB'),
634 AddrRange(0x1C000000, size='64MB')]
635
636 # Platform control device (off-chip)
637 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
638 idreg=0x02250000, pio_addr=0x1C010000)
639
640 mcc = VExpressMCC()
641 dcc = CoreTile2A15DCC()
642
643 ### On-chip devices ###
644 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
645 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
646
647 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
648 pio_addr=0x2C080000)
649
650 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
651 pio_addr=0x2b000000, int_num=117,
652 workaround_swap_rb=True)
653
654 def _on_chip_devices(self):
655 devices = [
656 self.gic, self.vgic,
657 self.local_cpu_timer
658 ]
659 if hasattr(self, "gicv2m"):
660 devices.append(self.gicv2m)
661 devices.append(self.hdlcd)
662 return devices
663
664 ### Off-chip devices ###
665 uart = Pl011(pio_addr=0x1c090000, int_num=37)
666 pci_host = GenericPciHost(
667 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
668 pci_pio_base=0)
669
670 generic_timer = GenericTimer(int_phys=29, int_virt=27)
671 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
672 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
673 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
674 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
675 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
676 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
677 io_shift = 2, ctrl_offset = 2, Command = 0x1,
678 BAR0 = 0x1C1A0000, BAR0Size = '256B',
679 BAR1 = 0x1C1A0100, BAR1Size = '4096B',
680 BAR0LegacyIO = True, BAR1LegacyIO = True)
681
682 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
683 conf_table_reported = False)
684 rtc = PL031(pio_addr=0x1C170000, int_num=36)
685
686 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
687 uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
688 uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
689 uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
690 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
691 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
692 aaci_fake = AmbaFake(pio_addr=0x1C040000)
693 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
694 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
695 mmc_fake = AmbaFake(pio_addr=0x1c050000)
696 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000)
697
698 def _off_chip_devices(self):
699 devices = [
700 self.uart,
701 self.realview_io,
702 self.pci_host,
703 self.timer0,
704 self.timer1,
705 self.clcd,
706 self.kmi0,
707 self.kmi1,
708 self.cf_ctrl,
709 self.rtc,
710 self.vram,
711 self.l2x0_fake,
712 self.uart1_fake,
713 self.uart2_fake,
714 self.uart3_fake,
715 self.sp810_fake,
716 self.watchdog_fake,
717 self.aaci_fake,
718 self.lan_fake,
719 self.usb_fake,
720 self.mmc_fake,
721 self.energy_ctrl,
722 ]
723 # Try to attach the I/O if it exists
724 if hasattr(self, "ide"):
725 devices.append(self.ide)
726 if hasattr(self, "ethernet"):
727 devices.append(self.ethernet)
728 return devices
729
730 # Attach any PCI devices that are supported
731 def attachPciDevices(self):
732 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
733 InterruptLine=1, InterruptPin=1)
734 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
735 InterruptLine=2, InterruptPin=2)
736
737 def enableMSIX(self):
738 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
739 self.gicv2m = Gicv2m()
740 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
741
742 def setupBootLoader(self, mem_bus, cur_sys, loc):
743 self.nvmem = SimpleMemory(range = AddrRange('64MB'),
744 conf_table_reported = False)
745 self.nvmem.port = mem_bus.master
746 if not cur_sys.boot_loader:
747 cur_sys.boot_loader = loc('boot_emm.arm')
748 cur_sys.atags_addr = 0x8000000
749 cur_sys.load_offset = 0x80000000
750
751class VExpress_EMM64(VExpress_EMM):
752 # Three memory regions are specified totalling 512GB
753 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
754 (Addr('512GB'), Addr('480GB'))]
755 pci_host = GenericPciHost(
756 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
757 pci_pio_base=0x2f000000)
758
759 def setupBootLoader(self, mem_bus, cur_sys, loc):
760 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
761 conf_table_reported=False)
762 self.nvmem.port = mem_bus.master
763 if not cur_sys.boot_loader:
764 cur_sys.boot_loader = loc('boot_emm.arm64')
765 cur_sys.atags_addr = 0x8000000
766 cur_sys.load_offset = 0x80000000
767
768
769class VExpress_GEM5_V1(RealView):
770 """
771The VExpress gem5 memory map is loosely based on a modified
772Versatile Express RS1 memory map.
773
774The gem5 platform has been designed to implement a subset of the
775original Versatile Express RS1 memory map. Off-chip peripherals should,
776when possible, adhere to the Versatile Express memory map. Non-PCI
777off-chip devices that are gem5-specific should live in the CS5 memory
778space to avoid conflicts with existing devices that we might want to
779model in the future. Such devices should normally have interrupts in
780the gem5-specific SPI range.
781
782On-chip peripherals are loosely modeled after the ARM CoreTile Express
783A15x2 A7x3 memory and interrupt map. In particular, the GIC and
784Generic Timer have the same interrupt lines and base addresses. Other
785on-chip devices are gem5 specific.
786
787Unlike the original Versatile Express RS2 extended platform, gem5 implements a
788large contigious DRAM space, without aliases or holes, starting at the
7892GiB boundary. This means that PCI memory is limited to 1GiB.
790
791Memory map:
792 0x00000000-0x03ffffff: Boot memory (CS0)
793 0x04000000-0x07ffffff: Reserved
794 0x08000000-0x0bffffff: Reserved (CS0 alias)
795 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4)
796 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
797 0x10000000-0x1000ffff: gem5 energy controller
798 0x10010000-0x1001ffff: gem5 pseudo-ops
799
800 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1)
801 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2)
802 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3):
803 0x1c010000-0x1c01ffff: realview_io (VE system control regs.)
804 0x1c060000-0x1c06ffff: KMI0 (keyboard)
805 0x1c070000-0x1c07ffff: KMI1 (mouse)
806 0x1c090000-0x1c09ffff: UART0
807 0x1c0a0000-0x1c0affff: UART1 (reserved)
808 0x1c0b0000-0x1c0bffff: UART2 (reserved)
809 0x1c0c0000-0x1c0cffff: UART3 (reserved)
810 0x1c170000-0x1c17ffff: RTC
811
812 0x20000000-0x3fffffff: On-chip peripherals:
813 0x2b000000-0x2b00ffff: HDLCD
814
815 0x2c001000-0x2c001fff: GIC (distributor)
816 0x2c002000-0x2c0020ff: GIC (CPU interface)
817 0x2c004000-0x2c005fff: vGIC (HV)
818 0x2c006000-0x2c007fff: vGIC (VCPU)
819 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0
820
821 0x2d000000-0x2d00ffff: GPU (reserved)
822
823 0x2f000000-0x2fffffff: PCI IO space
824 0x30000000-0x3fffffff: PCI config space
825
826 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory
827
828 0x80000000-X: DRAM
829
830Interrupts:
831 0- 15: Software generated interrupts (SGIs)
832 16- 31: On-chip private peripherals (PPIs)
833 25 : vgic
834 26 : generic_timer (hyp)
835 27 : generic_timer (virt)
836 28 : Reserved (Legacy FIQ)
837 29 : generic_timer (phys, sec)
838 30 : generic_timer (phys, non-sec)
839 31 : Reserved (Legacy IRQ)
840 32- 95: Mother board peripherals (SPIs)
841 32 : Reserved (SP805)
842 33 : Reserved (IOFPGA SW int)
843 34-35: Reserved (SP804)
844 36 : RTC
845 37-40: uart0-uart3
846 41-42: Reserved (PL180)
847 43 : Reserved (AACI)
848 44-45: kmi0-kmi1
849 46 : Reserved (CLCD)
850 47 : Reserved (Ethernet)
851 48 : Reserved (USB)
852 95-255: On-chip interrupt sources (we use these for
853 gem5-specific devices, SPIs)
854 95 : HDLCD
855 96- 98: GPU (reserved)
856 100-103: PCI
857 256-319: MSI frame 0 (gem5-specific, SPIs)
858 320-511: Unused
859
860 """
861
862 # Everything above 2GiB is memory
863 _mem_regions = [(Addr('2GB'), Addr('510GB'))]
864
865 _off_chip_ranges = [
866 # CS1-CS5
867 AddrRange(0x0c000000, 0x1fffffff),
868 # External AXI interface (PCI)
869 AddrRange(0x2f000000, 0x7fffffff),
870 ]
871
872 # Platform control device (off-chip)
873 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
874 idreg=0x02250000, pio_addr=0x1c010000)
875 mcc = VExpressMCC()
876 dcc = CoreTile2A15DCC()
877
878 ### On-chip devices ###
879 gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000,
880 it_lines=512)
881 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
882 gicv2m = Gicv2m()
883 gicv2m.frames = [
884 Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000),
885 ]
886
887 generic_timer = GenericTimer(int_phys=29, int_virt=27)
888
889 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
890 pio_addr=0x2b000000, int_num=95)
891
892 def _on_chip_devices(self):
893 return [
894 self.gic, self.vgic, self.gicv2m,
895 self.hdlcd,
896 self.generic_timer,
897 ]
898
899 ### Off-chip devices ###
| 542# Reference for memory map and interrupt number
543# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
544# Chapter 4: Programmer's Reference
545class RealViewPBX(RealView):
546 uart = Pl011(pio_addr=0x10009000, int_num=44)
547 realview_io = RealViewCtrl(pio_addr=0x10000000)
548 mcc = VExpressMCC()
549 dcc = CoreTile2A15DCC()
550 gic = Pl390()
551 pci_host = GenericPciHost(
552 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
553 pci_pio_base=0)
554 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
555 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
556 global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200)
557 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
558 pio_addr=0x1f000600)
559 clcd = Pl111(pio_addr=0x10020000, int_num=55)
560 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
561 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
562 a9scu = A9SCU(pio_addr=0x1f000000)
563 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
564 io_shift = 1, ctrl_offset = 2, Command = 0x1,
565 BAR0 = 0x18000000, BAR0Size = '16B',
566 BAR1 = 0x18000100, BAR1Size = '1B',
567 BAR0LegacyIO = True, BAR1LegacyIO = True)
568
569
570 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
571 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
572 fake_mem=True)
573 dmac_fake = AmbaFake(pio_addr=0x10030000)
574 uart1_fake = AmbaFake(pio_addr=0x1000a000)
575 uart2_fake = AmbaFake(pio_addr=0x1000b000)
576 uart3_fake = AmbaFake(pio_addr=0x1000c000)
577 smc_fake = AmbaFake(pio_addr=0x100e1000)
578 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
579 watchdog_fake = AmbaFake(pio_addr=0x10010000)
580 gpio0_fake = AmbaFake(pio_addr=0x10013000)
581 gpio1_fake = AmbaFake(pio_addr=0x10014000)
582 gpio2_fake = AmbaFake(pio_addr=0x10015000)
583 ssp_fake = AmbaFake(pio_addr=0x1000d000)
584 sci_fake = AmbaFake(pio_addr=0x1000e000)
585 aaci_fake = AmbaFake(pio_addr=0x10004000)
586 mmc_fake = AmbaFake(pio_addr=0x10005000)
587 rtc = PL031(pio_addr=0x10017000, int_num=42)
588 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
589
590
591 # Attach I/O devices that are on chip and also set the appropriate
592 # ranges for the bridge
593 def attachOnChipIO(self, bus, bridge):
594 self.gic.pio = bus.master
595 self.l2x0_fake.pio = bus.master
596 self.a9scu.pio = bus.master
597 self.global_timer.pio = bus.master
598 self.local_cpu_timer.pio = bus.master
599 # Bridge ranges based on excluding what is part of on-chip I/O
600 # (gic, l2x0, a9scu, local_cpu_timer)
601 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
602 self.a9scu.pio_addr - 1),
603 AddrRange(self.flash_fake.pio_addr,
604 self.flash_fake.pio_addr + \
605 self.flash_fake.pio_size - 1)]
606
607 # Set the clock domain for IO objects that are considered
608 # to be "close" to the cores.
609 def onChipIOClkDomain(self, clkdomain):
610 self.gic.clk_domain = clkdomain
611 self.l2x0_fake.clk_domain = clkdomain
612 self.a9scu.clkdomain = clkdomain
613 self.local_cpu_timer.clk_domain = clkdomain
614
615 # Attach I/O devices to specified bus object. Can't do this
616 # earlier, since the bus object itself is typically defined at the
617 # System level.
618 def attachIO(self, bus):
619 self.uart.pio = bus.master
620 self.realview_io.pio = bus.master
621 self.pci_host.pio = bus.master
622 self.timer0.pio = bus.master
623 self.timer1.pio = bus.master
624 self.clcd.pio = bus.master
625 self.clcd.dma = bus.slave
626 self.kmi0.pio = bus.master
627 self.kmi1.pio = bus.master
628 self.cf_ctrl.pio = bus.master
629 self.cf_ctrl.dma = bus.slave
630 self.dmac_fake.pio = bus.master
631 self.uart1_fake.pio = bus.master
632 self.uart2_fake.pio = bus.master
633 self.uart3_fake.pio = bus.master
634 self.smc_fake.pio = bus.master
635 self.sp810_fake.pio = bus.master
636 self.watchdog_fake.pio = bus.master
637 self.gpio0_fake.pio = bus.master
638 self.gpio1_fake.pio = bus.master
639 self.gpio2_fake.pio = bus.master
640 self.ssp_fake.pio = bus.master
641 self.sci_fake.pio = bus.master
642 self.aaci_fake.pio = bus.master
643 self.mmc_fake.pio = bus.master
644 self.rtc.pio = bus.master
645 self.flash_fake.pio = bus.master
646 self.energy_ctrl.pio = bus.master
647
648 # Set the clock domain for IO objects that are considered
649 # to be "far" away from the cores.
650 def offChipIOClkDomain(self, clkdomain):
651 self.uart.clk_domain = clkdomain
652 self.realview_io.clk_domain = clkdomain
653 self.timer0.clk_domain = clkdomain
654 self.timer1.clk_domain = clkdomain
655 self.clcd.clk_domain = clkdomain
656 self.kmi0.clk_domain = clkdomain
657 self.kmi1.clk_domain = clkdomain
658 self.cf_ctrl.clk_domain = clkdomain
659 self.dmac_fake.clk_domain = clkdomain
660 self.uart1_fake.clk_domain = clkdomain
661 self.uart2_fake.clk_domain = clkdomain
662 self.uart3_fake.clk_domain = clkdomain
663 self.smc_fake.clk_domain = clkdomain
664 self.sp810_fake.clk_domain = clkdomain
665 self.watchdog_fake.clk_domain = clkdomain
666 self.gpio0_fake.clk_domain = clkdomain
667 self.gpio1_fake.clk_domain = clkdomain
668 self.gpio2_fake.clk_domain = clkdomain
669 self.ssp_fake.clk_domain = clkdomain
670 self.sci_fake.clk_domain = clkdomain
671 self.aaci_fake.clk_domain = clkdomain
672 self.mmc_fake.clk_domain = clkdomain
673 self.rtc.clk_domain = clkdomain
674 self.flash_fake.clk_domain = clkdomain
675 self.energy_ctrl.clk_domain = clkdomain
676
677# Reference for memory map and interrupt number
678# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
679# Chapter 4: Programmer's Reference
680class RealViewEB(RealView):
681 uart = Pl011(pio_addr=0x10009000, int_num=44)
682 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
683 mcc = VExpressMCC()
684 dcc = CoreTile2A15DCC()
685 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
686 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
687 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
688 clcd = Pl111(pio_addr=0x10020000, int_num=23)
689 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
690 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
691
692 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
693 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
694 fake_mem=True)
695 dmac_fake = AmbaFake(pio_addr=0x10030000)
696 uart1_fake = AmbaFake(pio_addr=0x1000a000)
697 uart2_fake = AmbaFake(pio_addr=0x1000b000)
698 uart3_fake = AmbaFake(pio_addr=0x1000c000)
699 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
700 smc_fake = AmbaFake(pio_addr=0x100e1000)
701 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
702 watchdog_fake = AmbaFake(pio_addr=0x10010000)
703 gpio0_fake = AmbaFake(pio_addr=0x10013000)
704 gpio1_fake = AmbaFake(pio_addr=0x10014000)
705 gpio2_fake = AmbaFake(pio_addr=0x10015000)
706 ssp_fake = AmbaFake(pio_addr=0x1000d000)
707 sci_fake = AmbaFake(pio_addr=0x1000e000)
708 aaci_fake = AmbaFake(pio_addr=0x10004000)
709 mmc_fake = AmbaFake(pio_addr=0x10005000)
710 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
711 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
712
713 # Attach I/O devices that are on chip and also set the appropriate
714 # ranges for the bridge
715 def attachOnChipIO(self, bus, bridge):
716 self.gic.pio = bus.master
717 self.l2x0_fake.pio = bus.master
718 # Bridge ranges based on excluding what is part of on-chip I/O
719 # (gic, l2x0)
720 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
721 self.gic.cpu_addr - 1),
722 AddrRange(self.flash_fake.pio_addr, Addr.max)]
723
724 # Set the clock domain for IO objects that are considered
725 # to be "close" to the cores.
726 def onChipIOClkDomain(self, clkdomain):
727 self.gic.clk_domain = clkdomain
728 self.l2x0_fake.clk_domain = clkdomain
729
730 # Attach I/O devices to specified bus object. Can't do this
731 # earlier, since the bus object itself is typically defined at the
732 # System level.
733 def attachIO(self, bus):
734 self.uart.pio = bus.master
735 self.realview_io.pio = bus.master
736 self.pci_host.pio = bus.master
737 self.timer0.pio = bus.master
738 self.timer1.pio = bus.master
739 self.clcd.pio = bus.master
740 self.clcd.dma = bus.slave
741 self.kmi0.pio = bus.master
742 self.kmi1.pio = bus.master
743 self.dmac_fake.pio = bus.master
744 self.uart1_fake.pio = bus.master
745 self.uart2_fake.pio = bus.master
746 self.uart3_fake.pio = bus.master
747 self.smc_fake.pio = bus.master
748 self.sp810_fake.pio = bus.master
749 self.watchdog_fake.pio = bus.master
750 self.gpio0_fake.pio = bus.master
751 self.gpio1_fake.pio = bus.master
752 self.gpio2_fake.pio = bus.master
753 self.ssp_fake.pio = bus.master
754 self.sci_fake.pio = bus.master
755 self.aaci_fake.pio = bus.master
756 self.mmc_fake.pio = bus.master
757 self.rtc_fake.pio = bus.master
758 self.flash_fake.pio = bus.master
759 self.smcreg_fake.pio = bus.master
760 self.energy_ctrl.pio = bus.master
761
762 # Set the clock domain for IO objects that are considered
763 # to be "far" away from the cores.
764 def offChipIOClkDomain(self, clkdomain):
765 self.uart.clk_domain = clkdomain
766 self.realview_io.clk_domain = clkdomain
767 self.timer0.clk_domain = clkdomain
768 self.timer1.clk_domain = clkdomain
769 self.clcd.clk_domain = clkdomain
770 self.kmi0.clk_domain = clkdomain
771 self.kmi1.clk_domain = clkdomain
772 self.dmac_fake.clk_domain = clkdomain
773 self.uart1_fake.clk_domain = clkdomain
774 self.uart2_fake.clk_domain = clkdomain
775 self.uart3_fake.clk_domain = clkdomain
776 self.smc_fake.clk_domain = clkdomain
777 self.sp810_fake.clk_domain = clkdomain
778 self.watchdog_fake.clk_domain = clkdomain
779 self.gpio0_fake.clk_domain = clkdomain
780 self.gpio1_fake.clk_domain = clkdomain
781 self.gpio2_fake.clk_domain = clkdomain
782 self.ssp_fake.clk_domain = clkdomain
783 self.sci_fake.clk_domain = clkdomain
784 self.aaci_fake.clk_domain = clkdomain
785 self.mmc_fake.clk_domain = clkdomain
786 self.rtc.clk_domain = clkdomain
787 self.flash_fake.clk_domain = clkdomain
788 self.smcreg_fake.clk_domain = clkdomain
789 self.energy_ctrl.clk_domain = clkdomain
790
791class VExpress_EMM(RealView):
792 _mem_regions = [(Addr('2GB'), Addr('2GB'))]
793
794 # Ranges based on excluding what is part of on-chip I/O (gic,
795 # a9scu)
796 _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'),
797 AddrRange(0x30000000, size='256MB'),
798 AddrRange(0x40000000, size='512MB'),
799 AddrRange(0x18000000, size='64MB'),
800 AddrRange(0x1C000000, size='64MB')]
801
802 # Platform control device (off-chip)
803 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
804 idreg=0x02250000, pio_addr=0x1C010000)
805
806 mcc = VExpressMCC()
807 dcc = CoreTile2A15DCC()
808
809 ### On-chip devices ###
810 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
811 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
812
813 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
814 pio_addr=0x2C080000)
815
816 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
817 pio_addr=0x2b000000, int_num=117,
818 workaround_swap_rb=True)
819
820 def _on_chip_devices(self):
821 devices = [
822 self.gic, self.vgic,
823 self.local_cpu_timer
824 ]
825 if hasattr(self, "gicv2m"):
826 devices.append(self.gicv2m)
827 devices.append(self.hdlcd)
828 return devices
829
830 ### Off-chip devices ###
831 uart = Pl011(pio_addr=0x1c090000, int_num=37)
832 pci_host = GenericPciHost(
833 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
834 pci_pio_base=0)
835
836 generic_timer = GenericTimer(int_phys=29, int_virt=27)
837 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
838 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
839 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
840 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
841 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
842 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
843 io_shift = 2, ctrl_offset = 2, Command = 0x1,
844 BAR0 = 0x1C1A0000, BAR0Size = '256B',
845 BAR1 = 0x1C1A0100, BAR1Size = '4096B',
846 BAR0LegacyIO = True, BAR1LegacyIO = True)
847
848 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
849 conf_table_reported = False)
850 rtc = PL031(pio_addr=0x1C170000, int_num=36)
851
852 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
853 uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
854 uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
855 uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
856 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
857 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
858 aaci_fake = AmbaFake(pio_addr=0x1C040000)
859 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
860 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
861 mmc_fake = AmbaFake(pio_addr=0x1c050000)
862 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000)
863
864 def _off_chip_devices(self):
865 devices = [
866 self.uart,
867 self.realview_io,
868 self.pci_host,
869 self.timer0,
870 self.timer1,
871 self.clcd,
872 self.kmi0,
873 self.kmi1,
874 self.cf_ctrl,
875 self.rtc,
876 self.vram,
877 self.l2x0_fake,
878 self.uart1_fake,
879 self.uart2_fake,
880 self.uart3_fake,
881 self.sp810_fake,
882 self.watchdog_fake,
883 self.aaci_fake,
884 self.lan_fake,
885 self.usb_fake,
886 self.mmc_fake,
887 self.energy_ctrl,
888 ]
889 # Try to attach the I/O if it exists
890 if hasattr(self, "ide"):
891 devices.append(self.ide)
892 if hasattr(self, "ethernet"):
893 devices.append(self.ethernet)
894 return devices
895
896 # Attach any PCI devices that are supported
897 def attachPciDevices(self):
898 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
899 InterruptLine=1, InterruptPin=1)
900 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
901 InterruptLine=2, InterruptPin=2)
902
903 def enableMSIX(self):
904 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
905 self.gicv2m = Gicv2m()
906 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
907
908 def setupBootLoader(self, mem_bus, cur_sys, loc):
909 self.nvmem = SimpleMemory(range = AddrRange('64MB'),
910 conf_table_reported = False)
911 self.nvmem.port = mem_bus.master
912 if not cur_sys.boot_loader:
913 cur_sys.boot_loader = loc('boot_emm.arm')
914 cur_sys.atags_addr = 0x8000000
915 cur_sys.load_offset = 0x80000000
916
917class VExpress_EMM64(VExpress_EMM):
918 # Three memory regions are specified totalling 512GB
919 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
920 (Addr('512GB'), Addr('480GB'))]
921 pci_host = GenericPciHost(
922 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
923 pci_pio_base=0x2f000000)
924
925 def setupBootLoader(self, mem_bus, cur_sys, loc):
926 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
927 conf_table_reported=False)
928 self.nvmem.port = mem_bus.master
929 if not cur_sys.boot_loader:
930 cur_sys.boot_loader = loc('boot_emm.arm64')
931 cur_sys.atags_addr = 0x8000000
932 cur_sys.load_offset = 0x80000000
933
934
935class VExpress_GEM5_V1(RealView):
936 """
937The VExpress gem5 memory map is loosely based on a modified
938Versatile Express RS1 memory map.
939
940The gem5 platform has been designed to implement a subset of the
941original Versatile Express RS1 memory map. Off-chip peripherals should,
942when possible, adhere to the Versatile Express memory map. Non-PCI
943off-chip devices that are gem5-specific should live in the CS5 memory
944space to avoid conflicts with existing devices that we might want to
945model in the future. Such devices should normally have interrupts in
946the gem5-specific SPI range.
947
948On-chip peripherals are loosely modeled after the ARM CoreTile Express
949A15x2 A7x3 memory and interrupt map. In particular, the GIC and
950Generic Timer have the same interrupt lines and base addresses. Other
951on-chip devices are gem5 specific.
952
953Unlike the original Versatile Express RS2 extended platform, gem5 implements a
954large contigious DRAM space, without aliases or holes, starting at the
9552GiB boundary. This means that PCI memory is limited to 1GiB.
956
957Memory map:
958 0x00000000-0x03ffffff: Boot memory (CS0)
959 0x04000000-0x07ffffff: Reserved
960 0x08000000-0x0bffffff: Reserved (CS0 alias)
961 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4)
962 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
963 0x10000000-0x1000ffff: gem5 energy controller
964 0x10010000-0x1001ffff: gem5 pseudo-ops
965
966 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1)
967 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2)
968 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3):
969 0x1c010000-0x1c01ffff: realview_io (VE system control regs.)
970 0x1c060000-0x1c06ffff: KMI0 (keyboard)
971 0x1c070000-0x1c07ffff: KMI1 (mouse)
972 0x1c090000-0x1c09ffff: UART0
973 0x1c0a0000-0x1c0affff: UART1 (reserved)
974 0x1c0b0000-0x1c0bffff: UART2 (reserved)
975 0x1c0c0000-0x1c0cffff: UART3 (reserved)
976 0x1c170000-0x1c17ffff: RTC
977
978 0x20000000-0x3fffffff: On-chip peripherals:
979 0x2b000000-0x2b00ffff: HDLCD
980
981 0x2c001000-0x2c001fff: GIC (distributor)
982 0x2c002000-0x2c0020ff: GIC (CPU interface)
983 0x2c004000-0x2c005fff: vGIC (HV)
984 0x2c006000-0x2c007fff: vGIC (VCPU)
985 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0
986
987 0x2d000000-0x2d00ffff: GPU (reserved)
988
989 0x2f000000-0x2fffffff: PCI IO space
990 0x30000000-0x3fffffff: PCI config space
991
992 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory
993
994 0x80000000-X: DRAM
995
996Interrupts:
997 0- 15: Software generated interrupts (SGIs)
998 16- 31: On-chip private peripherals (PPIs)
999 25 : vgic
1000 26 : generic_timer (hyp)
1001 27 : generic_timer (virt)
1002 28 : Reserved (Legacy FIQ)
1003 29 : generic_timer (phys, sec)
1004 30 : generic_timer (phys, non-sec)
1005 31 : Reserved (Legacy IRQ)
1006 32- 95: Mother board peripherals (SPIs)
1007 32 : Reserved (SP805)
1008 33 : Reserved (IOFPGA SW int)
1009 34-35: Reserved (SP804)
1010 36 : RTC
1011 37-40: uart0-uart3
1012 41-42: Reserved (PL180)
1013 43 : Reserved (AACI)
1014 44-45: kmi0-kmi1
1015 46 : Reserved (CLCD)
1016 47 : Reserved (Ethernet)
1017 48 : Reserved (USB)
1018 95-255: On-chip interrupt sources (we use these for
1019 gem5-specific devices, SPIs)
1020 95 : HDLCD
1021 96- 98: GPU (reserved)
1022 100-103: PCI
1023 256-319: MSI frame 0 (gem5-specific, SPIs)
1024 320-511: Unused
1025
1026 """
1027
1028 # Everything above 2GiB is memory
1029 _mem_regions = [(Addr('2GB'), Addr('510GB'))]
1030
1031 _off_chip_ranges = [
1032 # CS1-CS5
1033 AddrRange(0x0c000000, 0x1fffffff),
1034 # External AXI interface (PCI)
1035 AddrRange(0x2f000000, 0x7fffffff),
1036 ]
1037
1038 # Platform control device (off-chip)
1039 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
1040 idreg=0x02250000, pio_addr=0x1c010000)
1041 mcc = VExpressMCC()
1042 dcc = CoreTile2A15DCC()
1043
1044 ### On-chip devices ###
1045 gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000,
1046 it_lines=512)
1047 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
1048 gicv2m = Gicv2m()
1049 gicv2m.frames = [
1050 Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000),
1051 ]
1052
1053 generic_timer = GenericTimer(int_phys=29, int_virt=27)
1054
1055 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
1056 pio_addr=0x2b000000, int_num=95)
1057
1058 def _on_chip_devices(self):
1059 return [
1060 self.gic, self.vgic, self.gicv2m,
1061 self.hdlcd,
1062 self.generic_timer,
1063 ]
1064
1065 ### Off-chip devices ###
|
| 1066 clock24MHz = SrcClockDomain(clock="24MHz",
1067 voltage_domain=VoltageDomain(voltage="3.3V"))
1068
|
900 uart0 = Pl011(pio_addr=0x1c090000, int_num=37)
901
902 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
903 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
904
905 rtc = PL031(pio_addr=0x1c170000, int_num=36)
906
907 ### gem5-specific off-chip devices ###
908 pci_host = GenericArmPciHost(
909 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
910 pci_pio_base=0x2f000000,
911 int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
912
913 energy_ctrl = EnergyCtrl(pio_addr=0x10000000)
914
915
916 def _off_chip_devices(self):
917 return [
918 self.realview_io,
919 self.uart0,
| 1069 uart0 = Pl011(pio_addr=0x1c090000, int_num=37)
1070
1071 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
1072 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
1073
1074 rtc = PL031(pio_addr=0x1c170000, int_num=36)
1075
1076 ### gem5-specific off-chip devices ###
1077 pci_host = GenericArmPciHost(
1078 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
1079 pci_pio_base=0x2f000000,
1080 int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
1081
1082 energy_ctrl = EnergyCtrl(pio_addr=0x10000000)
1083
1084
1085 def _off_chip_devices(self):
1086 return [
1087 self.realview_io,
1088 self.uart0,
|
920 self.kmi0, self.kmi1,
| 1089 self.kmi0,
1090 self.kmi1,
|
921 self.rtc,
922 self.pci_host,
923 self.energy_ctrl,
| 1091 self.rtc,
1092 self.pci_host,
1093 self.energy_ctrl,
|
| 1094 self.clock24MHz,
|
924 ]
925
926 def attachPciDevice(self, device, *args, **kwargs):
927 device.host = self.pci_host
928 self._attach_device(device, *args, **kwargs)
929
930 def setupBootLoader(self, mem_bus, cur_sys, loc):
931 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
932 conf_table_reported=False)
933 self.nvmem.port = mem_bus.master
934 if not cur_sys.boot_loader:
935 cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ]
936 cur_sys.atags_addr = 0x8000000
937 cur_sys.load_offset = 0x80000000
938
939 # Setup m5ops. It's technically not a part of the boot
940 # loader, but this is the only place we can configure the
941 # system.
942 cur_sys.m5ops_base = 0x10010000
| 1095 ]
1096
1097 def attachPciDevice(self, device, *args, **kwargs):
1098 device.host = self.pci_host
1099 self._attach_device(device, *args, **kwargs)
1100
1101 def setupBootLoader(self, mem_bus, cur_sys, loc):
1102 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
1103 conf_table_reported=False)
1104 self.nvmem.port = mem_bus.master
1105 if not cur_sys.boot_loader:
1106 cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ]
1107 cur_sys.atags_addr = 0x8000000
1108 cur_sys.load_offset = 0x80000000
1109
1110 # Setup m5ops. It's technically not a part of the boot
1111 # loader, but this is the only place we can configure the
1112 # system.
1113 cur_sys.m5ops_base = 0x10010000
|
| 1114
1115 def generateDeviceTree(self, state):
1116 # Generate using standard RealView function
1117 dt = list(super(VExpress_GEM5_V1, self).generateDeviceTree(state))
1118 if len(dt) > 1:
1119 raise Exception("System returned too many DT nodes")
1120 node = dt[0]
1121
1122 node.appendCompatible(["arm,vexpress"])
1123 node.append(FdtPropertyStrings("model", ["V2P-CA15"]))
1124 node.append(FdtPropertyWords("arm,hbi", [0x0]))
1125 node.append(FdtPropertyWords("arm,vexpress,site", [0xf]))
1126
1127 yield node
|
| |