1# Copyright (c) 2009-2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42
43from m5.params import *
44from m5.proxy import *
| 1# Copyright (c) 2009-2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42
43from m5.params import *
44from m5.proxy import *
|
| 45from ClockDomain import ClockDomain
46from VoltageDomain import VoltageDomain
|
45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
46from Pci import PciConfigAll
47from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
48from Ide import *
49from Platform import Platform
50from Terminal import Terminal
51from Uart import Uart
52from SimpleMemory import SimpleMemory
53from Gic import *
54from EnergyCtrl import EnergyCtrl
55
56class AmbaPioDevice(BasicPioDevice):
57 type = 'AmbaPioDevice'
58 abstract = True
59 cxx_header = "dev/arm/amba_device.hh"
60 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
61
62class AmbaIntDevice(AmbaPioDevice):
63 type = 'AmbaIntDevice'
64 abstract = True
65 cxx_header = "dev/arm/amba_device.hh"
66 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
67 int_num = Param.UInt32("Interrupt number that connects to GIC")
68 int_delay = Param.Latency("100ns",
69 "Time between action and interrupt generation by device")
70
71class AmbaDmaDevice(DmaDevice):
72 type = 'AmbaDmaDevice'
73 abstract = True
74 cxx_header = "dev/arm/amba_device.hh"
75 pio_addr = Param.Addr("Address for AMBA slave interface")
76 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
77 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
78 int_num = Param.UInt32("Interrupt number that connects to GIC")
79 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
80
81class A9SCU(BasicPioDevice):
82 type = 'A9SCU'
83 cxx_header = "dev/arm/a9scu.hh"
84
85class RealViewCtrl(BasicPioDevice):
86 type = 'RealViewCtrl'
87 cxx_header = "dev/arm/rv_ctrl.hh"
88 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
89 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
90 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
91
| 47from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
48from Pci import PciConfigAll
49from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
50from Ide import *
51from Platform import Platform
52from Terminal import Terminal
53from Uart import Uart
54from SimpleMemory import SimpleMemory
55from Gic import *
56from EnergyCtrl import EnergyCtrl
57
58class AmbaPioDevice(BasicPioDevice):
59 type = 'AmbaPioDevice'
60 abstract = True
61 cxx_header = "dev/arm/amba_device.hh"
62 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
63
64class AmbaIntDevice(AmbaPioDevice):
65 type = 'AmbaIntDevice'
66 abstract = True
67 cxx_header = "dev/arm/amba_device.hh"
68 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
69 int_num = Param.UInt32("Interrupt number that connects to GIC")
70 int_delay = Param.Latency("100ns",
71 "Time between action and interrupt generation by device")
72
73class AmbaDmaDevice(DmaDevice):
74 type = 'AmbaDmaDevice'
75 abstract = True
76 cxx_header = "dev/arm/amba_device.hh"
77 pio_addr = Param.Addr("Address for AMBA slave interface")
78 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
79 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
80 int_num = Param.UInt32("Interrupt number that connects to GIC")
81 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
82
83class A9SCU(BasicPioDevice):
84 type = 'A9SCU'
85 cxx_header = "dev/arm/a9scu.hh"
86
87class RealViewCtrl(BasicPioDevice):
88 type = 'RealViewCtrl'
89 cxx_header = "dev/arm/rv_ctrl.hh"
90 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
91 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
92 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
93
|
| 94class RealViewOsc(ClockDomain):
95 type = 'RealViewOsc'
96 cxx_header = "dev/arm/rv_ctrl.hh"
97
98 parent = Param.RealViewCtrl(Parent.any, "RealView controller")
99
100 # TODO: We currently don't have the notion of a clock source,
101 # which means we have to associate oscillators with a voltage
102 # source.
103 voltage_domain = Param.VoltageDomain(Parent.voltage_domain,
104 "Voltage domain")
105
106 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
107 # the individual core/logic tile reference manuals for details
108 # about the site/position/dcc/device allocation.
109 site = Param.UInt8("Board Site")
110 position = Param.UInt8("Position in device stack")
111 dcc = Param.UInt8("Daughterboard Configuration Controller")
112 device = Param.UInt8("Device ID")
113
114 freq = Param.Clock("Default frequency")
115
116class VExpressCoreTileCtrl(RealViewCtrl):
117 class MotherBoardOsc(RealViewOsc):
118 site, position, dcc = (0, 0, 0)
119
120 class CoreTileOsc(RealViewOsc):
121 site, position, dcc = (1, 0, 0)
122
123 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1)
124 osc_mcc = MotherBoardOsc(device=0, freq="50MHz")
125 osc_clcd = MotherBoardOsc(device=1, freq="23.75MHz")
126 osc_peripheral = MotherBoardOsc(device=2, freq="24MHz")
127 osc_system_bus = MotherBoardOsc(device=4, freq="24MHz")
128
129 # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM).
130 osc_cpu = CoreTileOsc(device=0, freq="60MHz")
131 osc_hsbm = CoreTileOsc(device=4, freq="40MHz")
132 osc_pxl = CoreTileOsc(device=5, freq="23.75MHz")
133 osc_smb = CoreTileOsc(device=6, freq="50MHz")
134 osc_sys = CoreTileOsc(device=7, freq="60MHz")
135 osc_ddr = CoreTileOsc(device=8, freq="40MHz")
136
|
92class VGic(PioDevice):
93 type = 'VGic'
94 cxx_header = "dev/arm/vgic.hh"
95 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
96 platform = Param.Platform(Parent.any, "Platform this device is part of.")
97 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
98 hv_addr = Param.Addr(0, "Address for hv control")
99 pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
100 # The number of list registers is not currently configurable at runtime.
101 ppint = Param.UInt32("HV maintenance interrupt number")
102
103class AmbaFake(AmbaPioDevice):
104 type = 'AmbaFake'
105 cxx_header = "dev/arm/amba_fake.hh"
106 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
107 amba_id = 0;
108
109class Pl011(Uart):
110 type = 'Pl011'
111 cxx_header = "dev/arm/pl011.hh"
112 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
113 int_num = Param.UInt32("Interrupt number that connects to GIC")
114 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
115 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
116
117class Sp804(AmbaPioDevice):
118 type = 'Sp804'
119 cxx_header = "dev/arm/timer_sp804.hh"
120 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
121 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
122 clock0 = Param.Clock('1MHz', "Clock speed of the input")
123 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
124 clock1 = Param.Clock('1MHz', "Clock speed of the input")
125 amba_id = 0x00141804
126
127class CpuLocalTimer(BasicPioDevice):
128 type = 'CpuLocalTimer'
129 cxx_header = "dev/arm/timer_cpulocal.hh"
130 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
131 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
132 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
133
134class GenericTimer(SimObject):
135 type = 'GenericTimer'
136 cxx_header = "dev/arm/generic_timer.hh"
137 system = Param.System(Parent.any, "system")
138 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
139 # @todo: for now only two timers per CPU is supported, which is the
140 # normal behaviour when security extensions are disabled.
141 int_phys = Param.UInt32("Physical timer interrupt number")
142 int_virt = Param.UInt32("Virtual timer interrupt number")
143
144class GenericTimerMem(PioDevice):
145 type = 'GenericTimerMem'
146 cxx_header = "dev/arm/generic_timer.hh"
147 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
148
149 base = Param.Addr(0, "Base address")
150
151 int_phys = Param.UInt32("Interrupt number")
152 int_virt = Param.UInt32("Interrupt number")
153
154class PL031(AmbaIntDevice):
155 type = 'PL031'
156 cxx_header = "dev/arm/rtc_pl031.hh"
157 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
158 amba_id = 0x00341031
159
160class Pl050(AmbaIntDevice):
161 type = 'Pl050'
162 cxx_header = "dev/arm/kmi.hh"
163 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
164 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
165 int_delay = '1us'
166 amba_id = 0x00141050
167
168class Pl111(AmbaDmaDevice):
169 type = 'Pl111'
170 cxx_header = "dev/arm/pl111.hh"
171 pixel_clock = Param.Clock('24MHz', "Pixel clock")
172 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
173 amba_id = 0x00141111
174 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
175
176
177class HDLcd(AmbaDmaDevice):
178 type = 'HDLcd'
179 cxx_header = "dev/arm/hdlcd.hh"
180 # For reference, 1024x768MR-16@60 ~= 56 MHz
181 # 1920x1080MR-16@60 ~= 137 MHz
182 # 3840x2160MR-16@60 ~= 533 MHz
183 # Match against the resolution selected in the Linux DTS/DTB file.
184 pixel_clock = Param.Clock('137MHz', "Clock frequency of the pixel clock "
185 "(i.e. PXLREFCLK / OSCCLK 5")
186 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer "
187 "display")
188 amba_id = 0x00141000
189 workaround_swap_rb = Param.Bool(True, "Workaround incorrect color "
190 "selector order in some kernels")
191 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
192
193class RealView(Platform):
194 type = 'RealView'
195 cxx_header = "dev/arm/realview.hh"
196 system = Param.System(Parent.any, "system")
197 pci_io_base = Param.Addr(0, "Base address of PCI IO Space")
198 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
199 pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access"
200 " be compatible with the pci-generic-host or the legacy host bridge?")
201 _mem_regions = [(Addr(0), Addr('256MB'))]
202
203 def attachPciDevices(self):
204 pass
205
206 def enableMSIX(self):
207 pass
208
209 def onChipIOClkDomain(self, clkdomain):
210 pass
211
212 def offChipIOClkDomain(self, clkdomain):
213 pass
214
215 def setupBootLoader(self, mem_bus, cur_sys, loc):
216 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
217 conf_table_reported = False)
218 self.nvmem.port = mem_bus.master
219 cur_sys.boot_loader = loc('boot.arm')
220 cur_sys.atags_addr = 0x100
221 cur_sys.load_addr_mask = 0xfffffff
222 cur_sys.load_offset = 0
223
224
225# Reference for memory map and interrupt number
226# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
227# Chapter 4: Programmer's Reference
228class RealViewPBX(RealView):
229 uart = Pl011(pio_addr=0x10009000, int_num=44)
| 137class VGic(PioDevice):
138 type = 'VGic'
139 cxx_header = "dev/arm/vgic.hh"
140 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
141 platform = Param.Platform(Parent.any, "Platform this device is part of.")
142 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
143 hv_addr = Param.Addr(0, "Address for hv control")
144 pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
145 # The number of list registers is not currently configurable at runtime.
146 ppint = Param.UInt32("HV maintenance interrupt number")
147
148class AmbaFake(AmbaPioDevice):
149 type = 'AmbaFake'
150 cxx_header = "dev/arm/amba_fake.hh"
151 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
152 amba_id = 0;
153
154class Pl011(Uart):
155 type = 'Pl011'
156 cxx_header = "dev/arm/pl011.hh"
157 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
158 int_num = Param.UInt32("Interrupt number that connects to GIC")
159 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
160 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
161
162class Sp804(AmbaPioDevice):
163 type = 'Sp804'
164 cxx_header = "dev/arm/timer_sp804.hh"
165 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
166 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
167 clock0 = Param.Clock('1MHz', "Clock speed of the input")
168 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
169 clock1 = Param.Clock('1MHz', "Clock speed of the input")
170 amba_id = 0x00141804
171
172class CpuLocalTimer(BasicPioDevice):
173 type = 'CpuLocalTimer'
174 cxx_header = "dev/arm/timer_cpulocal.hh"
175 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
176 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
177 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
178
179class GenericTimer(SimObject):
180 type = 'GenericTimer'
181 cxx_header = "dev/arm/generic_timer.hh"
182 system = Param.System(Parent.any, "system")
183 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
184 # @todo: for now only two timers per CPU is supported, which is the
185 # normal behaviour when security extensions are disabled.
186 int_phys = Param.UInt32("Physical timer interrupt number")
187 int_virt = Param.UInt32("Virtual timer interrupt number")
188
189class GenericTimerMem(PioDevice):
190 type = 'GenericTimerMem'
191 cxx_header = "dev/arm/generic_timer.hh"
192 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
193
194 base = Param.Addr(0, "Base address")
195
196 int_phys = Param.UInt32("Interrupt number")
197 int_virt = Param.UInt32("Interrupt number")
198
199class PL031(AmbaIntDevice):
200 type = 'PL031'
201 cxx_header = "dev/arm/rtc_pl031.hh"
202 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
203 amba_id = 0x00341031
204
205class Pl050(AmbaIntDevice):
206 type = 'Pl050'
207 cxx_header = "dev/arm/kmi.hh"
208 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
209 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
210 int_delay = '1us'
211 amba_id = 0x00141050
212
213class Pl111(AmbaDmaDevice):
214 type = 'Pl111'
215 cxx_header = "dev/arm/pl111.hh"
216 pixel_clock = Param.Clock('24MHz', "Pixel clock")
217 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
218 amba_id = 0x00141111
219 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
220
221
222class HDLcd(AmbaDmaDevice):
223 type = 'HDLcd'
224 cxx_header = "dev/arm/hdlcd.hh"
225 # For reference, 1024x768MR-16@60 ~= 56 MHz
226 # 1920x1080MR-16@60 ~= 137 MHz
227 # 3840x2160MR-16@60 ~= 533 MHz
228 # Match against the resolution selected in the Linux DTS/DTB file.
229 pixel_clock = Param.Clock('137MHz', "Clock frequency of the pixel clock "
230 "(i.e. PXLREFCLK / OSCCLK 5")
231 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer "
232 "display")
233 amba_id = 0x00141000
234 workaround_swap_rb = Param.Bool(True, "Workaround incorrect color "
235 "selector order in some kernels")
236 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
237
238class RealView(Platform):
239 type = 'RealView'
240 cxx_header = "dev/arm/realview.hh"
241 system = Param.System(Parent.any, "system")
242 pci_io_base = Param.Addr(0, "Base address of PCI IO Space")
243 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
244 pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access"
245 " be compatible with the pci-generic-host or the legacy host bridge?")
246 _mem_regions = [(Addr(0), Addr('256MB'))]
247
248 def attachPciDevices(self):
249 pass
250
251 def enableMSIX(self):
252 pass
253
254 def onChipIOClkDomain(self, clkdomain):
255 pass
256
257 def offChipIOClkDomain(self, clkdomain):
258 pass
259
260 def setupBootLoader(self, mem_bus, cur_sys, loc):
261 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
262 conf_table_reported = False)
263 self.nvmem.port = mem_bus.master
264 cur_sys.boot_loader = loc('boot.arm')
265 cur_sys.atags_addr = 0x100
266 cur_sys.load_addr_mask = 0xfffffff
267 cur_sys.load_offset = 0
268
269
270# Reference for memory map and interrupt number
271# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
272# Chapter 4: Programmer's Reference
273class RealViewPBX(RealView):
274 uart = Pl011(pio_addr=0x10009000, int_num=44)
|
230 realview_io = RealViewCtrl(pio_addr=0x10000000)
| 275 realview_io = VExpressCoreTileCtrl(pio_addr=0x10000000)
|
231 gic = Pl390()
232 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
233 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
234 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600)
235 clcd = Pl111(pio_addr=0x10020000, int_num=55)
236 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
237 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
238 a9scu = A9SCU(pio_addr=0x1f000000)
239 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
240 io_shift = 1, ctrl_offset = 2, Command = 0x1,
241 BAR0 = 0x18000000, BAR0Size = '16B',
242 BAR1 = 0x18000100, BAR1Size = '1B',
243 BAR0LegacyIO = True, BAR1LegacyIO = True)
244
245
246 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
247 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
248 fake_mem=True)
249 dmac_fake = AmbaFake(pio_addr=0x10030000)
250 uart1_fake = AmbaFake(pio_addr=0x1000a000)
251 uart2_fake = AmbaFake(pio_addr=0x1000b000)
252 uart3_fake = AmbaFake(pio_addr=0x1000c000)
253 smc_fake = AmbaFake(pio_addr=0x100e1000)
254 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
255 watchdog_fake = AmbaFake(pio_addr=0x10010000)
256 gpio0_fake = AmbaFake(pio_addr=0x10013000)
257 gpio1_fake = AmbaFake(pio_addr=0x10014000)
258 gpio2_fake = AmbaFake(pio_addr=0x10015000)
259 ssp_fake = AmbaFake(pio_addr=0x1000d000)
260 sci_fake = AmbaFake(pio_addr=0x1000e000)
261 aaci_fake = AmbaFake(pio_addr=0x10004000)
262 mmc_fake = AmbaFake(pio_addr=0x10005000)
263 rtc = PL031(pio_addr=0x10017000, int_num=42)
264 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
265
266
267 # Attach I/O devices that are on chip and also set the appropriate
268 # ranges for the bridge
269 def attachOnChipIO(self, bus, bridge):
270 self.gic.pio = bus.master
271 self.l2x0_fake.pio = bus.master
272 self.a9scu.pio = bus.master
273 self.local_cpu_timer.pio = bus.master
274 # Bridge ranges based on excluding what is part of on-chip I/O
275 # (gic, l2x0, a9scu, local_cpu_timer)
276 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
277 self.a9scu.pio_addr - 1),
278 AddrRange(self.flash_fake.pio_addr,
279 self.flash_fake.pio_addr + \
280 self.flash_fake.pio_size - 1)]
281
282 # Set the clock domain for IO objects that are considered
283 # to be "close" to the cores.
284 def onChipIOClkDomain(self, clkdomain):
285 self.gic.clk_domain = clkdomain
286 self.l2x0_fake.clk_domain = clkdomain
287 self.a9scu.clkdomain = clkdomain
288 self.local_cpu_timer.clk_domain = clkdomain
289
290 # Attach I/O devices to specified bus object. Can't do this
291 # earlier, since the bus object itself is typically defined at the
292 # System level.
293 def attachIO(self, bus):
294 self.uart.pio = bus.master
295 self.realview_io.pio = bus.master
296 self.timer0.pio = bus.master
297 self.timer1.pio = bus.master
298 self.clcd.pio = bus.master
299 self.clcd.dma = bus.slave
300 self.kmi0.pio = bus.master
301 self.kmi1.pio = bus.master
302 self.cf_ctrl.pio = bus.master
303 self.cf_ctrl.config = bus.master
304 self.cf_ctrl.dma = bus.slave
305 self.dmac_fake.pio = bus.master
306 self.uart1_fake.pio = bus.master
307 self.uart2_fake.pio = bus.master
308 self.uart3_fake.pio = bus.master
309 self.smc_fake.pio = bus.master
310 self.sp810_fake.pio = bus.master
311 self.watchdog_fake.pio = bus.master
312 self.gpio0_fake.pio = bus.master
313 self.gpio1_fake.pio = bus.master
314 self.gpio2_fake.pio = bus.master
315 self.ssp_fake.pio = bus.master
316 self.sci_fake.pio = bus.master
317 self.aaci_fake.pio = bus.master
318 self.mmc_fake.pio = bus.master
319 self.rtc.pio = bus.master
320 self.flash_fake.pio = bus.master
321 self.energy_ctrl.pio = bus.master
322
323 # Set the clock domain for IO objects that are considered
324 # to be "far" away from the cores.
325 def offChipIOClkDomain(self, clkdomain):
326 self.uart.clk_domain = clkdomain
327 self.realview_io.clk_domain = clkdomain
328 self.timer0.clk_domain = clkdomain
329 self.timer1.clk_domain = clkdomain
330 self.clcd.clk_domain = clkdomain
331 self.kmi0.clk_domain = clkdomain
332 self.kmi1.clk_domain = clkdomain
333 self.cf_ctrl.clk_domain = clkdomain
334 self.dmac_fake.clk_domain = clkdomain
335 self.uart1_fake.clk_domain = clkdomain
336 self.uart2_fake.clk_domain = clkdomain
337 self.uart3_fake.clk_domain = clkdomain
338 self.smc_fake.clk_domain = clkdomain
339 self.sp810_fake.clk_domain = clkdomain
340 self.watchdog_fake.clk_domain = clkdomain
341 self.gpio0_fake.clk_domain = clkdomain
342 self.gpio1_fake.clk_domain = clkdomain
343 self.gpio2_fake.clk_domain = clkdomain
344 self.ssp_fake.clk_domain = clkdomain
345 self.sci_fake.clk_domain = clkdomain
346 self.aaci_fake.clk_domain = clkdomain
347 self.mmc_fake.clk_domain = clkdomain
348 self.rtc.clk_domain = clkdomain
349 self.flash_fake.clk_domain = clkdomain
350 self.energy_ctrl.clk_domain = clkdomain
351
352# Reference for memory map and interrupt number
353# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
354# Chapter 4: Programmer's Reference
355class RealViewEB(RealView):
356 uart = Pl011(pio_addr=0x10009000, int_num=44)
| 276 gic = Pl390()
277 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
278 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
279 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600)
280 clcd = Pl111(pio_addr=0x10020000, int_num=55)
281 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
282 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
283 a9scu = A9SCU(pio_addr=0x1f000000)
284 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
285 io_shift = 1, ctrl_offset = 2, Command = 0x1,
286 BAR0 = 0x18000000, BAR0Size = '16B',
287 BAR1 = 0x18000100, BAR1Size = '1B',
288 BAR0LegacyIO = True, BAR1LegacyIO = True)
289
290
291 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
292 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
293 fake_mem=True)
294 dmac_fake = AmbaFake(pio_addr=0x10030000)
295 uart1_fake = AmbaFake(pio_addr=0x1000a000)
296 uart2_fake = AmbaFake(pio_addr=0x1000b000)
297 uart3_fake = AmbaFake(pio_addr=0x1000c000)
298 smc_fake = AmbaFake(pio_addr=0x100e1000)
299 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
300 watchdog_fake = AmbaFake(pio_addr=0x10010000)
301 gpio0_fake = AmbaFake(pio_addr=0x10013000)
302 gpio1_fake = AmbaFake(pio_addr=0x10014000)
303 gpio2_fake = AmbaFake(pio_addr=0x10015000)
304 ssp_fake = AmbaFake(pio_addr=0x1000d000)
305 sci_fake = AmbaFake(pio_addr=0x1000e000)
306 aaci_fake = AmbaFake(pio_addr=0x10004000)
307 mmc_fake = AmbaFake(pio_addr=0x10005000)
308 rtc = PL031(pio_addr=0x10017000, int_num=42)
309 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
310
311
312 # Attach I/O devices that are on chip and also set the appropriate
313 # ranges for the bridge
314 def attachOnChipIO(self, bus, bridge):
315 self.gic.pio = bus.master
316 self.l2x0_fake.pio = bus.master
317 self.a9scu.pio = bus.master
318 self.local_cpu_timer.pio = bus.master
319 # Bridge ranges based on excluding what is part of on-chip I/O
320 # (gic, l2x0, a9scu, local_cpu_timer)
321 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
322 self.a9scu.pio_addr - 1),
323 AddrRange(self.flash_fake.pio_addr,
324 self.flash_fake.pio_addr + \
325 self.flash_fake.pio_size - 1)]
326
327 # Set the clock domain for IO objects that are considered
328 # to be "close" to the cores.
329 def onChipIOClkDomain(self, clkdomain):
330 self.gic.clk_domain = clkdomain
331 self.l2x0_fake.clk_domain = clkdomain
332 self.a9scu.clkdomain = clkdomain
333 self.local_cpu_timer.clk_domain = clkdomain
334
335 # Attach I/O devices to specified bus object. Can't do this
336 # earlier, since the bus object itself is typically defined at the
337 # System level.
338 def attachIO(self, bus):
339 self.uart.pio = bus.master
340 self.realview_io.pio = bus.master
341 self.timer0.pio = bus.master
342 self.timer1.pio = bus.master
343 self.clcd.pio = bus.master
344 self.clcd.dma = bus.slave
345 self.kmi0.pio = bus.master
346 self.kmi1.pio = bus.master
347 self.cf_ctrl.pio = bus.master
348 self.cf_ctrl.config = bus.master
349 self.cf_ctrl.dma = bus.slave
350 self.dmac_fake.pio = bus.master
351 self.uart1_fake.pio = bus.master
352 self.uart2_fake.pio = bus.master
353 self.uart3_fake.pio = bus.master
354 self.smc_fake.pio = bus.master
355 self.sp810_fake.pio = bus.master
356 self.watchdog_fake.pio = bus.master
357 self.gpio0_fake.pio = bus.master
358 self.gpio1_fake.pio = bus.master
359 self.gpio2_fake.pio = bus.master
360 self.ssp_fake.pio = bus.master
361 self.sci_fake.pio = bus.master
362 self.aaci_fake.pio = bus.master
363 self.mmc_fake.pio = bus.master
364 self.rtc.pio = bus.master
365 self.flash_fake.pio = bus.master
366 self.energy_ctrl.pio = bus.master
367
368 # Set the clock domain for IO objects that are considered
369 # to be "far" away from the cores.
370 def offChipIOClkDomain(self, clkdomain):
371 self.uart.clk_domain = clkdomain
372 self.realview_io.clk_domain = clkdomain
373 self.timer0.clk_domain = clkdomain
374 self.timer1.clk_domain = clkdomain
375 self.clcd.clk_domain = clkdomain
376 self.kmi0.clk_domain = clkdomain
377 self.kmi1.clk_domain = clkdomain
378 self.cf_ctrl.clk_domain = clkdomain
379 self.dmac_fake.clk_domain = clkdomain
380 self.uart1_fake.clk_domain = clkdomain
381 self.uart2_fake.clk_domain = clkdomain
382 self.uart3_fake.clk_domain = clkdomain
383 self.smc_fake.clk_domain = clkdomain
384 self.sp810_fake.clk_domain = clkdomain
385 self.watchdog_fake.clk_domain = clkdomain
386 self.gpio0_fake.clk_domain = clkdomain
387 self.gpio1_fake.clk_domain = clkdomain
388 self.gpio2_fake.clk_domain = clkdomain
389 self.ssp_fake.clk_domain = clkdomain
390 self.sci_fake.clk_domain = clkdomain
391 self.aaci_fake.clk_domain = clkdomain
392 self.mmc_fake.clk_domain = clkdomain
393 self.rtc.clk_domain = clkdomain
394 self.flash_fake.clk_domain = clkdomain
395 self.energy_ctrl.clk_domain = clkdomain
396
397# Reference for memory map and interrupt number
398# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
399# Chapter 4: Programmer's Reference
400class RealViewEB(RealView):
401 uart = Pl011(pio_addr=0x10009000, int_num=44)
|
357 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
| 402 realview_io = VExpressCoreTileCtrl(pio_addr=0x10000000, idreg=0x01400500)
|
358 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
359 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
360 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
361 clcd = Pl111(pio_addr=0x10020000, int_num=23)
362 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
363 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
364
365 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
366 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
367 fake_mem=True)
368 dmac_fake = AmbaFake(pio_addr=0x10030000)
369 uart1_fake = AmbaFake(pio_addr=0x1000a000)
370 uart2_fake = AmbaFake(pio_addr=0x1000b000)
371 uart3_fake = AmbaFake(pio_addr=0x1000c000)
372 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
373 smc_fake = AmbaFake(pio_addr=0x100e1000)
374 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
375 watchdog_fake = AmbaFake(pio_addr=0x10010000)
376 gpio0_fake = AmbaFake(pio_addr=0x10013000)
377 gpio1_fake = AmbaFake(pio_addr=0x10014000)
378 gpio2_fake = AmbaFake(pio_addr=0x10015000)
379 ssp_fake = AmbaFake(pio_addr=0x1000d000)
380 sci_fake = AmbaFake(pio_addr=0x1000e000)
381 aaci_fake = AmbaFake(pio_addr=0x10004000)
382 mmc_fake = AmbaFake(pio_addr=0x10005000)
383 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
384 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
385
386 # Attach I/O devices that are on chip and also set the appropriate
387 # ranges for the bridge
388 def attachOnChipIO(self, bus, bridge):
389 self.gic.pio = bus.master
390 self.l2x0_fake.pio = bus.master
391 # Bridge ranges based on excluding what is part of on-chip I/O
392 # (gic, l2x0)
393 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
394 self.gic.cpu_addr - 1),
395 AddrRange(self.flash_fake.pio_addr, Addr.max)]
396
397 # Set the clock domain for IO objects that are considered
398 # to be "close" to the cores.
399 def onChipIOClkDomain(self, clkdomain):
400 self.gic.clk_domain = clkdomain
401 self.l2x0_fake.clk_domain = clkdomain
402
403 # Attach I/O devices to specified bus object. Can't do this
404 # earlier, since the bus object itself is typically defined at the
405 # System level.
406 def attachIO(self, bus):
407 self.uart.pio = bus.master
408 self.realview_io.pio = bus.master
409 self.timer0.pio = bus.master
410 self.timer1.pio = bus.master
411 self.clcd.pio = bus.master
412 self.clcd.dma = bus.slave
413 self.kmi0.pio = bus.master
414 self.kmi1.pio = bus.master
415 self.dmac_fake.pio = bus.master
416 self.uart1_fake.pio = bus.master
417 self.uart2_fake.pio = bus.master
418 self.uart3_fake.pio = bus.master
419 self.smc_fake.pio = bus.master
420 self.sp810_fake.pio = bus.master
421 self.watchdog_fake.pio = bus.master
422 self.gpio0_fake.pio = bus.master
423 self.gpio1_fake.pio = bus.master
424 self.gpio2_fake.pio = bus.master
425 self.ssp_fake.pio = bus.master
426 self.sci_fake.pio = bus.master
427 self.aaci_fake.pio = bus.master
428 self.mmc_fake.pio = bus.master
429 self.rtc_fake.pio = bus.master
430 self.flash_fake.pio = bus.master
431 self.smcreg_fake.pio = bus.master
432 self.energy_ctrl.pio = bus.master
433
434 # Set the clock domain for IO objects that are considered
435 # to be "far" away from the cores.
436 def offChipIOClkDomain(self, clkdomain):
437 self.uart.clk_domain = clkdomain
438 self.realview_io.clk_domain = clkdomain
439 self.timer0.clk_domain = clkdomain
440 self.timer1.clk_domain = clkdomain
441 self.clcd.clk_domain = clkdomain
442 self.kmi0.clk_domain = clkdomain
443 self.kmi1.clk_domain = clkdomain
444 self.dmac_fake.clk_domain = clkdomain
445 self.uart1_fake.clk_domain = clkdomain
446 self.uart2_fake.clk_domain = clkdomain
447 self.uart3_fake.clk_domain = clkdomain
448 self.smc_fake.clk_domain = clkdomain
449 self.sp810_fake.clk_domain = clkdomain
450 self.watchdog_fake.clk_domain = clkdomain
451 self.gpio0_fake.clk_domain = clkdomain
452 self.gpio1_fake.clk_domain = clkdomain
453 self.gpio2_fake.clk_domain = clkdomain
454 self.ssp_fake.clk_domain = clkdomain
455 self.sci_fake.clk_domain = clkdomain
456 self.aaci_fake.clk_domain = clkdomain
457 self.mmc_fake.clk_domain = clkdomain
458 self.rtc.clk_domain = clkdomain
459 self.flash_fake.clk_domain = clkdomain
460 self.smcreg_fake.clk_domain = clkdomain
461 self.energy_ctrl.clk_domain = clkdomain
462
463class VExpress_EMM(RealView):
464 _mem_regions = [(Addr('2GB'), Addr('2GB'))]
465 pci_cfg_base = 0x30000000
466 uart = Pl011(pio_addr=0x1c090000, int_num=37)
| 403 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
404 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
405 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
406 clcd = Pl111(pio_addr=0x10020000, int_num=23)
407 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
408 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
409
410 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
411 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
412 fake_mem=True)
413 dmac_fake = AmbaFake(pio_addr=0x10030000)
414 uart1_fake = AmbaFake(pio_addr=0x1000a000)
415 uart2_fake = AmbaFake(pio_addr=0x1000b000)
416 uart3_fake = AmbaFake(pio_addr=0x1000c000)
417 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
418 smc_fake = AmbaFake(pio_addr=0x100e1000)
419 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
420 watchdog_fake = AmbaFake(pio_addr=0x10010000)
421 gpio0_fake = AmbaFake(pio_addr=0x10013000)
422 gpio1_fake = AmbaFake(pio_addr=0x10014000)
423 gpio2_fake = AmbaFake(pio_addr=0x10015000)
424 ssp_fake = AmbaFake(pio_addr=0x1000d000)
425 sci_fake = AmbaFake(pio_addr=0x1000e000)
426 aaci_fake = AmbaFake(pio_addr=0x10004000)
427 mmc_fake = AmbaFake(pio_addr=0x10005000)
428 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
429 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
430
431 # Attach I/O devices that are on chip and also set the appropriate
432 # ranges for the bridge
433 def attachOnChipIO(self, bus, bridge):
434 self.gic.pio = bus.master
435 self.l2x0_fake.pio = bus.master
436 # Bridge ranges based on excluding what is part of on-chip I/O
437 # (gic, l2x0)
438 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
439 self.gic.cpu_addr - 1),
440 AddrRange(self.flash_fake.pio_addr, Addr.max)]
441
442 # Set the clock domain for IO objects that are considered
443 # to be "close" to the cores.
444 def onChipIOClkDomain(self, clkdomain):
445 self.gic.clk_domain = clkdomain
446 self.l2x0_fake.clk_domain = clkdomain
447
448 # Attach I/O devices to specified bus object. Can't do this
449 # earlier, since the bus object itself is typically defined at the
450 # System level.
451 def attachIO(self, bus):
452 self.uart.pio = bus.master
453 self.realview_io.pio = bus.master
454 self.timer0.pio = bus.master
455 self.timer1.pio = bus.master
456 self.clcd.pio = bus.master
457 self.clcd.dma = bus.slave
458 self.kmi0.pio = bus.master
459 self.kmi1.pio = bus.master
460 self.dmac_fake.pio = bus.master
461 self.uart1_fake.pio = bus.master
462 self.uart2_fake.pio = bus.master
463 self.uart3_fake.pio = bus.master
464 self.smc_fake.pio = bus.master
465 self.sp810_fake.pio = bus.master
466 self.watchdog_fake.pio = bus.master
467 self.gpio0_fake.pio = bus.master
468 self.gpio1_fake.pio = bus.master
469 self.gpio2_fake.pio = bus.master
470 self.ssp_fake.pio = bus.master
471 self.sci_fake.pio = bus.master
472 self.aaci_fake.pio = bus.master
473 self.mmc_fake.pio = bus.master
474 self.rtc_fake.pio = bus.master
475 self.flash_fake.pio = bus.master
476 self.smcreg_fake.pio = bus.master
477 self.energy_ctrl.pio = bus.master
478
479 # Set the clock domain for IO objects that are considered
480 # to be "far" away from the cores.
481 def offChipIOClkDomain(self, clkdomain):
482 self.uart.clk_domain = clkdomain
483 self.realview_io.clk_domain = clkdomain
484 self.timer0.clk_domain = clkdomain
485 self.timer1.clk_domain = clkdomain
486 self.clcd.clk_domain = clkdomain
487 self.kmi0.clk_domain = clkdomain
488 self.kmi1.clk_domain = clkdomain
489 self.dmac_fake.clk_domain = clkdomain
490 self.uart1_fake.clk_domain = clkdomain
491 self.uart2_fake.clk_domain = clkdomain
492 self.uart3_fake.clk_domain = clkdomain
493 self.smc_fake.clk_domain = clkdomain
494 self.sp810_fake.clk_domain = clkdomain
495 self.watchdog_fake.clk_domain = clkdomain
496 self.gpio0_fake.clk_domain = clkdomain
497 self.gpio1_fake.clk_domain = clkdomain
498 self.gpio2_fake.clk_domain = clkdomain
499 self.ssp_fake.clk_domain = clkdomain
500 self.sci_fake.clk_domain = clkdomain
501 self.aaci_fake.clk_domain = clkdomain
502 self.mmc_fake.clk_domain = clkdomain
503 self.rtc.clk_domain = clkdomain
504 self.flash_fake.clk_domain = clkdomain
505 self.smcreg_fake.clk_domain = clkdomain
506 self.energy_ctrl.clk_domain = clkdomain
507
508class VExpress_EMM(RealView):
509 _mem_regions = [(Addr('2GB'), Addr('2GB'))]
510 pci_cfg_base = 0x30000000
511 uart = Pl011(pio_addr=0x1c090000, int_num=37)
|
467 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \
468 idreg=0x02250000, pio_addr=0x1C010000)
| 512 realview_io = VExpressCoreTileCtrl(
513 proc_id0=0x14000000, proc_id1=0x14000000,
514 idreg=0x02250000, pio_addr=0x1C010000)
|
469 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
470 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000)
471 generic_timer = GenericTimer(int_phys=29, int_virt=27)
472 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
473 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
474 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
475 hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117)
476 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
477 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
478 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
479 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
480 io_shift = 2, ctrl_offset = 2, Command = 0x1,
481 BAR0 = 0x1C1A0000, BAR0Size = '256B',
482 BAR1 = 0x1C1A0100, BAR1Size = '4096B',
483 BAR0LegacyIO = True, BAR1LegacyIO = True)
484
485 pciconfig = PciConfigAll(size='256MB')
486 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
487 conf_table_reported = False)
488 rtc = PL031(pio_addr=0x1C170000, int_num=36)
489
490 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
491 uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
492 uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
493 uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
494 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
495 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
496 aaci_fake = AmbaFake(pio_addr=0x1C040000)
497 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
498 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
499 mmc_fake = AmbaFake(pio_addr=0x1c050000)
500 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000)
501
502 # Attach any PCI devices that are supported
503 def attachPciDevices(self):
504 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
505 InterruptLine=1, InterruptPin=1)
506 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
507 InterruptLine=2, InterruptPin=2)
508
509 def enableMSIX(self):
510 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
511 self.gicv2m = Gicv2m()
512 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
513
514 def setupBootLoader(self, mem_bus, cur_sys, loc):
515 self.nvmem = SimpleMemory(range = AddrRange('64MB'),
516 conf_table_reported = False)
517 self.nvmem.port = mem_bus.master
518 cur_sys.boot_loader = loc('boot_emm.arm')
519 cur_sys.atags_addr = 0x8000000
520 cur_sys.load_addr_mask = 0xfffffff
521 cur_sys.load_offset = 0x80000000
522
523 # Attach I/O devices that are on chip and also set the appropriate
524 # ranges for the bridge
525 def attachOnChipIO(self, bus, bridge=None):
526 self.gic.pio = bus.master
527 self.vgic.pio = bus.master
528 self.local_cpu_timer.pio = bus.master
529 if hasattr(self, "gicv2m"):
530 self.gicv2m.pio = bus.master
531 self.hdlcd.dma = bus.slave
532 if bridge:
533 # Bridge ranges based on excluding what is part of on-chip I/O
534 # (gic, a9scu)
535 bridge.ranges = [AddrRange(0x2F000000, size='16MB'),
536 AddrRange(0x2B000000, size='4MB'),
537 AddrRange(0x30000000, size='256MB'),
538 AddrRange(0x40000000, size='512MB'),
539 AddrRange(0x18000000, size='64MB'),
540 AddrRange(0x1C000000, size='64MB')]
541
542
543 # Set the clock domain for IO objects that are considered
544 # to be "close" to the cores.
545 def onChipIOClkDomain(self, clkdomain):
546 self.gic.clk_domain = clkdomain
547 if hasattr(self, "gicv2m"):
548 self.gicv2m.clk_domain = clkdomain
549 self.hdlcd.clk_domain = clkdomain
550 self.vgic.clk_domain = clkdomain
551
552 # Attach I/O devices to specified bus object. Done here
553 # as the specified bus to connect to may not always be fixed.
554 def attachIO(self, bus):
555 self.uart.pio = bus.master
556 self.realview_io.pio = bus.master
557 self.timer0.pio = bus.master
558 self.timer1.pio = bus.master
559 self.clcd.pio = bus.master
560 self.clcd.dma = bus.slave
561 self.hdlcd.pio = bus.master
562 self.kmi0.pio = bus.master
563 self.kmi1.pio = bus.master
564 self.cf_ctrl.pio = bus.master
565 self.cf_ctrl.dma = bus.slave
566 self.cf_ctrl.config = bus.master
567 self.rtc.pio = bus.master
568 bus.use_default_range = True
569 self.vram.port = bus.master
570 self.pciconfig.pio = bus.default
571
572 self.l2x0_fake.pio = bus.master
573 self.uart1_fake.pio = bus.master
574 self.uart2_fake.pio = bus.master
575 self.uart3_fake.pio = bus.master
576 self.sp810_fake.pio = bus.master
577 self.watchdog_fake.pio = bus.master
578 self.aaci_fake.pio = bus.master
579 self.lan_fake.pio = bus.master
580 self.usb_fake.pio = bus.master
581 self.mmc_fake.pio = bus.master
582 self.energy_ctrl.pio = bus.master
583
584 # Try to attach the I/O if it exists
585 try:
586 self.ide.pio = bus.master
587 self.ide.config = bus.master
588 self.ide.dma = bus.slave
589 self.ethernet.pio = bus.master
590 self.ethernet.config = bus.master
591 self.ethernet.dma = bus.slave
592 except:
593 pass
594
595 # Set the clock domain for IO objects that are considered
596 # to be "far" away from the cores.
597 def offChipIOClkDomain(self, clkdomain):
598 self.uart.clk_domain = clkdomain
599 self.realview_io.clk_domain = clkdomain
600 self.timer0.clk_domain = clkdomain
601 self.timer1.clk_domain = clkdomain
602 self.clcd.clk_domain = clkdomain
603 self.kmi0.clk_domain = clkdomain
604 self.kmi1.clk_domain = clkdomain
605 self.cf_ctrl.clk_domain = clkdomain
606 self.rtc.clk_domain = clkdomain
607 self.vram.clk_domain = clkdomain
608 self.pciconfig.clk_domain = clkdomain
609
610 self.l2x0_fake.clk_domain = clkdomain
611 self.uart1_fake.clk_domain = clkdomain
612 self.uart2_fake.clk_domain = clkdomain
613 self.uart3_fake.clk_domain = clkdomain
614 self.sp810_fake.clk_domain = clkdomain
615 self.watchdog_fake.clk_domain = clkdomain
616 self.aaci_fake.clk_domain = clkdomain
617 self.lan_fake.clk_domain = clkdomain
618 self.usb_fake.clk_domain = clkdomain
619 self.mmc_fake.clk_domain = clkdomain
620 self.energy_ctrl.clk_domain = clkdomain
621
622class VExpress_EMM64(VExpress_EMM):
623 pci_io_base = 0x2f000000
624 pci_cfg_gen_offsets = True
625 # Three memory regions are specified totalling 512GB
626 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
627 (Addr('512GB'), Addr('480GB'))]
628 def setupBootLoader(self, mem_bus, cur_sys, loc):
629 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
630 self.nvmem.port = mem_bus.master
631 cur_sys.boot_loader = loc('boot_emm.arm64')
632 cur_sys.atags_addr = 0x8000000
633 cur_sys.load_addr_mask = 0xfffffff
634 cur_sys.load_offset = 0x80000000
635
636
| 515 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
516 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000)
517 generic_timer = GenericTimer(int_phys=29, int_virt=27)
518 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
519 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
520 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
521 hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117)
522 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
523 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
524 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
525 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
526 io_shift = 2, ctrl_offset = 2, Command = 0x1,
527 BAR0 = 0x1C1A0000, BAR0Size = '256B',
528 BAR1 = 0x1C1A0100, BAR1Size = '4096B',
529 BAR0LegacyIO = True, BAR1LegacyIO = True)
530
531 pciconfig = PciConfigAll(size='256MB')
532 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
533 conf_table_reported = False)
534 rtc = PL031(pio_addr=0x1C170000, int_num=36)
535
536 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
537 uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
538 uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
539 uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
540 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
541 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
542 aaci_fake = AmbaFake(pio_addr=0x1C040000)
543 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
544 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
545 mmc_fake = AmbaFake(pio_addr=0x1c050000)
546 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000)
547
548 # Attach any PCI devices that are supported
549 def attachPciDevices(self):
550 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
551 InterruptLine=1, InterruptPin=1)
552 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
553 InterruptLine=2, InterruptPin=2)
554
555 def enableMSIX(self):
556 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
557 self.gicv2m = Gicv2m()
558 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
559
560 def setupBootLoader(self, mem_bus, cur_sys, loc):
561 self.nvmem = SimpleMemory(range = AddrRange('64MB'),
562 conf_table_reported = False)
563 self.nvmem.port = mem_bus.master
564 cur_sys.boot_loader = loc('boot_emm.arm')
565 cur_sys.atags_addr = 0x8000000
566 cur_sys.load_addr_mask = 0xfffffff
567 cur_sys.load_offset = 0x80000000
568
569 # Attach I/O devices that are on chip and also set the appropriate
570 # ranges for the bridge
571 def attachOnChipIO(self, bus, bridge=None):
572 self.gic.pio = bus.master
573 self.vgic.pio = bus.master
574 self.local_cpu_timer.pio = bus.master
575 if hasattr(self, "gicv2m"):
576 self.gicv2m.pio = bus.master
577 self.hdlcd.dma = bus.slave
578 if bridge:
579 # Bridge ranges based on excluding what is part of on-chip I/O
580 # (gic, a9scu)
581 bridge.ranges = [AddrRange(0x2F000000, size='16MB'),
582 AddrRange(0x2B000000, size='4MB'),
583 AddrRange(0x30000000, size='256MB'),
584 AddrRange(0x40000000, size='512MB'),
585 AddrRange(0x18000000, size='64MB'),
586 AddrRange(0x1C000000, size='64MB')]
587
588
589 # Set the clock domain for IO objects that are considered
590 # to be "close" to the cores.
591 def onChipIOClkDomain(self, clkdomain):
592 self.gic.clk_domain = clkdomain
593 if hasattr(self, "gicv2m"):
594 self.gicv2m.clk_domain = clkdomain
595 self.hdlcd.clk_domain = clkdomain
596 self.vgic.clk_domain = clkdomain
597
598 # Attach I/O devices to specified bus object. Done here
599 # as the specified bus to connect to may not always be fixed.
600 def attachIO(self, bus):
601 self.uart.pio = bus.master
602 self.realview_io.pio = bus.master
603 self.timer0.pio = bus.master
604 self.timer1.pio = bus.master
605 self.clcd.pio = bus.master
606 self.clcd.dma = bus.slave
607 self.hdlcd.pio = bus.master
608 self.kmi0.pio = bus.master
609 self.kmi1.pio = bus.master
610 self.cf_ctrl.pio = bus.master
611 self.cf_ctrl.dma = bus.slave
612 self.cf_ctrl.config = bus.master
613 self.rtc.pio = bus.master
614 bus.use_default_range = True
615 self.vram.port = bus.master
616 self.pciconfig.pio = bus.default
617
618 self.l2x0_fake.pio = bus.master
619 self.uart1_fake.pio = bus.master
620 self.uart2_fake.pio = bus.master
621 self.uart3_fake.pio = bus.master
622 self.sp810_fake.pio = bus.master
623 self.watchdog_fake.pio = bus.master
624 self.aaci_fake.pio = bus.master
625 self.lan_fake.pio = bus.master
626 self.usb_fake.pio = bus.master
627 self.mmc_fake.pio = bus.master
628 self.energy_ctrl.pio = bus.master
629
630 # Try to attach the I/O if it exists
631 try:
632 self.ide.pio = bus.master
633 self.ide.config = bus.master
634 self.ide.dma = bus.slave
635 self.ethernet.pio = bus.master
636 self.ethernet.config = bus.master
637 self.ethernet.dma = bus.slave
638 except:
639 pass
640
641 # Set the clock domain for IO objects that are considered
642 # to be "far" away from the cores.
643 def offChipIOClkDomain(self, clkdomain):
644 self.uart.clk_domain = clkdomain
645 self.realview_io.clk_domain = clkdomain
646 self.timer0.clk_domain = clkdomain
647 self.timer1.clk_domain = clkdomain
648 self.clcd.clk_domain = clkdomain
649 self.kmi0.clk_domain = clkdomain
650 self.kmi1.clk_domain = clkdomain
651 self.cf_ctrl.clk_domain = clkdomain
652 self.rtc.clk_domain = clkdomain
653 self.vram.clk_domain = clkdomain
654 self.pciconfig.clk_domain = clkdomain
655
656 self.l2x0_fake.clk_domain = clkdomain
657 self.uart1_fake.clk_domain = clkdomain
658 self.uart2_fake.clk_domain = clkdomain
659 self.uart3_fake.clk_domain = clkdomain
660 self.sp810_fake.clk_domain = clkdomain
661 self.watchdog_fake.clk_domain = clkdomain
662 self.aaci_fake.clk_domain = clkdomain
663 self.lan_fake.clk_domain = clkdomain
664 self.usb_fake.clk_domain = clkdomain
665 self.mmc_fake.clk_domain = clkdomain
666 self.energy_ctrl.clk_domain = clkdomain
667
668class VExpress_EMM64(VExpress_EMM):
669 pci_io_base = 0x2f000000
670 pci_cfg_gen_offsets = True
671 # Three memory regions are specified totalling 512GB
672 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
673 (Addr('512GB'), Addr('480GB'))]
674 def setupBootLoader(self, mem_bus, cur_sys, loc):
675 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
676 self.nvmem.port = mem_bus.master
677 cur_sys.boot_loader = loc('boot_emm.arm64')
678 cur_sys.atags_addr = 0x8000000
679 cur_sys.load_addr_mask = 0xfffffff
680 cur_sys.load_offset = 0x80000000
681
682
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