1# Copyright (c) 2009-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42
43from m5.params import *
44from m5.proxy import *
45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
46from Pci import PciConfigAll
47from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
48from Ide import *
49from Platform import Platform
50from Terminal import Terminal
51from Uart import Uart
52from SimpleMemory import SimpleMemory
53from Gic import *
| 1# Copyright (c) 2009-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42
43from m5.params import *
44from m5.proxy import *
45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
46from Pci import PciConfigAll
47from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
48from Ide import *
49from Platform import Platform
50from Terminal import Terminal
51from Uart import Uart
52from SimpleMemory import SimpleMemory
53from Gic import *
|
| 54from EnergyCtrl import EnergyCtrl
|
54
55class AmbaPioDevice(BasicPioDevice):
56 type = 'AmbaPioDevice'
57 abstract = True
58 cxx_header = "dev/arm/amba_device.hh"
59 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
60
61class AmbaIntDevice(AmbaPioDevice):
62 type = 'AmbaIntDevice'
63 abstract = True
64 cxx_header = "dev/arm/amba_device.hh"
65 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
66 int_num = Param.UInt32("Interrupt number that connects to GIC")
67 int_delay = Param.Latency("100ns",
68 "Time between action and interrupt generation by device")
69
70class AmbaDmaDevice(DmaDevice):
71 type = 'AmbaDmaDevice'
72 abstract = True
73 cxx_header = "dev/arm/amba_device.hh"
74 pio_addr = Param.Addr("Address for AMBA slave interface")
75 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
76 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
77 int_num = Param.UInt32("Interrupt number that connects to GIC")
78 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
79
80class A9SCU(BasicPioDevice):
81 type = 'A9SCU'
82 cxx_header = "dev/arm/a9scu.hh"
83
84class RealViewCtrl(BasicPioDevice):
85 type = 'RealViewCtrl'
86 cxx_header = "dev/arm/rv_ctrl.hh"
87 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
88 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
89 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
90
91class VGic(PioDevice):
92 type = 'VGic'
93 cxx_header = "dev/arm/vgic.hh"
94 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
95 platform = Param.Platform(Parent.any, "Platform this device is part of.")
96 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
97 hv_addr = Param.Addr(0, "Address for hv control")
98 pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
99 # The number of list registers is not currently configurable at runtime.
100 ppint = Param.UInt32("HV maintenance interrupt number")
101
102class AmbaFake(AmbaPioDevice):
103 type = 'AmbaFake'
104 cxx_header = "dev/arm/amba_fake.hh"
105 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
106 amba_id = 0;
107
108class Pl011(Uart):
109 type = 'Pl011'
110 cxx_header = "dev/arm/pl011.hh"
111 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
112 int_num = Param.UInt32("Interrupt number that connects to GIC")
113 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
114 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
115
116class Sp804(AmbaPioDevice):
117 type = 'Sp804'
118 cxx_header = "dev/arm/timer_sp804.hh"
119 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
120 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
121 clock0 = Param.Clock('1MHz', "Clock speed of the input")
122 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
123 clock1 = Param.Clock('1MHz', "Clock speed of the input")
124 amba_id = 0x00141804
125
126class CpuLocalTimer(BasicPioDevice):
127 type = 'CpuLocalTimer'
128 cxx_header = "dev/arm/timer_cpulocal.hh"
129 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
130 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
131 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
132
133class GenericTimer(SimObject):
134 type = 'GenericTimer'
135 cxx_header = "dev/arm/generic_timer.hh"
136 system = Param.System(Parent.any, "system")
137 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
138 int_num = Param.UInt32("Interrupt number used per-cpu to GIC")
139 # @todo: for now only one timer per CPU is supported, which is the
140 # normal behaviour when Security and Virt. extensions are disabled.
141
142class PL031(AmbaIntDevice):
143 type = 'PL031'
144 cxx_header = "dev/arm/rtc_pl031.hh"
145 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
146 amba_id = 0x00341031
147
148class Pl050(AmbaIntDevice):
149 type = 'Pl050'
150 cxx_header = "dev/arm/kmi.hh"
151 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
152 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
153 int_delay = '1us'
154 amba_id = 0x00141050
155
156class Pl111(AmbaDmaDevice):
157 type = 'Pl111'
158 cxx_header = "dev/arm/pl111.hh"
159 pixel_clock = Param.Clock('24MHz', "Pixel clock")
160 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
161 amba_id = 0x00141111
162 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
163
164
165class HDLcd(AmbaDmaDevice):
166 type = 'HDLcd'
167 cxx_header = "dev/arm/hdlcd.hh"
168 # For reference, 1024x768MR-16@60 ~= 56 MHz
169 # 1920x1080MR-16@60 ~= 137 MHz
170 # 3840x2160MR-16@60 ~= 533 MHz
171 # Match against the resolution selected in the Linux DTS/DTB file.
172 pixel_clock = Param.Clock('137MHz', "Clock frequency of the pixel clock "
173 "(i.e. PXLREFCLK / OSCCLK 5")
174 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer "
175 "display")
176 amba_id = 0x00141000
177 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
178
179class RealView(Platform):
180 type = 'RealView'
181 cxx_header = "dev/arm/realview.hh"
182 system = Param.System(Parent.any, "system")
183 pci_io_base = Param.Addr(0, "Base address of PCI IO Space")
184 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
185 pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access"
186 " be compatible with the pci-generic-host or the legacy host bridge?")
187 _mem_regions = [(Addr(0), Addr('256MB'))]
188
189 def attachPciDevices(self):
190 pass
191
192 def enableMSIX(self):
193 pass
194
195 def onChipIOClkDomain(self, clkdomain):
196 pass
197
198 def offChipIOClkDomain(self, clkdomain):
199 pass
200
201 def setupBootLoader(self, mem_bus, cur_sys, loc):
202 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
203 conf_table_reported = False)
204 self.nvmem.port = mem_bus.master
205 cur_sys.boot_loader = loc('boot.arm')
206 cur_sys.atags_addr = 0x100
207 cur_sys.load_addr_mask = 0xfffffff
208 cur_sys.load_offset = 0
209
210
211# Reference for memory map and interrupt number
212# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
213# Chapter 4: Programmer's Reference
214class RealViewPBX(RealView):
215 uart = Pl011(pio_addr=0x10009000, int_num=44)
216 realview_io = RealViewCtrl(pio_addr=0x10000000)
217 gic = Pl390()
218 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
219 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
220 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600)
221 clcd = Pl111(pio_addr=0x10020000, int_num=55)
222 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
223 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
224 a9scu = A9SCU(pio_addr=0x1f000000)
225 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
226 io_shift = 1, ctrl_offset = 2, Command = 0x1,
227 BAR0 = 0x18000000, BAR0Size = '16B',
228 BAR1 = 0x18000100, BAR1Size = '1B',
229 BAR0LegacyIO = True, BAR1LegacyIO = True)
230
231
232 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
233 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
234 fake_mem=True)
235 dmac_fake = AmbaFake(pio_addr=0x10030000)
236 uart1_fake = AmbaFake(pio_addr=0x1000a000)
237 uart2_fake = AmbaFake(pio_addr=0x1000b000)
238 uart3_fake = AmbaFake(pio_addr=0x1000c000)
239 smc_fake = AmbaFake(pio_addr=0x100e1000)
240 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
241 watchdog_fake = AmbaFake(pio_addr=0x10010000)
242 gpio0_fake = AmbaFake(pio_addr=0x10013000)
243 gpio1_fake = AmbaFake(pio_addr=0x10014000)
244 gpio2_fake = AmbaFake(pio_addr=0x10015000)
245 ssp_fake = AmbaFake(pio_addr=0x1000d000)
246 sci_fake = AmbaFake(pio_addr=0x1000e000)
247 aaci_fake = AmbaFake(pio_addr=0x10004000)
248 mmc_fake = AmbaFake(pio_addr=0x10005000)
249 rtc = PL031(pio_addr=0x10017000, int_num=42)
| 55
56class AmbaPioDevice(BasicPioDevice):
57 type = 'AmbaPioDevice'
58 abstract = True
59 cxx_header = "dev/arm/amba_device.hh"
60 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
61
62class AmbaIntDevice(AmbaPioDevice):
63 type = 'AmbaIntDevice'
64 abstract = True
65 cxx_header = "dev/arm/amba_device.hh"
66 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
67 int_num = Param.UInt32("Interrupt number that connects to GIC")
68 int_delay = Param.Latency("100ns",
69 "Time between action and interrupt generation by device")
70
71class AmbaDmaDevice(DmaDevice):
72 type = 'AmbaDmaDevice'
73 abstract = True
74 cxx_header = "dev/arm/amba_device.hh"
75 pio_addr = Param.Addr("Address for AMBA slave interface")
76 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
77 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
78 int_num = Param.UInt32("Interrupt number that connects to GIC")
79 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
80
81class A9SCU(BasicPioDevice):
82 type = 'A9SCU'
83 cxx_header = "dev/arm/a9scu.hh"
84
85class RealViewCtrl(BasicPioDevice):
86 type = 'RealViewCtrl'
87 cxx_header = "dev/arm/rv_ctrl.hh"
88 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
89 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
90 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
91
92class VGic(PioDevice):
93 type = 'VGic'
94 cxx_header = "dev/arm/vgic.hh"
95 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
96 platform = Param.Platform(Parent.any, "Platform this device is part of.")
97 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
98 hv_addr = Param.Addr(0, "Address for hv control")
99 pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
100 # The number of list registers is not currently configurable at runtime.
101 ppint = Param.UInt32("HV maintenance interrupt number")
102
103class AmbaFake(AmbaPioDevice):
104 type = 'AmbaFake'
105 cxx_header = "dev/arm/amba_fake.hh"
106 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
107 amba_id = 0;
108
109class Pl011(Uart):
110 type = 'Pl011'
111 cxx_header = "dev/arm/pl011.hh"
112 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
113 int_num = Param.UInt32("Interrupt number that connects to GIC")
114 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
115 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
116
117class Sp804(AmbaPioDevice):
118 type = 'Sp804'
119 cxx_header = "dev/arm/timer_sp804.hh"
120 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
121 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
122 clock0 = Param.Clock('1MHz', "Clock speed of the input")
123 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
124 clock1 = Param.Clock('1MHz', "Clock speed of the input")
125 amba_id = 0x00141804
126
127class CpuLocalTimer(BasicPioDevice):
128 type = 'CpuLocalTimer'
129 cxx_header = "dev/arm/timer_cpulocal.hh"
130 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
131 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
132 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
133
134class GenericTimer(SimObject):
135 type = 'GenericTimer'
136 cxx_header = "dev/arm/generic_timer.hh"
137 system = Param.System(Parent.any, "system")
138 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
139 int_num = Param.UInt32("Interrupt number used per-cpu to GIC")
140 # @todo: for now only one timer per CPU is supported, which is the
141 # normal behaviour when Security and Virt. extensions are disabled.
142
143class PL031(AmbaIntDevice):
144 type = 'PL031'
145 cxx_header = "dev/arm/rtc_pl031.hh"
146 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
147 amba_id = 0x00341031
148
149class Pl050(AmbaIntDevice):
150 type = 'Pl050'
151 cxx_header = "dev/arm/kmi.hh"
152 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
153 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
154 int_delay = '1us'
155 amba_id = 0x00141050
156
157class Pl111(AmbaDmaDevice):
158 type = 'Pl111'
159 cxx_header = "dev/arm/pl111.hh"
160 pixel_clock = Param.Clock('24MHz', "Pixel clock")
161 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
162 amba_id = 0x00141111
163 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
164
165
166class HDLcd(AmbaDmaDevice):
167 type = 'HDLcd'
168 cxx_header = "dev/arm/hdlcd.hh"
169 # For reference, 1024x768MR-16@60 ~= 56 MHz
170 # 1920x1080MR-16@60 ~= 137 MHz
171 # 3840x2160MR-16@60 ~= 533 MHz
172 # Match against the resolution selected in the Linux DTS/DTB file.
173 pixel_clock = Param.Clock('137MHz', "Clock frequency of the pixel clock "
174 "(i.e. PXLREFCLK / OSCCLK 5")
175 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer "
176 "display")
177 amba_id = 0x00141000
178 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
179
180class RealView(Platform):
181 type = 'RealView'
182 cxx_header = "dev/arm/realview.hh"
183 system = Param.System(Parent.any, "system")
184 pci_io_base = Param.Addr(0, "Base address of PCI IO Space")
185 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
186 pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access"
187 " be compatible with the pci-generic-host or the legacy host bridge?")
188 _mem_regions = [(Addr(0), Addr('256MB'))]
189
190 def attachPciDevices(self):
191 pass
192
193 def enableMSIX(self):
194 pass
195
196 def onChipIOClkDomain(self, clkdomain):
197 pass
198
199 def offChipIOClkDomain(self, clkdomain):
200 pass
201
202 def setupBootLoader(self, mem_bus, cur_sys, loc):
203 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
204 conf_table_reported = False)
205 self.nvmem.port = mem_bus.master
206 cur_sys.boot_loader = loc('boot.arm')
207 cur_sys.atags_addr = 0x100
208 cur_sys.load_addr_mask = 0xfffffff
209 cur_sys.load_offset = 0
210
211
212# Reference for memory map and interrupt number
213# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
214# Chapter 4: Programmer's Reference
215class RealViewPBX(RealView):
216 uart = Pl011(pio_addr=0x10009000, int_num=44)
217 realview_io = RealViewCtrl(pio_addr=0x10000000)
218 gic = Pl390()
219 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
220 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
221 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600)
222 clcd = Pl111(pio_addr=0x10020000, int_num=55)
223 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
224 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
225 a9scu = A9SCU(pio_addr=0x1f000000)
226 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
227 io_shift = 1, ctrl_offset = 2, Command = 0x1,
228 BAR0 = 0x18000000, BAR0Size = '16B',
229 BAR1 = 0x18000100, BAR1Size = '1B',
230 BAR0LegacyIO = True, BAR1LegacyIO = True)
231
232
233 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
234 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
235 fake_mem=True)
236 dmac_fake = AmbaFake(pio_addr=0x10030000)
237 uart1_fake = AmbaFake(pio_addr=0x1000a000)
238 uart2_fake = AmbaFake(pio_addr=0x1000b000)
239 uart3_fake = AmbaFake(pio_addr=0x1000c000)
240 smc_fake = AmbaFake(pio_addr=0x100e1000)
241 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
242 watchdog_fake = AmbaFake(pio_addr=0x10010000)
243 gpio0_fake = AmbaFake(pio_addr=0x10013000)
244 gpio1_fake = AmbaFake(pio_addr=0x10014000)
245 gpio2_fake = AmbaFake(pio_addr=0x10015000)
246 ssp_fake = AmbaFake(pio_addr=0x1000d000)
247 sci_fake = AmbaFake(pio_addr=0x1000e000)
248 aaci_fake = AmbaFake(pio_addr=0x10004000)
249 mmc_fake = AmbaFake(pio_addr=0x10005000)
250 rtc = PL031(pio_addr=0x10017000, int_num=42)
|
| 251 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
|
250
251
252 # Attach I/O devices that are on chip and also set the appropriate
253 # ranges for the bridge
254 def attachOnChipIO(self, bus, bridge):
255 self.gic.pio = bus.master
256 self.l2x0_fake.pio = bus.master
257 self.a9scu.pio = bus.master
258 self.local_cpu_timer.pio = bus.master
259 # Bridge ranges based on excluding what is part of on-chip I/O
260 # (gic, l2x0, a9scu, local_cpu_timer)
261 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
262 self.a9scu.pio_addr - 1),
263 AddrRange(self.flash_fake.pio_addr,
264 self.flash_fake.pio_addr + \
265 self.flash_fake.pio_size - 1)]
266
267 # Set the clock domain for IO objects that are considered
268 # to be "close" to the cores.
269 def onChipIOClkDomain(self, clkdomain):
270 self.gic.clk_domain = clkdomain
271 self.l2x0_fake.clk_domain = clkdomain
272 self.a9scu.clkdomain = clkdomain
273 self.local_cpu_timer.clk_domain = clkdomain
274
275 # Attach I/O devices to specified bus object. Can't do this
276 # earlier, since the bus object itself is typically defined at the
277 # System level.
278 def attachIO(self, bus):
279 self.uart.pio = bus.master
280 self.realview_io.pio = bus.master
281 self.timer0.pio = bus.master
282 self.timer1.pio = bus.master
283 self.clcd.pio = bus.master
284 self.clcd.dma = bus.slave
285 self.kmi0.pio = bus.master
286 self.kmi1.pio = bus.master
287 self.cf_ctrl.pio = bus.master
288 self.cf_ctrl.config = bus.master
289 self.cf_ctrl.dma = bus.slave
290 self.dmac_fake.pio = bus.master
291 self.uart1_fake.pio = bus.master
292 self.uart2_fake.pio = bus.master
293 self.uart3_fake.pio = bus.master
294 self.smc_fake.pio = bus.master
295 self.sp810_fake.pio = bus.master
296 self.watchdog_fake.pio = bus.master
297 self.gpio0_fake.pio = bus.master
298 self.gpio1_fake.pio = bus.master
299 self.gpio2_fake.pio = bus.master
300 self.ssp_fake.pio = bus.master
301 self.sci_fake.pio = bus.master
302 self.aaci_fake.pio = bus.master
303 self.mmc_fake.pio = bus.master
304 self.rtc.pio = bus.master
305 self.flash_fake.pio = bus.master
| 252
253
254 # Attach I/O devices that are on chip and also set the appropriate
255 # ranges for the bridge
256 def attachOnChipIO(self, bus, bridge):
257 self.gic.pio = bus.master
258 self.l2x0_fake.pio = bus.master
259 self.a9scu.pio = bus.master
260 self.local_cpu_timer.pio = bus.master
261 # Bridge ranges based on excluding what is part of on-chip I/O
262 # (gic, l2x0, a9scu, local_cpu_timer)
263 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
264 self.a9scu.pio_addr - 1),
265 AddrRange(self.flash_fake.pio_addr,
266 self.flash_fake.pio_addr + \
267 self.flash_fake.pio_size - 1)]
268
269 # Set the clock domain for IO objects that are considered
270 # to be "close" to the cores.
271 def onChipIOClkDomain(self, clkdomain):
272 self.gic.clk_domain = clkdomain
273 self.l2x0_fake.clk_domain = clkdomain
274 self.a9scu.clkdomain = clkdomain
275 self.local_cpu_timer.clk_domain = clkdomain
276
277 # Attach I/O devices to specified bus object. Can't do this
278 # earlier, since the bus object itself is typically defined at the
279 # System level.
280 def attachIO(self, bus):
281 self.uart.pio = bus.master
282 self.realview_io.pio = bus.master
283 self.timer0.pio = bus.master
284 self.timer1.pio = bus.master
285 self.clcd.pio = bus.master
286 self.clcd.dma = bus.slave
287 self.kmi0.pio = bus.master
288 self.kmi1.pio = bus.master
289 self.cf_ctrl.pio = bus.master
290 self.cf_ctrl.config = bus.master
291 self.cf_ctrl.dma = bus.slave
292 self.dmac_fake.pio = bus.master
293 self.uart1_fake.pio = bus.master
294 self.uart2_fake.pio = bus.master
295 self.uart3_fake.pio = bus.master
296 self.smc_fake.pio = bus.master
297 self.sp810_fake.pio = bus.master
298 self.watchdog_fake.pio = bus.master
299 self.gpio0_fake.pio = bus.master
300 self.gpio1_fake.pio = bus.master
301 self.gpio2_fake.pio = bus.master
302 self.ssp_fake.pio = bus.master
303 self.sci_fake.pio = bus.master
304 self.aaci_fake.pio = bus.master
305 self.mmc_fake.pio = bus.master
306 self.rtc.pio = bus.master
307 self.flash_fake.pio = bus.master
|
| 308 self.energy_ctrl.pio = bus.master
|
306
307 # Set the clock domain for IO objects that are considered
308 # to be "far" away from the cores.
309 def offChipIOClkDomain(self, clkdomain):
310 self.uart.clk_domain = clkdomain
311 self.realview_io.clk_domain = clkdomain
312 self.timer0.clk_domain = clkdomain
313 self.timer1.clk_domain = clkdomain
314 self.clcd.clk_domain = clkdomain
315 self.kmi0.clk_domain = clkdomain
316 self.kmi1.clk_domain = clkdomain
317 self.cf_ctrl.clk_domain = clkdomain
318 self.dmac_fake.clk_domain = clkdomain
319 self.uart1_fake.clk_domain = clkdomain
320 self.uart2_fake.clk_domain = clkdomain
321 self.uart3_fake.clk_domain = clkdomain
322 self.smc_fake.clk_domain = clkdomain
323 self.sp810_fake.clk_domain = clkdomain
324 self.watchdog_fake.clk_domain = clkdomain
325 self.gpio0_fake.clk_domain = clkdomain
326 self.gpio1_fake.clk_domain = clkdomain
327 self.gpio2_fake.clk_domain = clkdomain
328 self.ssp_fake.clk_domain = clkdomain
329 self.sci_fake.clk_domain = clkdomain
330 self.aaci_fake.clk_domain = clkdomain
331 self.mmc_fake.clk_domain = clkdomain
332 self.rtc.clk_domain = clkdomain
333 self.flash_fake.clk_domain = clkdomain
| 309
310 # Set the clock domain for IO objects that are considered
311 # to be "far" away from the cores.
312 def offChipIOClkDomain(self, clkdomain):
313 self.uart.clk_domain = clkdomain
314 self.realview_io.clk_domain = clkdomain
315 self.timer0.clk_domain = clkdomain
316 self.timer1.clk_domain = clkdomain
317 self.clcd.clk_domain = clkdomain
318 self.kmi0.clk_domain = clkdomain
319 self.kmi1.clk_domain = clkdomain
320 self.cf_ctrl.clk_domain = clkdomain
321 self.dmac_fake.clk_domain = clkdomain
322 self.uart1_fake.clk_domain = clkdomain
323 self.uart2_fake.clk_domain = clkdomain
324 self.uart3_fake.clk_domain = clkdomain
325 self.smc_fake.clk_domain = clkdomain
326 self.sp810_fake.clk_domain = clkdomain
327 self.watchdog_fake.clk_domain = clkdomain
328 self.gpio0_fake.clk_domain = clkdomain
329 self.gpio1_fake.clk_domain = clkdomain
330 self.gpio2_fake.clk_domain = clkdomain
331 self.ssp_fake.clk_domain = clkdomain
332 self.sci_fake.clk_domain = clkdomain
333 self.aaci_fake.clk_domain = clkdomain
334 self.mmc_fake.clk_domain = clkdomain
335 self.rtc.clk_domain = clkdomain
336 self.flash_fake.clk_domain = clkdomain
|
| 337 self.energy_ctrl.clk_domain = clkdomain
|
334
335# Reference for memory map and interrupt number
336# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
337# Chapter 4: Programmer's Reference
338class RealViewEB(RealView):
339 uart = Pl011(pio_addr=0x10009000, int_num=44)
340 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
341 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
342 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
343 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
344 clcd = Pl111(pio_addr=0x10020000, int_num=23)
345 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
346 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
347
348 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
349 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
350 fake_mem=True)
351 dmac_fake = AmbaFake(pio_addr=0x10030000)
352 uart1_fake = AmbaFake(pio_addr=0x1000a000)
353 uart2_fake = AmbaFake(pio_addr=0x1000b000)
354 uart3_fake = AmbaFake(pio_addr=0x1000c000)
355 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
356 smc_fake = AmbaFake(pio_addr=0x100e1000)
357 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
358 watchdog_fake = AmbaFake(pio_addr=0x10010000)
359 gpio0_fake = AmbaFake(pio_addr=0x10013000)
360 gpio1_fake = AmbaFake(pio_addr=0x10014000)
361 gpio2_fake = AmbaFake(pio_addr=0x10015000)
362 ssp_fake = AmbaFake(pio_addr=0x1000d000)
363 sci_fake = AmbaFake(pio_addr=0x1000e000)
364 aaci_fake = AmbaFake(pio_addr=0x10004000)
365 mmc_fake = AmbaFake(pio_addr=0x10005000)
366 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
| 338
339# Reference for memory map and interrupt number
340# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
341# Chapter 4: Programmer's Reference
342class RealViewEB(RealView):
343 uart = Pl011(pio_addr=0x10009000, int_num=44)
344 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
345 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
346 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
347 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
348 clcd = Pl111(pio_addr=0x10020000, int_num=23)
349 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
350 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
351
352 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
353 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
354 fake_mem=True)
355 dmac_fake = AmbaFake(pio_addr=0x10030000)
356 uart1_fake = AmbaFake(pio_addr=0x1000a000)
357 uart2_fake = AmbaFake(pio_addr=0x1000b000)
358 uart3_fake = AmbaFake(pio_addr=0x1000c000)
359 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
360 smc_fake = AmbaFake(pio_addr=0x100e1000)
361 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
362 watchdog_fake = AmbaFake(pio_addr=0x10010000)
363 gpio0_fake = AmbaFake(pio_addr=0x10013000)
364 gpio1_fake = AmbaFake(pio_addr=0x10014000)
365 gpio2_fake = AmbaFake(pio_addr=0x10015000)
366 ssp_fake = AmbaFake(pio_addr=0x1000d000)
367 sci_fake = AmbaFake(pio_addr=0x1000e000)
368 aaci_fake = AmbaFake(pio_addr=0x10004000)
369 mmc_fake = AmbaFake(pio_addr=0x10005000)
370 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
|
| 371 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
|
367
| 372
|
368
369
| |
370 # Attach I/O devices that are on chip and also set the appropriate
371 # ranges for the bridge
372 def attachOnChipIO(self, bus, bridge):
373 self.gic.pio = bus.master
374 self.l2x0_fake.pio = bus.master
375 # Bridge ranges based on excluding what is part of on-chip I/O
376 # (gic, l2x0)
377 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
378 self.gic.cpu_addr - 1),
379 AddrRange(self.flash_fake.pio_addr, Addr.max)]
380
381 # Set the clock domain for IO objects that are considered
382 # to be "close" to the cores.
383 def onChipIOClkDomain(self, clkdomain):
384 self.gic.clk_domain = clkdomain
385 self.l2x0_fake.clk_domain = clkdomain
386
387 # Attach I/O devices to specified bus object. Can't do this
388 # earlier, since the bus object itself is typically defined at the
389 # System level.
390 def attachIO(self, bus):
391 self.uart.pio = bus.master
392 self.realview_io.pio = bus.master
393 self.timer0.pio = bus.master
394 self.timer1.pio = bus.master
395 self.clcd.pio = bus.master
396 self.clcd.dma = bus.slave
397 self.kmi0.pio = bus.master
398 self.kmi1.pio = bus.master
399 self.dmac_fake.pio = bus.master
400 self.uart1_fake.pio = bus.master
401 self.uart2_fake.pio = bus.master
402 self.uart3_fake.pio = bus.master
403 self.smc_fake.pio = bus.master
404 self.sp810_fake.pio = bus.master
405 self.watchdog_fake.pio = bus.master
406 self.gpio0_fake.pio = bus.master
407 self.gpio1_fake.pio = bus.master
408 self.gpio2_fake.pio = bus.master
409 self.ssp_fake.pio = bus.master
410 self.sci_fake.pio = bus.master
411 self.aaci_fake.pio = bus.master
412 self.mmc_fake.pio = bus.master
413 self.rtc_fake.pio = bus.master
414 self.flash_fake.pio = bus.master
415 self.smcreg_fake.pio = bus.master
| 373 # Attach I/O devices that are on chip and also set the appropriate
374 # ranges for the bridge
375 def attachOnChipIO(self, bus, bridge):
376 self.gic.pio = bus.master
377 self.l2x0_fake.pio = bus.master
378 # Bridge ranges based on excluding what is part of on-chip I/O
379 # (gic, l2x0)
380 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
381 self.gic.cpu_addr - 1),
382 AddrRange(self.flash_fake.pio_addr, Addr.max)]
383
384 # Set the clock domain for IO objects that are considered
385 # to be "close" to the cores.
386 def onChipIOClkDomain(self, clkdomain):
387 self.gic.clk_domain = clkdomain
388 self.l2x0_fake.clk_domain = clkdomain
389
390 # Attach I/O devices to specified bus object. Can't do this
391 # earlier, since the bus object itself is typically defined at the
392 # System level.
393 def attachIO(self, bus):
394 self.uart.pio = bus.master
395 self.realview_io.pio = bus.master
396 self.timer0.pio = bus.master
397 self.timer1.pio = bus.master
398 self.clcd.pio = bus.master
399 self.clcd.dma = bus.slave
400 self.kmi0.pio = bus.master
401 self.kmi1.pio = bus.master
402 self.dmac_fake.pio = bus.master
403 self.uart1_fake.pio = bus.master
404 self.uart2_fake.pio = bus.master
405 self.uart3_fake.pio = bus.master
406 self.smc_fake.pio = bus.master
407 self.sp810_fake.pio = bus.master
408 self.watchdog_fake.pio = bus.master
409 self.gpio0_fake.pio = bus.master
410 self.gpio1_fake.pio = bus.master
411 self.gpio2_fake.pio = bus.master
412 self.ssp_fake.pio = bus.master
413 self.sci_fake.pio = bus.master
414 self.aaci_fake.pio = bus.master
415 self.mmc_fake.pio = bus.master
416 self.rtc_fake.pio = bus.master
417 self.flash_fake.pio = bus.master
418 self.smcreg_fake.pio = bus.master
|
| 419 self.energy_ctrl.pio = bus.master
|
416
417 # Set the clock domain for IO objects that are considered
418 # to be "far" away from the cores.
419 def offChipIOClkDomain(self, clkdomain):
420 self.uart.clk_domain = clkdomain
421 self.realview_io.clk_domain = clkdomain
422 self.timer0.clk_domain = clkdomain
423 self.timer1.clk_domain = clkdomain
424 self.clcd.clk_domain = clkdomain
425 self.kmi0.clk_domain = clkdomain
426 self.kmi1.clk_domain = clkdomain
427 self.dmac_fake.clk_domain = clkdomain
428 self.uart1_fake.clk_domain = clkdomain
429 self.uart2_fake.clk_domain = clkdomain
430 self.uart3_fake.clk_domain = clkdomain
431 self.smc_fake.clk_domain = clkdomain
432 self.sp810_fake.clk_domain = clkdomain
433 self.watchdog_fake.clk_domain = clkdomain
434 self.gpio0_fake.clk_domain = clkdomain
435 self.gpio1_fake.clk_domain = clkdomain
436 self.gpio2_fake.clk_domain = clkdomain
437 self.ssp_fake.clk_domain = clkdomain
438 self.sci_fake.clk_domain = clkdomain
439 self.aaci_fake.clk_domain = clkdomain
440 self.mmc_fake.clk_domain = clkdomain
441 self.rtc.clk_domain = clkdomain
442 self.flash_fake.clk_domain = clkdomain
443 self.smcreg_fake.clk_domain = clkdomain
| 420
421 # Set the clock domain for IO objects that are considered
422 # to be "far" away from the cores.
423 def offChipIOClkDomain(self, clkdomain):
424 self.uart.clk_domain = clkdomain
425 self.realview_io.clk_domain = clkdomain
426 self.timer0.clk_domain = clkdomain
427 self.timer1.clk_domain = clkdomain
428 self.clcd.clk_domain = clkdomain
429 self.kmi0.clk_domain = clkdomain
430 self.kmi1.clk_domain = clkdomain
431 self.dmac_fake.clk_domain = clkdomain
432 self.uart1_fake.clk_domain = clkdomain
433 self.uart2_fake.clk_domain = clkdomain
434 self.uart3_fake.clk_domain = clkdomain
435 self.smc_fake.clk_domain = clkdomain
436 self.sp810_fake.clk_domain = clkdomain
437 self.watchdog_fake.clk_domain = clkdomain
438 self.gpio0_fake.clk_domain = clkdomain
439 self.gpio1_fake.clk_domain = clkdomain
440 self.gpio2_fake.clk_domain = clkdomain
441 self.ssp_fake.clk_domain = clkdomain
442 self.sci_fake.clk_domain = clkdomain
443 self.aaci_fake.clk_domain = clkdomain
444 self.mmc_fake.clk_domain = clkdomain
445 self.rtc.clk_domain = clkdomain
446 self.flash_fake.clk_domain = clkdomain
447 self.smcreg_fake.clk_domain = clkdomain
|
| 448 self.energy_ctrl.clk_domain = clkdomain
|
444
445class VExpress_EMM(RealView):
446 _mem_regions = [(Addr('2GB'), Addr('2GB'))]
447 pci_cfg_base = 0x30000000
448 uart = Pl011(pio_addr=0x1c090000, int_num=37)
449 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \
450 idreg=0x02250000, pio_addr=0x1C010000)
451 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
452 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000)
453 generic_timer = GenericTimer(int_num=29)
454 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
455 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
456 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
457 hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117)
458 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
459 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
460 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
461 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
462 io_shift = 2, ctrl_offset = 2, Command = 0x1,
463 BAR0 = 0x1C1A0000, BAR0Size = '256B',
464 BAR1 = 0x1C1A0100, BAR1Size = '4096B',
465 BAR0LegacyIO = True, BAR1LegacyIO = True)
466
467 pciconfig = PciConfigAll(size='256MB')
468 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
469 conf_table_reported = False)
470 rtc = PL031(pio_addr=0x1C170000, int_num=36)
471
472 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
473 uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
474 uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
475 uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
476 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
477 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
478 aaci_fake = AmbaFake(pio_addr=0x1C040000)
479 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
480 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
481 mmc_fake = AmbaFake(pio_addr=0x1c050000)
| 449
450class VExpress_EMM(RealView):
451 _mem_regions = [(Addr('2GB'), Addr('2GB'))]
452 pci_cfg_base = 0x30000000
453 uart = Pl011(pio_addr=0x1c090000, int_num=37)
454 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \
455 idreg=0x02250000, pio_addr=0x1C010000)
456 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
457 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000)
458 generic_timer = GenericTimer(int_num=29)
459 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
460 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
461 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
462 hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117)
463 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
464 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
465 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
466 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
467 io_shift = 2, ctrl_offset = 2, Command = 0x1,
468 BAR0 = 0x1C1A0000, BAR0Size = '256B',
469 BAR1 = 0x1C1A0100, BAR1Size = '4096B',
470 BAR0LegacyIO = True, BAR1LegacyIO = True)
471
472 pciconfig = PciConfigAll(size='256MB')
473 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
474 conf_table_reported = False)
475 rtc = PL031(pio_addr=0x1C170000, int_num=36)
476
477 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
478 uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
479 uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
480 uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
481 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
482 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
483 aaci_fake = AmbaFake(pio_addr=0x1C040000)
484 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
485 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
486 mmc_fake = AmbaFake(pio_addr=0x1c050000)
|
| 487 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000)
|
482
483 # Attach any PCI devices that are supported
484 def attachPciDevices(self):
485 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
486 InterruptLine=1, InterruptPin=1)
487 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
488 InterruptLine=2, InterruptPin=2)
489
490 def enableMSIX(self):
491 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
492 self.gicv2m = Gicv2m()
493 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
494
495 def setupBootLoader(self, mem_bus, cur_sys, loc):
496 self.nvmem = SimpleMemory(range = AddrRange('64MB'),
497 conf_table_reported = False)
498 self.nvmem.port = mem_bus.master
499 cur_sys.boot_loader = loc('boot_emm.arm')
500 cur_sys.atags_addr = 0x8000000
501 cur_sys.load_addr_mask = 0xfffffff
502 cur_sys.load_offset = 0x80000000
503
504 # Attach I/O devices that are on chip and also set the appropriate
505 # ranges for the bridge
506 def attachOnChipIO(self, bus, bridge):
507 self.gic.pio = bus.master
508 self.local_cpu_timer.pio = bus.master
509 if hasattr(self, "gicv2m"):
510 self.gicv2m.pio = bus.master
511 self.hdlcd.dma = bus.slave
512 # Bridge ranges based on excluding what is part of on-chip I/O
513 # (gic, a9scu)
514 bridge.ranges = [AddrRange(0x2F000000, size='16MB'),
515 AddrRange(0x2B000000, size='4MB'),
516 AddrRange(0x30000000, size='256MB'),
517 AddrRange(0x40000000, size='512MB'),
518 AddrRange(0x18000000, size='64MB'),
519 AddrRange(0x1C000000, size='64MB')]
520 self.vgic.pio = bus.master
521
522
523 # Set the clock domain for IO objects that are considered
524 # to be "close" to the cores.
525 def onChipIOClkDomain(self, clkdomain):
526 self.gic.clk_domain = clkdomain
527 if hasattr(self, "gicv2m"):
528 self.gicv2m.clk_domain = clkdomain
529 self.hdlcd.clk_domain = clkdomain
530 self.vgic.clk_domain = clkdomain
531
532 # Attach I/O devices to specified bus object. Done here
533 # as the specified bus to connect to may not always be fixed.
534 def attachIO(self, bus):
535 self.uart.pio = bus.master
536 self.realview_io.pio = bus.master
537 self.timer0.pio = bus.master
538 self.timer1.pio = bus.master
539 self.clcd.pio = bus.master
540 self.clcd.dma = bus.slave
541 self.hdlcd.pio = bus.master
542 self.kmi0.pio = bus.master
543 self.kmi1.pio = bus.master
544 self.cf_ctrl.pio = bus.master
545 self.cf_ctrl.dma = bus.slave
546 self.cf_ctrl.config = bus.master
547 self.rtc.pio = bus.master
548 bus.use_default_range = True
549 self.vram.port = bus.master
550 self.pciconfig.pio = bus.default
551
552 self.l2x0_fake.pio = bus.master
553 self.uart1_fake.pio = bus.master
554 self.uart2_fake.pio = bus.master
555 self.uart3_fake.pio = bus.master
556 self.sp810_fake.pio = bus.master
557 self.watchdog_fake.pio = bus.master
558 self.aaci_fake.pio = bus.master
559 self.lan_fake.pio = bus.master
560 self.usb_fake.pio = bus.master
561 self.mmc_fake.pio = bus.master
| 488
489 # Attach any PCI devices that are supported
490 def attachPciDevices(self):
491 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
492 InterruptLine=1, InterruptPin=1)
493 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
494 InterruptLine=2, InterruptPin=2)
495
496 def enableMSIX(self):
497 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
498 self.gicv2m = Gicv2m()
499 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
500
501 def setupBootLoader(self, mem_bus, cur_sys, loc):
502 self.nvmem = SimpleMemory(range = AddrRange('64MB'),
503 conf_table_reported = False)
504 self.nvmem.port = mem_bus.master
505 cur_sys.boot_loader = loc('boot_emm.arm')
506 cur_sys.atags_addr = 0x8000000
507 cur_sys.load_addr_mask = 0xfffffff
508 cur_sys.load_offset = 0x80000000
509
510 # Attach I/O devices that are on chip and also set the appropriate
511 # ranges for the bridge
512 def attachOnChipIO(self, bus, bridge):
513 self.gic.pio = bus.master
514 self.local_cpu_timer.pio = bus.master
515 if hasattr(self, "gicv2m"):
516 self.gicv2m.pio = bus.master
517 self.hdlcd.dma = bus.slave
518 # Bridge ranges based on excluding what is part of on-chip I/O
519 # (gic, a9scu)
520 bridge.ranges = [AddrRange(0x2F000000, size='16MB'),
521 AddrRange(0x2B000000, size='4MB'),
522 AddrRange(0x30000000, size='256MB'),
523 AddrRange(0x40000000, size='512MB'),
524 AddrRange(0x18000000, size='64MB'),
525 AddrRange(0x1C000000, size='64MB')]
526 self.vgic.pio = bus.master
527
528
529 # Set the clock domain for IO objects that are considered
530 # to be "close" to the cores.
531 def onChipIOClkDomain(self, clkdomain):
532 self.gic.clk_domain = clkdomain
533 if hasattr(self, "gicv2m"):
534 self.gicv2m.clk_domain = clkdomain
535 self.hdlcd.clk_domain = clkdomain
536 self.vgic.clk_domain = clkdomain
537
538 # Attach I/O devices to specified bus object. Done here
539 # as the specified bus to connect to may not always be fixed.
540 def attachIO(self, bus):
541 self.uart.pio = bus.master
542 self.realview_io.pio = bus.master
543 self.timer0.pio = bus.master
544 self.timer1.pio = bus.master
545 self.clcd.pio = bus.master
546 self.clcd.dma = bus.slave
547 self.hdlcd.pio = bus.master
548 self.kmi0.pio = bus.master
549 self.kmi1.pio = bus.master
550 self.cf_ctrl.pio = bus.master
551 self.cf_ctrl.dma = bus.slave
552 self.cf_ctrl.config = bus.master
553 self.rtc.pio = bus.master
554 bus.use_default_range = True
555 self.vram.port = bus.master
556 self.pciconfig.pio = bus.default
557
558 self.l2x0_fake.pio = bus.master
559 self.uart1_fake.pio = bus.master
560 self.uart2_fake.pio = bus.master
561 self.uart3_fake.pio = bus.master
562 self.sp810_fake.pio = bus.master
563 self.watchdog_fake.pio = bus.master
564 self.aaci_fake.pio = bus.master
565 self.lan_fake.pio = bus.master
566 self.usb_fake.pio = bus.master
567 self.mmc_fake.pio = bus.master
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| 568 self.energy_ctrl.pio = bus.master
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562
563 # Try to attach the I/O if it exists
564 try:
565 self.ide.pio = bus.master
566 self.ide.config = bus.master
567 self.ide.dma = bus.slave
568 self.ethernet.pio = bus.master
569 self.ethernet.config = bus.master
570 self.ethernet.dma = bus.slave
571 except:
572 pass
573
574 # Set the clock domain for IO objects that are considered
575 # to be "far" away from the cores.
576 def offChipIOClkDomain(self, clkdomain):
577 self.uart.clk_domain = clkdomain
578 self.realview_io.clk_domain = clkdomain
579 self.timer0.clk_domain = clkdomain
580 self.timer1.clk_domain = clkdomain
581 self.clcd.clk_domain = clkdomain
582 self.kmi0.clk_domain = clkdomain
583 self.kmi1.clk_domain = clkdomain
584 self.cf_ctrl.clk_domain = clkdomain
585 self.rtc.clk_domain = clkdomain
586 self.vram.clk_domain = clkdomain
587 self.pciconfig.clk_domain = clkdomain
588
589 self.l2x0_fake.clk_domain = clkdomain
590 self.uart1_fake.clk_domain = clkdomain
591 self.uart2_fake.clk_domain = clkdomain
592 self.uart3_fake.clk_domain = clkdomain
593 self.sp810_fake.clk_domain = clkdomain
594 self.watchdog_fake.clk_domain = clkdomain
595 self.aaci_fake.clk_domain = clkdomain
596 self.lan_fake.clk_domain = clkdomain
597 self.usb_fake.clk_domain = clkdomain
598 self.mmc_fake.clk_domain = clkdomain
| 569
570 # Try to attach the I/O if it exists
571 try:
572 self.ide.pio = bus.master
573 self.ide.config = bus.master
574 self.ide.dma = bus.slave
575 self.ethernet.pio = bus.master
576 self.ethernet.config = bus.master
577 self.ethernet.dma = bus.slave
578 except:
579 pass
580
581 # Set the clock domain for IO objects that are considered
582 # to be "far" away from the cores.
583 def offChipIOClkDomain(self, clkdomain):
584 self.uart.clk_domain = clkdomain
585 self.realview_io.clk_domain = clkdomain
586 self.timer0.clk_domain = clkdomain
587 self.timer1.clk_domain = clkdomain
588 self.clcd.clk_domain = clkdomain
589 self.kmi0.clk_domain = clkdomain
590 self.kmi1.clk_domain = clkdomain
591 self.cf_ctrl.clk_domain = clkdomain
592 self.rtc.clk_domain = clkdomain
593 self.vram.clk_domain = clkdomain
594 self.pciconfig.clk_domain = clkdomain
595
596 self.l2x0_fake.clk_domain = clkdomain
597 self.uart1_fake.clk_domain = clkdomain
598 self.uart2_fake.clk_domain = clkdomain
599 self.uart3_fake.clk_domain = clkdomain
600 self.sp810_fake.clk_domain = clkdomain
601 self.watchdog_fake.clk_domain = clkdomain
602 self.aaci_fake.clk_domain = clkdomain
603 self.lan_fake.clk_domain = clkdomain
604 self.usb_fake.clk_domain = clkdomain
605 self.mmc_fake.clk_domain = clkdomain
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| 606 self.energy_ctrl.clk_domain = clkdomain
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599
600class VExpress_EMM64(VExpress_EMM):
601 pci_io_base = 0x2f000000
602 pci_cfg_gen_offsets = True
603 # Three memory regions are specified totalling 512GB
604 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
605 (Addr('512GB'), Addr('480GB'))]
606 def setupBootLoader(self, mem_bus, cur_sys, loc):
607 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
608 self.nvmem.port = mem_bus.master
609 cur_sys.boot_loader = loc('boot_emm.arm64')
610 cur_sys.atags_addr = 0x8000000
611 cur_sys.load_addr_mask = 0xfffffff
612 cur_sys.load_offset = 0x80000000
613
614
| 607
608class VExpress_EMM64(VExpress_EMM):
609 pci_io_base = 0x2f000000
610 pci_cfg_gen_offsets = True
611 # Three memory regions are specified totalling 512GB
612 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
613 (Addr('512GB'), Addr('480GB'))]
614 def setupBootLoader(self, mem_bus, cur_sys, loc):
615 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
616 self.nvmem.port = mem_bus.master
617 cur_sys.boot_loader = loc('boot_emm.arm64')
618 cur_sys.atags_addr = 0x8000000
619 cur_sys.load_addr_mask = 0xfffffff
620 cur_sys.load_offset = 0x80000000
621
622
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