RealView.py (13505:e699fce12780) | RealView.py (13532:b1cacf73cd4e) |
---|---|
1# Copyright (c) 2009-2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 839 unchanged lines hidden (view full) --- 848 conf_table_reported=False) 849 if mem_bus is not None: 850 cur_sys.bootmem.port = mem_bus.master 851 if not cur_sys.boot_loader: 852 cur_sys.boot_loader = loc('boot_emm.arm64') 853 cur_sys.atags_addr = 0x8000000 854 cur_sys.load_offset = 0x80000000 855 | 1# Copyright (c) 2009-2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 839 unchanged lines hidden (view full) --- 848 conf_table_reported=False) 849 if mem_bus is not None: 850 cur_sys.bootmem.port = mem_bus.master 851 if not cur_sys.boot_loader: 852 cur_sys.boot_loader = loc('boot_emm.arm64') 853 cur_sys.atags_addr = 0x8000000 854 cur_sys.load_offset = 0x80000000 855 |
856class VExpress_GEM5_V1_Base(RealView): | 856class VExpress_GEM5_Base(RealView): |
857 """ 858The VExpress gem5 memory map is loosely based on a modified 859Versatile Express RS1 memory map. 860 861The gem5 platform has been designed to implement a subset of the 862original Versatile Express RS1 memory map. Off-chip peripherals should, 863when possible, adhere to the Versatile Express memory map. Non-PCI 864off-chip devices that are gem5-specific should live in the CS5 memory --- 97 unchanged lines hidden (view full) --- 962 963 # Platform control device (off-chip) 964 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 965 idreg=0x02250000, pio_addr=0x1c010000) 966 mcc = VExpressMCC() 967 dcc = CoreTile2A15DCC() 968 969 ### On-chip devices ### | 857 """ 858The VExpress gem5 memory map is loosely based on a modified 859Versatile Express RS1 memory map. 860 861The gem5 platform has been designed to implement a subset of the 862original Versatile Express RS1 memory map. Off-chip peripherals should, 863when possible, adhere to the Versatile Express memory map. Non-PCI 864off-chip devices that are gem5-specific should live in the CS5 memory --- 97 unchanged lines hidden (view full) --- 962 963 # Platform control device (off-chip) 964 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 965 idreg=0x02250000, pio_addr=0x1c010000) 966 mcc = VExpressMCC() 967 dcc = CoreTile2A15DCC() 968 969 ### On-chip devices ### |
970 gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000, 971 it_lines=512) 972 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 973 gicv2m = Gicv2m() 974 gicv2m.frames = [ 975 Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000), 976 ] 977 | |
978 generic_timer = GenericTimer(int_phys_s=ArmPPI(num=29), 979 int_phys_ns=ArmPPI(num=30), 980 int_virt=ArmPPI(num=27), 981 int_hyp=ArmPPI(num=26)) 982 983 def _on_chip_devices(self): 984 return [ | 970 generic_timer = GenericTimer(int_phys_s=ArmPPI(num=29), 971 int_phys_ns=ArmPPI(num=30), 972 int_virt=ArmPPI(num=27), 973 int_hyp=ArmPPI(num=26)) 974 975 def _on_chip_devices(self): 976 return [ |
985 self.gic, self.vgic, self.gicv2m, | |
986 self.generic_timer, 987 ] 988 989 ### Off-chip devices ### 990 clock24MHz = SrcClockDomain(clock="24MHz", 991 voltage_domain=VoltageDomain(voltage="3.3V")) 992 993 uart = [ --- 50 unchanged lines hidden (view full) --- 1044 1045 # Setup m5ops. It's technically not a part of the boot 1046 # loader, but this is the only place we can configure the 1047 # system. 1048 cur_sys.m5ops_base = 0x10010000 1049 1050 def generateDeviceTree(self, state): 1051 # Generate using standard RealView function | 977 self.generic_timer, 978 ] 979 980 ### Off-chip devices ### 981 clock24MHz = SrcClockDomain(clock="24MHz", 982 voltage_domain=VoltageDomain(voltage="3.3V")) 983 984 uart = [ --- 50 unchanged lines hidden (view full) --- 1035 1036 # Setup m5ops. It's technically not a part of the boot 1037 # loader, but this is the only place we can configure the 1038 # system. 1039 cur_sys.m5ops_base = 0x10010000 1040 1041 def generateDeviceTree(self, state): 1042 # Generate using standard RealView function |
1052 dt = list(super(VExpress_GEM5_V1_Base, self).generateDeviceTree(state)) | 1043 dt = list(super(VExpress_GEM5_Base, self).generateDeviceTree(state)) |
1053 if len(dt) > 1: 1054 raise Exception("System returned too many DT nodes") 1055 node = dt[0] 1056 1057 node.appendCompatible(["arm,vexpress"]) 1058 node.append(FdtPropertyStrings("model", ["V2P-CA15"])) 1059 node.append(FdtPropertyWords("arm,hbi", [0x0])) 1060 node.append(FdtPropertyWords("arm,vexpress,site", [0xf])) 1061 1062 yield node 1063 | 1044 if len(dt) > 1: 1045 raise Exception("System returned too many DT nodes") 1046 node = dt[0] 1047 1048 node.appendCompatible(["arm,vexpress"]) 1049 node.append(FdtPropertyStrings("model", ["V2P-CA15"])) 1050 node.append(FdtPropertyWords("arm,hbi", [0x0])) 1051 node.append(FdtPropertyWords("arm,vexpress,site", [0xf])) 1052 1053 yield node 1054 |
1055class VExpress_GEM5_V1_Base(VExpress_GEM5_Base): 1056 gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000, 1057 it_lines=512) 1058 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 1059 gicv2m = Gicv2m() 1060 gicv2m.frames = [ 1061 Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000), 1062 ] |
|
1064 | 1063 |
1064 def _on_chip_devices(self): 1065 return super(VExpress_GEM5_V1_Base,self)._on_chip_devices() + [ 1066 self.gic, self.vgic, self.gicv2m, 1067 ] 1068 |
|
1065class VExpress_GEM5_V1(VExpress_GEM5_V1_Base): 1066 hdlcd = HDLcd(pxl_clk=VExpress_GEM5_V1_Base.dcc.osc_pxl, 1067 pio_addr=0x2b000000, int_num=95) 1068 1069 def _on_chip_devices(self): 1070 return super(VExpress_GEM5_V1,self)._on_chip_devices() + [ 1071 self.hdlcd, 1072 ] | 1069class VExpress_GEM5_V1(VExpress_GEM5_V1_Base): 1070 hdlcd = HDLcd(pxl_clk=VExpress_GEM5_V1_Base.dcc.osc_pxl, 1071 pio_addr=0x2b000000, int_num=95) 1072 1073 def _on_chip_devices(self): 1074 return super(VExpress_GEM5_V1,self)._on_chip_devices() + [ 1075 self.hdlcd, 1076 ] |
1077 1078class VExpress_GEM5_V2_Base(VExpress_GEM5_Base): 1079 gic = Gicv3() 1080 1081 def _on_chip_devices(self): 1082 return super(VExpress_GEM5_V2_Base,self)._on_chip_devices() + [ 1083 self.gic, 1084 ] 1085 1086 def setupBootLoader(self, mem_bus, cur_sys, loc): 1087 cur_sys.boot_loader = [ loc('boot_emm_v2.arm64') ] 1088 super(VExpress_GEM5_V2_Base,self).setupBootLoader(mem_bus, 1089 cur_sys, loc) 1090 1091class VExpress_GEM5_V2(VExpress_GEM5_V2_Base): 1092 hdlcd = HDLcd(pxl_clk=VExpress_GEM5_V2_Base.dcc.osc_pxl, 1093 pio_addr=0x2b000000, int_num=95) 1094 1095 def _on_chip_devices(self): 1096 return super(VExpress_GEM5_V2,self)._on_chip_devices() + [ 1097 self.hdlcd, 1098 ] |
|