RealView.py (12474:31aaa43d1401) | RealView.py (12598:b80b2d9a251b) |
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1# Copyright (c) 2009-2017 ARM Limited | 1# Copyright (c) 2009-2018 ARM Limited |
2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 565 unchanged lines hidden (view full) --- 575 self._attach_io(self._on_chip_devices(), bus, *args, **kwargs) 576 if bridge: 577 bridge.ranges = self._off_chip_ranges 578 579 def attachIO(self, *args, **kwargs): 580 self._attach_io(self._off_chip_devices(), *args, **kwargs) 581 582 def setupBootLoader(self, mem_bus, cur_sys, loc): | 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 565 unchanged lines hidden (view full) --- 575 self._attach_io(self._on_chip_devices(), bus, *args, **kwargs) 576 if bridge: 577 bridge.ranges = self._off_chip_ranges 578 579 def attachIO(self, *args, **kwargs): 580 self._attach_io(self._off_chip_devices(), *args, **kwargs) 581 582 def setupBootLoader(self, mem_bus, cur_sys, loc): |
583 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 584 conf_table_reported = False) 585 self.nvmem.port = mem_bus.master | 583 cur_sys.bootmem = SimpleMemory( 584 range = AddrRange('2GB', size = '64MB'), 585 conf_table_reported = False) 586 if mem_bus is not None: 587 cur_sys.bootmem.port = mem_bus.master |
586 cur_sys.boot_loader = loc('boot.arm') 587 cur_sys.atags_addr = 0x100 588 cur_sys.load_offset = 0 589 590 def generateDeviceTree(self, state): 591 node = FdtNode("/") # Things in this module need to end up in the root 592 node.append(FdtPropertyWords("interrupt-parent", 593 state.phandle(self.gic))) --- 372 unchanged lines hidden (view full) --- 966 InterruptLine=2, InterruptPin=2) 967 968 def enableMSIX(self): 969 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 970 self.gicv2m = Gicv2m() 971 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 972 973 def setupBootLoader(self, mem_bus, cur_sys, loc): | 588 cur_sys.boot_loader = loc('boot.arm') 589 cur_sys.atags_addr = 0x100 590 cur_sys.load_offset = 0 591 592 def generateDeviceTree(self, state): 593 node = FdtNode("/") # Things in this module need to end up in the root 594 node.append(FdtPropertyWords("interrupt-parent", 595 state.phandle(self.gic))) --- 372 unchanged lines hidden (view full) --- 968 InterruptLine=2, InterruptPin=2) 969 970 def enableMSIX(self): 971 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 972 self.gicv2m = Gicv2m() 973 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 974 975 def setupBootLoader(self, mem_bus, cur_sys, loc): |
974 self.nvmem = SimpleMemory(range = AddrRange('64MB'), 975 conf_table_reported = False) 976 self.nvmem.port = mem_bus.master | 976 cur_sys.bootmem = SimpleMemory(range = AddrRange('64MB'), 977 conf_table_reported = False) 978 if mem_bus is not None: 979 cur_sys.bootmem.port = mem_bus.master |
977 if not cur_sys.boot_loader: 978 cur_sys.boot_loader = loc('boot_emm.arm') 979 cur_sys.atags_addr = 0x8000000 980 cur_sys.load_offset = 0x80000000 981 982class VExpress_EMM64(VExpress_EMM): 983 # Three memory regions are specified totalling 512GB 984 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 985 (Addr('512GB'), Addr('480GB'))] 986 pci_host = GenericPciHost( 987 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 988 pci_pio_base=0x2f000000) 989 990 def setupBootLoader(self, mem_bus, cur_sys, loc): | 980 if not cur_sys.boot_loader: 981 cur_sys.boot_loader = loc('boot_emm.arm') 982 cur_sys.atags_addr = 0x8000000 983 cur_sys.load_offset = 0x80000000 984 985class VExpress_EMM64(VExpress_EMM): 986 # Three memory regions are specified totalling 512GB 987 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 988 (Addr('512GB'), Addr('480GB'))] 989 pci_host = GenericPciHost( 990 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 991 pci_pio_base=0x2f000000) 992 993 def setupBootLoader(self, mem_bus, cur_sys, loc): |
991 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'), 992 conf_table_reported=False) 993 self.nvmem.port = mem_bus.master | 994 cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'), 995 conf_table_reported=False) 996 if mem_bus is not None: 997 cur_sys.bootmem.port = mem_bus.master |
994 if not cur_sys.boot_loader: 995 cur_sys.boot_loader = loc('boot_emm.arm64') 996 cur_sys.atags_addr = 0x8000000 997 cur_sys.load_offset = 0x80000000 998 | 998 if not cur_sys.boot_loader: 999 cur_sys.boot_loader = loc('boot_emm.arm64') 1000 cur_sys.atags_addr = 0x8000000 1001 cur_sys.load_offset = 0x80000000 1002 |
999 | |
1000class VExpress_GEM5_V1(RealView): 1001 """ 1002The VExpress gem5 memory map is loosely based on a modified 1003Versatile Express RS1 memory map. 1004 1005The gem5 platform has been designed to implement a subset of the 1006original Versatile Express RS1 memory map. Off-chip peripherals should, 1007when possible, adhere to the Versatile Express memory map. Non-PCI --- 151 unchanged lines hidden (view full) --- 1159 self.clock24MHz, 1160 ] 1161 1162 def attachPciDevice(self, device, *args, **kwargs): 1163 device.host = self.pci_host 1164 self._attach_device(device, *args, **kwargs) 1165 1166 def setupBootLoader(self, mem_bus, cur_sys, loc): | 1003class VExpress_GEM5_V1(RealView): 1004 """ 1005The VExpress gem5 memory map is loosely based on a modified 1006Versatile Express RS1 memory map. 1007 1008The gem5 platform has been designed to implement a subset of the 1009original Versatile Express RS1 memory map. Off-chip peripherals should, 1010when possible, adhere to the Versatile Express memory map. Non-PCI --- 151 unchanged lines hidden (view full) --- 1162 self.clock24MHz, 1163 ] 1164 1165 def attachPciDevice(self, device, *args, **kwargs): 1166 device.host = self.pci_host 1167 self._attach_device(device, *args, **kwargs) 1168 1169 def setupBootLoader(self, mem_bus, cur_sys, loc): |
1167 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'), 1168 conf_table_reported=False) 1169 self.nvmem.port = mem_bus.master | 1170 cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'), 1171 conf_table_reported=False) 1172 if mem_bus is not None: 1173 cur_sys.bootmem.port = mem_bus.master |
1170 if not cur_sys.boot_loader: 1171 cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ] 1172 cur_sys.atags_addr = 0x8000000 1173 cur_sys.load_offset = 0x80000000 1174 1175 # Setup m5ops. It's technically not a part of the boot 1176 # loader, but this is the only place we can configure the 1177 # system. --- 15 unchanged lines hidden --- | 1174 if not cur_sys.boot_loader: 1175 cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ] 1176 cur_sys.atags_addr = 0x8000000 1177 cur_sys.load_offset = 0x80000000 1178 1179 # Setup m5ops. It's technically not a part of the boot 1180 # loader, but this is the only place we can configure the 1181 # system. --- 15 unchanged lines hidden --- |