RealView.py (12059:bf8ec28e7a76) | RealView.py (12069:6554872926ec) |
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1# Copyright (c) 2009-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 331 unchanged lines hidden (view full) --- 340 pass 341 342 def onChipIOClkDomain(self, clkdomain): 343 self._attach_clk(self._on_chip_devices(), clkdomain) 344 345 def offChipIOClkDomain(self, clkdomain): 346 self._attach_clk(self._off_chip_devices(), clkdomain) 347 | 1# Copyright (c) 2009-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 331 unchanged lines hidden (view full) --- 340 pass 341 342 def onChipIOClkDomain(self, clkdomain): 343 self._attach_clk(self._on_chip_devices(), clkdomain) 344 345 def offChipIOClkDomain(self, clkdomain): 346 self._attach_clk(self._off_chip_devices(), clkdomain) 347 |
348 def attachOnChipIO(self, bus, bridge=None, **kwargs): 349 self._attach_io(self._on_chip_devices(), bus, **kwargs) | 348 def attachOnChipIO(self, bus, bridge=None, *args, **kwargs): 349 self._attach_io(self._on_chip_devices(), bus, *args, **kwargs) |
350 if bridge: 351 bridge.ranges = self._off_chip_ranges 352 353 def attachIO(self, *args, **kwargs): 354 self._attach_io(self._off_chip_devices(), *args, **kwargs) 355 | 350 if bridge: 351 bridge.ranges = self._off_chip_ranges 352 353 def attachIO(self, *args, **kwargs): 354 self._attach_io(self._off_chip_devices(), *args, **kwargs) 355 |
356 | |
357 def setupBootLoader(self, mem_bus, cur_sys, loc): 358 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 359 conf_table_reported = False) 360 self.nvmem.port = mem_bus.master 361 cur_sys.boot_loader = loc('boot.arm') 362 cur_sys.atags_addr = 0x100 363 cur_sys.load_addr_mask = 0xfffffff 364 cur_sys.load_offset = 0 --- 242 unchanged lines hidden (view full) --- 607 self.mmc_fake.clk_domain = clkdomain 608 self.rtc.clk_domain = clkdomain 609 self.flash_fake.clk_domain = clkdomain 610 self.smcreg_fake.clk_domain = clkdomain 611 self.energy_ctrl.clk_domain = clkdomain 612 613class VExpress_EMM(RealView): 614 _mem_regions = [(Addr('2GB'), Addr('2GB'))] | 356 def setupBootLoader(self, mem_bus, cur_sys, loc): 357 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 358 conf_table_reported = False) 359 self.nvmem.port = mem_bus.master 360 cur_sys.boot_loader = loc('boot.arm') 361 cur_sys.atags_addr = 0x100 362 cur_sys.load_addr_mask = 0xfffffff 363 cur_sys.load_offset = 0 --- 242 unchanged lines hidden (view full) --- 606 self.mmc_fake.clk_domain = clkdomain 607 self.rtc.clk_domain = clkdomain 608 self.flash_fake.clk_domain = clkdomain 609 self.smcreg_fake.clk_domain = clkdomain 610 self.energy_ctrl.clk_domain = clkdomain 611 612class VExpress_EMM(RealView): 613 _mem_regions = [(Addr('2GB'), Addr('2GB'))] |
615 uart = Pl011(pio_addr=0x1c090000, int_num=37) 616 realview_io = RealViewCtrl( 617 proc_id0=0x14000000, proc_id1=0x14000000, 618 idreg=0x02250000, pio_addr=0x1C010000) | 614 615 # Ranges based on excluding what is part of on-chip I/O (gic, 616 # a9scu) 617 _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'), 618 AddrRange(0x30000000, size='256MB'), 619 AddrRange(0x40000000, size='512MB'), 620 AddrRange(0x18000000, size='64MB'), 621 AddrRange(0x1C000000, size='64MB')] 622 623 # Platform control device (off-chip) 624 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 625 idreg=0x02250000, pio_addr=0x1C010000) 626 |
619 mcc = VExpressMCC() 620 dcc = CoreTile2A15DCC() | 627 mcc = VExpressMCC() 628 dcc = CoreTile2A15DCC() |
629 630 ### On-chip devices ### |
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621 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) | 631 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) |
632 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 633 634 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, 635 pio_addr=0x2C080000) 636 637 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 638 pio_addr=0x2b000000, int_num=117, 639 workaround_swap_rb=True) 640 641 def _on_chip_devices(self): 642 devices = [ 643 self.gic, self.vgic, 644 self.local_cpu_timer 645 ] 646 if hasattr(self, "gicv2m"): 647 devices.append(self.gicv2m) 648 devices.append(self.hdlcd) 649 return devices 650 651 ### Off-chip devices ### 652 uart = Pl011(pio_addr=0x1c090000, int_num=37) |
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622 pci_host = GenericPciHost( 623 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 624 pci_pio_base=0) | 653 pci_host = GenericPciHost( 654 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 655 pci_pio_base=0) |
625 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) | 656 |
626 generic_timer = GenericTimer(int_phys=29, int_virt=27) 627 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 628 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 629 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) | 657 generic_timer = GenericTimer(int_phys=29, int_virt=27) 658 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 659 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 660 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) |
630 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 631 pio_addr=0x2b000000, int_num=117, 632 workaround_swap_rb=True) | |
633 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 634 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) | 661 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 662 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) |
635 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) | |
636 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 637 io_shift = 2, ctrl_offset = 2, Command = 0x1, 638 BAR0 = 0x1C1A0000, BAR0Size = '256B', 639 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 640 BAR0LegacyIO = True, BAR1LegacyIO = True) 641 642 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 643 conf_table_reported = False) --- 6 unchanged lines hidden (view full) --- 650 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 651 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 652 aaci_fake = AmbaFake(pio_addr=0x1C040000) 653 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 654 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 655 mmc_fake = AmbaFake(pio_addr=0x1c050000) 656 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 657 | 663 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 664 io_shift = 2, ctrl_offset = 2, Command = 0x1, 665 BAR0 = 0x1C1A0000, BAR0Size = '256B', 666 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 667 BAR0LegacyIO = True, BAR1LegacyIO = True) 668 669 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 670 conf_table_reported = False) --- 6 unchanged lines hidden (view full) --- 677 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 678 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 679 aaci_fake = AmbaFake(pio_addr=0x1C040000) 680 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 681 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 682 mmc_fake = AmbaFake(pio_addr=0x1c050000) 683 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 684 |
685 def _off_chip_devices(self): 686 devices = [ 687 self.uart, 688 self.realview_io, 689 self.pci_host, 690 self.timer0, 691 self.timer1, 692 self.clcd, 693 self.kmi0, 694 self.kmi1, 695 self.cf_ctrl, 696 self.rtc, 697 self.vram, 698 self.l2x0_fake, 699 self.uart1_fake, 700 self.uart2_fake, 701 self.uart3_fake, 702 self.sp810_fake, 703 self.watchdog_fake, 704 self.aaci_fake, 705 self.lan_fake, 706 self.usb_fake, 707 self.mmc_fake, 708 self.energy_ctrl, 709 ] 710 # Try to attach the I/O if it exists 711 if hasattr(self, "ide"): 712 devices.append(self.ide) 713 if hasattr(self, "ethernet"): 714 devices.append(self.ethernet) 715 return devices 716 |
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658 # Attach any PCI devices that are supported 659 def attachPciDevices(self): 660 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 661 InterruptLine=1, InterruptPin=1) 662 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 663 InterruptLine=2, InterruptPin=2) 664 665 def enableMSIX(self): --- 5 unchanged lines hidden (view full) --- 671 self.nvmem = SimpleMemory(range = AddrRange('64MB'), 672 conf_table_reported = False) 673 self.nvmem.port = mem_bus.master 674 cur_sys.boot_loader = loc('boot_emm.arm') 675 cur_sys.atags_addr = 0x8000000 676 cur_sys.load_addr_mask = 0xfffffff 677 cur_sys.load_offset = 0x80000000 678 | 717 # Attach any PCI devices that are supported 718 def attachPciDevices(self): 719 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 720 InterruptLine=1, InterruptPin=1) 721 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 722 InterruptLine=2, InterruptPin=2) 723 724 def enableMSIX(self): --- 5 unchanged lines hidden (view full) --- 730 self.nvmem = SimpleMemory(range = AddrRange('64MB'), 731 conf_table_reported = False) 732 self.nvmem.port = mem_bus.master 733 cur_sys.boot_loader = loc('boot_emm.arm') 734 cur_sys.atags_addr = 0x8000000 735 cur_sys.load_addr_mask = 0xfffffff 736 cur_sys.load_offset = 0x80000000 737 |
679 # Attach I/O devices that are on chip and also set the appropriate 680 # ranges for the bridge 681 def attachOnChipIO(self, bus, bridge=None): 682 self.gic.pio = bus.master 683 self.vgic.pio = bus.master 684 self.local_cpu_timer.pio = bus.master 685 if hasattr(self, "gicv2m"): 686 self.gicv2m.pio = bus.master 687 self.hdlcd.dma = bus.slave 688 if bridge: 689 # Bridge ranges based on excluding what is part of on-chip I/O 690 # (gic, a9scu) 691 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 692 AddrRange(0x2B000000, size='4MB'), 693 AddrRange(0x30000000, size='256MB'), 694 AddrRange(0x40000000, size='512MB'), 695 AddrRange(0x18000000, size='64MB'), 696 AddrRange(0x1C000000, size='64MB')] 697 698 699 # Set the clock domain for IO objects that are considered 700 # to be "close" to the cores. 701 def onChipIOClkDomain(self, clkdomain): 702 self.gic.clk_domain = clkdomain 703 if hasattr(self, "gicv2m"): 704 self.gicv2m.clk_domain = clkdomain 705 self.hdlcd.clk_domain = clkdomain 706 self.vgic.clk_domain = clkdomain 707 708 # Attach I/O devices to specified bus object. Done here 709 # as the specified bus to connect to may not always be fixed. 710 def attachIO(self, bus): 711 self.uart.pio = bus.master 712 self.realview_io.pio = bus.master 713 self.pci_host.pio = bus.master 714 self.timer0.pio = bus.master 715 self.timer1.pio = bus.master 716 self.clcd.pio = bus.master 717 self.clcd.dma = bus.slave 718 self.hdlcd.pio = bus.master 719 self.kmi0.pio = bus.master 720 self.kmi1.pio = bus.master 721 self.cf_ctrl.pio = bus.master 722 self.cf_ctrl.dma = bus.slave 723 self.rtc.pio = bus.master 724 self.vram.port = bus.master 725 726 self.l2x0_fake.pio = bus.master 727 self.uart1_fake.pio = bus.master 728 self.uart2_fake.pio = bus.master 729 self.uart3_fake.pio = bus.master 730 self.sp810_fake.pio = bus.master 731 self.watchdog_fake.pio = bus.master 732 self.aaci_fake.pio = bus.master 733 self.lan_fake.pio = bus.master 734 self.usb_fake.pio = bus.master 735 self.mmc_fake.pio = bus.master 736 self.energy_ctrl.pio = bus.master 737 738 # Try to attach the I/O if it exists 739 try: 740 self.ide.pio = bus.master 741 self.ide.dma = bus.slave 742 self.ethernet.pio = bus.master 743 self.ethernet.dma = bus.slave 744 except: 745 pass 746 747 # Set the clock domain for IO objects that are considered 748 # to be "far" away from the cores. 749 def offChipIOClkDomain(self, clkdomain): 750 self.uart.clk_domain = clkdomain 751 self.realview_io.clk_domain = clkdomain 752 self.timer0.clk_domain = clkdomain 753 self.timer1.clk_domain = clkdomain 754 self.clcd.clk_domain = clkdomain 755 self.kmi0.clk_domain = clkdomain 756 self.kmi1.clk_domain = clkdomain 757 self.cf_ctrl.clk_domain = clkdomain 758 self.rtc.clk_domain = clkdomain 759 self.vram.clk_domain = clkdomain 760 761 self.l2x0_fake.clk_domain = clkdomain 762 self.uart1_fake.clk_domain = clkdomain 763 self.uart2_fake.clk_domain = clkdomain 764 self.uart3_fake.clk_domain = clkdomain 765 self.sp810_fake.clk_domain = clkdomain 766 self.watchdog_fake.clk_domain = clkdomain 767 self.aaci_fake.clk_domain = clkdomain 768 self.lan_fake.clk_domain = clkdomain 769 self.usb_fake.clk_domain = clkdomain 770 self.mmc_fake.clk_domain = clkdomain 771 self.energy_ctrl.clk_domain = clkdomain 772 | |
773class VExpress_EMM64(VExpress_EMM): 774 # Three memory regions are specified totalling 512GB 775 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 776 (Addr('512GB'), Addr('480GB'))] 777 pci_host = GenericPciHost( 778 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 779 pci_pio_base=0x2f000000) 780 --- 186 unchanged lines hidden --- | 738class VExpress_EMM64(VExpress_EMM): 739 # Three memory regions are specified totalling 512GB 740 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 741 (Addr('512GB'), Addr('480GB'))] 742 pci_host = GenericPciHost( 743 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 744 pci_pio_base=0x2f000000) 745 --- 186 unchanged lines hidden --- |