1# Copyright (c) 2009 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42
43from m5.params import *
44from m5.proxy import *
45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
46from Ide import *
47from Platform import Platform
48from Terminal import Terminal
49from Uart import Uart
50
51class AmbaDevice(BasicPioDevice):
52 type = 'AmbaDevice'
53 abstract = True
54 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
55
56class AmbaIntDevice(AmbaDevice):
57 type = 'AmbaIntDevice'
58 abstract = True
59 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
60 int_num = Param.UInt32("Interrupt number that connects to GIC")
61 int_delay = Param.Latency("100ns",
62 "Time between action and interrupt generation by device")
63
64class AmbaDmaDevice(DmaDevice):
65 type = 'AmbaDmaDevice'
66 abstract = True
67 pio_addr = Param.Addr("Address for AMBA slave interface")
68 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
69 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
70 int_num = Param.UInt32("Interrupt number that connects to GIC")
71 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
72
73class A9SCU(BasicPioDevice):
74 type = 'A9SCU'
75
76class RealViewCtrl(BasicPioDevice):
77 type = 'RealViewCtrl'
78 proc_id = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
79 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
80
81class Gic(PioDevice):
82 type = 'Gic'
83 dist_addr = Param.Addr(0x1f001000, "Address for distributor")
84 cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
85 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
86 cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
87 int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
88 it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
89
90class AmbaFake(AmbaDevice):
91 type = 'AmbaFake'
92 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
93 amba_id = 0;
94
95class Pl011(Uart):
96 type = 'Pl011'
97 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
98 int_num = Param.UInt32("Interrupt number that connects to GIC")
99 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
100 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
101
102class Sp804(AmbaDevice):
103 type = 'Sp804'
104 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
105 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
106 clock0 = Param.Clock('1MHz', "Clock speed of the input")
107 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
108 clock1 = Param.Clock('1MHz', "Clock speed of the input")
109 amba_id = 0x00141804
110
111class CpuLocalTimer(BasicPioDevice):
112 type = 'CpuLocalTimer'
113 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
114 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
115 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
116 clock = Param.Clock('1GHz', "Clock speed at which the timer counts")
117
118class Pl050(AmbaIntDevice):
119 type = 'Pl050'
120 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display")
121 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
122 int_delay = '1us'
123 amba_id = 0x00141050
124
125class Pl111(AmbaDmaDevice):
126 type = 'Pl111'
127 clock = Param.Clock('24MHz', "Clock speed of the input")
128 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display")
129 amba_id = 0x00141111
130
131class RealView(Platform):
132 type = 'RealView'
133 system = Param.System(Parent.any, "system")
134
135# Reference for memory map and interrupt number
136# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
137# Chapter 4: Programmer's Reference
138class RealViewPBX(RealView):
139 uart = Pl011(pio_addr=0x10009000, int_num=44)
140 realview_io = RealViewCtrl(pio_addr=0x10000000)
141 gic = Gic()
142 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
143 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
144 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600)
145 clcd = Pl111(pio_addr=0x10020000, int_num=55)
146 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
147 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
148 a9scu = A9SCU(pio_addr=0x1f000000)
149 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=0,
150 io_shift = 1, ctrl_offset = 2, Command = 0x1,
151 BAR0 = 0x18000000, BAR0Size = '16B',
152 BAR1 = 0x18000100, BAR1Size = '1B',
153 BAR0LegacyIO = True, BAR1LegacyIO = True)
154
155
156 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
157 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
158 fake_mem=True)
159 dmac_fake = AmbaFake(pio_addr=0x10030000)
160 uart1_fake = AmbaFake(pio_addr=0x1000a000)
161 uart2_fake = AmbaFake(pio_addr=0x1000b000)
162 uart3_fake = AmbaFake(pio_addr=0x1000c000)
163 smc_fake = AmbaFake(pio_addr=0x100e1000)
164 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
165 watchdog_fake = AmbaFake(pio_addr=0x10010000)
166 gpio0_fake = AmbaFake(pio_addr=0x10013000)
167 gpio1_fake = AmbaFake(pio_addr=0x10014000)
168 gpio2_fake = AmbaFake(pio_addr=0x10015000)
169 ssp_fake = AmbaFake(pio_addr=0x1000d000)
170 sci_fake = AmbaFake(pio_addr=0x1000e000)
171 aaci_fake = AmbaFake(pio_addr=0x10004000)
172 mmc_fake = AmbaFake(pio_addr=0x10005000)
173 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
174
175
176 # Attach I/O devices that are on chip
177 def attachOnChipIO(self, bus):
178 self.gic.pio = bus.port
179 self.l2x0_fake.pio = bus.port
180 self.a9scu.pio = bus.port
181 self.local_cpu_timer.pio = bus.port
182
183 # Attach I/O devices to specified bus object. Can't do this
184 # earlier, since the bus object itself is typically defined at the
185 # System level.
186 def attachIO(self, bus):
187 self.uart.pio = bus.port
188 self.realview_io.pio = bus.port
189 self.timer0.pio = bus.port
190 self.timer1.pio = bus.port
191 self.clcd.pio = bus.port
192 self.kmi0.pio = bus.port
193 self.kmi1.pio = bus.port
194 self.cf_ctrl.pio = bus.port
195 self.dmac_fake.pio = bus.port
196 self.uart1_fake.pio = bus.port
197 self.uart2_fake.pio = bus.port
198 self.uart3_fake.pio = bus.port
199 self.smc_fake.pio = bus.port
200 self.sp810_fake.pio = bus.port
201 self.watchdog_fake.pio = bus.port
202 self.gpio0_fake.pio = bus.port
203 self.gpio1_fake.pio = bus.port
204 self.gpio2_fake.pio = bus.port
205 self.ssp_fake.pio = bus.port
206 self.sci_fake.pio = bus.port
207 self.aaci_fake.pio = bus.port
208 self.mmc_fake.pio = bus.port
209 self.rtc_fake.pio = bus.port
210 self.flash_fake.pio = bus.port
211
212# Reference for memory map and interrupt number
213# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
214# Chapter 4: Programmer's Reference
215class RealViewEB(RealView):
216 uart = Pl011(pio_addr=0x10009000, int_num=44)
217 realview_io = RealViewCtrl(pio_addr=0x10000000)
218 gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000)
219 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
220 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
221 clcd = Pl111(pio_addr=0x10020000, int_num=23)
222 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
223 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
224
225 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
226 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
227 fake_mem=True)
228 dmac_fake = AmbaFake(pio_addr=0x10030000)
229 uart1_fake = AmbaFake(pio_addr=0x1000a000)
230 uart2_fake = AmbaFake(pio_addr=0x1000b000)
231 uart3_fake = AmbaFake(pio_addr=0x1000c000)
232 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
233 smc_fake = AmbaFake(pio_addr=0x100e1000)
234 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
235 watchdog_fake = AmbaFake(pio_addr=0x10010000)
236 gpio0_fake = AmbaFake(pio_addr=0x10013000)
237 gpio1_fake = AmbaFake(pio_addr=0x10014000)
238 gpio2_fake = AmbaFake(pio_addr=0x10015000)
239 ssp_fake = AmbaFake(pio_addr=0x1000d000)
240 sci_fake = AmbaFake(pio_addr=0x1000e000)
241 aaci_fake = AmbaFake(pio_addr=0x10004000)
242 mmc_fake = AmbaFake(pio_addr=0x10005000)
243 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
244
245
246
247 # Attach I/O devices that are on chip
248 def attachOnChipIO(self, bus):
249 self.gic.pio = bus.port
250 self.l2x0_fake.pio = bus.port
251
252 # Attach I/O devices to specified bus object. Can't do this
253 # earlier, since the bus object itself is typically defined at the
254 # System level.
255 def attachIO(self, bus):
256 self.uart.pio = bus.port
257 self.realview_io.pio = bus.port
258 self.timer0.pio = bus.port
259 self.timer1.pio = bus.port
260 self.clcd.pio = bus.port
261 self.kmi0.pio = bus.port
262 self.kmi1.pio = bus.port
263 self.dmac_fake.pio = bus.port
264 self.uart1_fake.pio = bus.port
265 self.uart2_fake.pio = bus.port
266 self.uart3_fake.pio = bus.port
267 self.smc_fake.pio = bus.port
268 self.sp810_fake.pio = bus.port
269 self.watchdog_fake.pio = bus.port
270 self.gpio0_fake.pio = bus.port
271 self.gpio1_fake.pio = bus.port
272 self.gpio2_fake.pio = bus.port
273 self.ssp_fake.pio = bus.port
274 self.sci_fake.pio = bus.port
275 self.aaci_fake.pio = bus.port
276 self.mmc_fake.pio = bus.port
277 self.rtc_fake.pio = bus.port
278 self.flash_fake.pio = bus.port
279 self.smcreg_fake.pio = bus.port
280