1# Copyright (c) 2009-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

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83
84class RealViewCtrl(BasicPioDevice):
85 type = 'RealViewCtrl'
86 cxx_header = "dev/arm/rv_ctrl.hh"
87 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
88 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
89 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
90
91class AmbaFake(AmbaPioDevice):
92 type = 'AmbaFake'
93 cxx_header = "dev/arm/amba_fake.hh"
94 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
95 amba_id = 0;
96
97class Pl011(Uart):
98 type = 'Pl011'

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114
115class CpuLocalTimer(BasicPioDevice):
116 type = 'CpuLocalTimer'
117 cxx_header = "dev/arm/timer_cpulocal.hh"
118 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
119 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
120 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
121
122class PL031(AmbaIntDevice):
123 type = 'PL031'
124 cxx_header = "dev/arm/rtc_pl031.hh"
125 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
126 amba_id = 0x00341031
127
128class Pl050(AmbaIntDevice):
129 type = 'Pl050'

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161 mem_start_addr = Param.Addr(0, "Start address of main memory")
162 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform")
163
164 def setupBootLoader(self, mem_bus, cur_sys, loc):
165 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
166 conf_table_reported = False)
167 self.nvmem.port = mem_bus.master
168 cur_sys.boot_loader = loc('boot.arm')
169
170
171# Reference for memory map and interrupt number
172# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
173# Chapter 4: Programmer's Reference
174class RealViewPBX(RealView):
175 uart = Pl011(pio_addr=0x10009000, int_num=44)
176 realview_io = RealViewCtrl(pio_addr=0x10000000)

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335class VExpress_EMM(RealView):
336 mem_start_addr = '2GB'
337 max_mem_size = '2GB'
338 pci_cfg_base = 0x30000000
339 uart = Pl011(pio_addr=0x1c090000, int_num=37)
340 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000)
341 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
342 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000)
343 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
344 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
345 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
346 hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117)
347 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
348 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
349 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
350 io_shift = 2, ctrl_offset = 2, Command = 0x1,
351 BAR0 = 0x1C1A0000, BAR0Size = '256B',
352 BAR1 = 0x1C1A0100, BAR1Size = '4096B',
353 BAR0LegacyIO = True, BAR1LegacyIO = True)
354
355 pciconfig = PciConfigAll(size='256MB')
356 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,

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375 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
376 mmc_fake = AmbaFake(pio_addr=0x1c050000)
377
378 def setupBootLoader(self, mem_bus, cur_sys, loc):
379 self.nvmem = SimpleMemory(range = AddrRange('64MB'),
380 conf_table_reported = False)
381 self.nvmem.port = mem_bus.master
382 cur_sys.boot_loader = loc('boot_emm.arm')
383 cur_sys.atags_addr = 0x80000100
384
385 # Attach I/O devices that are on chip and also set the appropriate
386 # ranges for the bridge
387 def attachOnChipIO(self, bus, bridge):
388 self.gic.pio = bus.master
389 self.local_cpu_timer.pio = bus.master
390 self.hdlcd.dma = bus.slave
391 # Bridge ranges based on excluding what is part of on-chip I/O
392 # (gic, a9scu)
393 bridge.ranges = [AddrRange(0x2F000000, size='16MB'),
394 AddrRange(0x2B000000, size='4MB'),
395 AddrRange(0x30000000, size='256MB'),
396 AddrRange(0x40000000, size='512MB'),
397 AddrRange(0x18000000, size='64MB'),
398 AddrRange(0x1C000000, size='64MB')]
399
400 # Attach I/O devices to specified bus object. Can't do this
401 # earlier, since the bus object itself is typically defined at the
402 # System level.
403 def attachIO(self, bus):
404 self.uart.pio = bus.master
405 self.realview_io.pio = bus.master
406 self.timer0.pio = bus.master
407 self.timer1.pio = bus.master

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430 self.uart3_fake.pio = bus.master
431 self.sp810_fake.pio = bus.master
432 self.watchdog_fake.pio = bus.master
433 self.aaci_fake.pio = bus.master
434 self.lan_fake.pio = bus.master
435 self.usb_fake.pio = bus.master
436 self.mmc_fake.pio = bus.master
437