1# Copyright (c) 2009-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
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46from Pci import PciConfigAll
47from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
48from Ide import *
49from Platform import Platform
50from Terminal import Terminal
51from Uart import Uart
52from SimpleMemory import SimpleMemory
53from Gic import *
54
55class AmbaPioDevice(BasicPioDevice):
56 type = 'AmbaPioDevice'
57 abstract = True
58 cxx_header = "dev/arm/amba_device.hh"
59 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
60
61class AmbaIntDevice(AmbaPioDevice):
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242 gpio0_fake = AmbaFake(pio_addr=0x10013000)
243 gpio1_fake = AmbaFake(pio_addr=0x10014000)
244 gpio2_fake = AmbaFake(pio_addr=0x10015000)
245 ssp_fake = AmbaFake(pio_addr=0x1000d000)
246 sci_fake = AmbaFake(pio_addr=0x1000e000)
247 aaci_fake = AmbaFake(pio_addr=0x10004000)
248 mmc_fake = AmbaFake(pio_addr=0x10005000)
249 rtc = PL031(pio_addr=0x10017000, int_num=42)
250
251
252 # Attach I/O devices that are on chip and also set the appropriate
253 # ranges for the bridge
254 def attachOnChipIO(self, bus, bridge):
255 self.gic.pio = bus.master
256 self.l2x0_fake.pio = bus.master
257 self.a9scu.pio = bus.master
--- 40 unchanged lines hidden (view full) ---
298 self.gpio1_fake.pio = bus.master
299 self.gpio2_fake.pio = bus.master
300 self.ssp_fake.pio = bus.master
301 self.sci_fake.pio = bus.master
302 self.aaci_fake.pio = bus.master
303 self.mmc_fake.pio = bus.master
304 self.rtc.pio = bus.master
305 self.flash_fake.pio = bus.master
306
307 # Set the clock domain for IO objects that are considered
308 # to be "far" away from the cores.
309 def offChipIOClkDomain(self, clkdomain):
310 self.uart.clk_domain = clkdomain
311 self.realview_io.clk_domain = clkdomain
312 self.timer0.clk_domain = clkdomain
313 self.timer1.clk_domain = clkdomain
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326 self.gpio1_fake.clk_domain = clkdomain
327 self.gpio2_fake.clk_domain = clkdomain
328 self.ssp_fake.clk_domain = clkdomain
329 self.sci_fake.clk_domain = clkdomain
330 self.aaci_fake.clk_domain = clkdomain
331 self.mmc_fake.clk_domain = clkdomain
332 self.rtc.clk_domain = clkdomain
333 self.flash_fake.clk_domain = clkdomain
334
335# Reference for memory map and interrupt number
336# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
337# Chapter 4: Programmer's Reference
338class RealViewEB(RealView):
339 uart = Pl011(pio_addr=0x10009000, int_num=44)
340 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
341 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
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359 gpio0_fake = AmbaFake(pio_addr=0x10013000)
360 gpio1_fake = AmbaFake(pio_addr=0x10014000)
361 gpio2_fake = AmbaFake(pio_addr=0x10015000)
362 ssp_fake = AmbaFake(pio_addr=0x1000d000)
363 sci_fake = AmbaFake(pio_addr=0x1000e000)
364 aaci_fake = AmbaFake(pio_addr=0x10004000)
365 mmc_fake = AmbaFake(pio_addr=0x10005000)
366 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
367
368
369
370 # Attach I/O devices that are on chip and also set the appropriate
371 # ranges for the bridge
372 def attachOnChipIO(self, bus, bridge):
373 self.gic.pio = bus.master
374 self.l2x0_fake.pio = bus.master
375 # Bridge ranges based on excluding what is part of on-chip I/O
376 # (gic, l2x0)
377 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
--- 30 unchanged lines hidden (view full) ---
408 self.gpio2_fake.pio = bus.master
409 self.ssp_fake.pio = bus.master
410 self.sci_fake.pio = bus.master
411 self.aaci_fake.pio = bus.master
412 self.mmc_fake.pio = bus.master
413 self.rtc_fake.pio = bus.master
414 self.flash_fake.pio = bus.master
415 self.smcreg_fake.pio = bus.master
416
417 # Set the clock domain for IO objects that are considered
418 # to be "far" away from the cores.
419 def offChipIOClkDomain(self, clkdomain):
420 self.uart.clk_domain = clkdomain
421 self.realview_io.clk_domain = clkdomain
422 self.timer0.clk_domain = clkdomain
423 self.timer1.clk_domain = clkdomain
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436 self.gpio2_fake.clk_domain = clkdomain
437 self.ssp_fake.clk_domain = clkdomain
438 self.sci_fake.clk_domain = clkdomain
439 self.aaci_fake.clk_domain = clkdomain
440 self.mmc_fake.clk_domain = clkdomain
441 self.rtc.clk_domain = clkdomain
442 self.flash_fake.clk_domain = clkdomain
443 self.smcreg_fake.clk_domain = clkdomain
444
445class VExpress_EMM(RealView):
446 _mem_regions = [(Addr('2GB'), Addr('2GB'))]
447 pci_cfg_base = 0x30000000
448 uart = Pl011(pio_addr=0x1c090000, int_num=37)
449 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \
450 idreg=0x02250000, pio_addr=0x1C010000)
451 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
--- 22 unchanged lines hidden (view full) ---
474 uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
475 uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
476 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
477 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
478 aaci_fake = AmbaFake(pio_addr=0x1C040000)
479 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
480 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
481 mmc_fake = AmbaFake(pio_addr=0x1c050000)
482
483 # Attach any PCI devices that are supported
484 def attachPciDevices(self):
485 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
486 InterruptLine=1, InterruptPin=1)
487 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
488 InterruptLine=2, InterruptPin=2)
489
--- 64 unchanged lines hidden (view full) ---
554 self.uart2_fake.pio = bus.master
555 self.uart3_fake.pio = bus.master
556 self.sp810_fake.pio = bus.master
557 self.watchdog_fake.pio = bus.master
558 self.aaci_fake.pio = bus.master
559 self.lan_fake.pio = bus.master
560 self.usb_fake.pio = bus.master
561 self.mmc_fake.pio = bus.master
562
563 # Try to attach the I/O if it exists
564 try:
565 self.ide.pio = bus.master
566 self.ide.config = bus.master
567 self.ide.dma = bus.slave
568 self.ethernet.pio = bus.master
569 self.ethernet.config = bus.master
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591 self.uart2_fake.clk_domain = clkdomain
592 self.uart3_fake.clk_domain = clkdomain
593 self.sp810_fake.clk_domain = clkdomain
594 self.watchdog_fake.clk_domain = clkdomain
595 self.aaci_fake.clk_domain = clkdomain
596 self.lan_fake.clk_domain = clkdomain
597 self.usb_fake.clk_domain = clkdomain
598 self.mmc_fake.clk_domain = clkdomain
599
600class VExpress_EMM64(VExpress_EMM):
601 pci_io_base = 0x2f000000
602 pci_cfg_gen_offsets = True
603 # Three memory regions are specified totalling 512GB
604 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
605 (Addr('512GB'), Addr('480GB'))]
606 def setupBootLoader(self, mem_bus, cur_sys, loc):
607 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
608 self.nvmem.port = mem_bus.master
609 cur_sys.boot_loader = loc('boot_emm.arm64')
610 cur_sys.atags_addr = 0x8000000
611 cur_sys.load_addr_mask = 0xfffffff
612 cur_sys.load_offset = 0x80000000
613
614
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
--- 37 unchanged lines hidden (view full) ---
46from Pci import PciConfigAll
47from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
48from Ide import *
49from Platform import Platform
50from Terminal import Terminal
51from Uart import Uart
52from SimpleMemory import SimpleMemory
53from Gic import *
54
55class AmbaPioDevice(BasicPioDevice):
56 type = 'AmbaPioDevice'
57 abstract = True
58 cxx_header = "dev/arm/amba_device.hh"
59 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
60
61class AmbaIntDevice(AmbaPioDevice):
--- 180 unchanged lines hidden (view full) ---
242 gpio0_fake = AmbaFake(pio_addr=0x10013000)
243 gpio1_fake = AmbaFake(pio_addr=0x10014000)
244 gpio2_fake = AmbaFake(pio_addr=0x10015000)
245 ssp_fake = AmbaFake(pio_addr=0x1000d000)
246 sci_fake = AmbaFake(pio_addr=0x1000e000)
247 aaci_fake = AmbaFake(pio_addr=0x10004000)
248 mmc_fake = AmbaFake(pio_addr=0x10005000)
249 rtc = PL031(pio_addr=0x10017000, int_num=42)
250
251
252 # Attach I/O devices that are on chip and also set the appropriate
253 # ranges for the bridge
254 def attachOnChipIO(self, bus, bridge):
255 self.gic.pio = bus.master
256 self.l2x0_fake.pio = bus.master
257 self.a9scu.pio = bus.master
--- 40 unchanged lines hidden (view full) ---
298 self.gpio1_fake.pio = bus.master
299 self.gpio2_fake.pio = bus.master
300 self.ssp_fake.pio = bus.master
301 self.sci_fake.pio = bus.master
302 self.aaci_fake.pio = bus.master
303 self.mmc_fake.pio = bus.master
304 self.rtc.pio = bus.master
305 self.flash_fake.pio = bus.master
306
307 # Set the clock domain for IO objects that are considered
308 # to be "far" away from the cores.
309 def offChipIOClkDomain(self, clkdomain):
310 self.uart.clk_domain = clkdomain
311 self.realview_io.clk_domain = clkdomain
312 self.timer0.clk_domain = clkdomain
313 self.timer1.clk_domain = clkdomain
--- 12 unchanged lines hidden (view full) ---
326 self.gpio1_fake.clk_domain = clkdomain
327 self.gpio2_fake.clk_domain = clkdomain
328 self.ssp_fake.clk_domain = clkdomain
329 self.sci_fake.clk_domain = clkdomain
330 self.aaci_fake.clk_domain = clkdomain
331 self.mmc_fake.clk_domain = clkdomain
332 self.rtc.clk_domain = clkdomain
333 self.flash_fake.clk_domain = clkdomain
334
335# Reference for memory map and interrupt number
336# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
337# Chapter 4: Programmer's Reference
338class RealViewEB(RealView):
339 uart = Pl011(pio_addr=0x10009000, int_num=44)
340 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
341 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
--- 17 unchanged lines hidden (view full) ---
359 gpio0_fake = AmbaFake(pio_addr=0x10013000)
360 gpio1_fake = AmbaFake(pio_addr=0x10014000)
361 gpio2_fake = AmbaFake(pio_addr=0x10015000)
362 ssp_fake = AmbaFake(pio_addr=0x1000d000)
363 sci_fake = AmbaFake(pio_addr=0x1000e000)
364 aaci_fake = AmbaFake(pio_addr=0x10004000)
365 mmc_fake = AmbaFake(pio_addr=0x10005000)
366 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
367
368
369
370 # Attach I/O devices that are on chip and also set the appropriate
371 # ranges for the bridge
372 def attachOnChipIO(self, bus, bridge):
373 self.gic.pio = bus.master
374 self.l2x0_fake.pio = bus.master
375 # Bridge ranges based on excluding what is part of on-chip I/O
376 # (gic, l2x0)
377 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
--- 30 unchanged lines hidden (view full) ---
408 self.gpio2_fake.pio = bus.master
409 self.ssp_fake.pio = bus.master
410 self.sci_fake.pio = bus.master
411 self.aaci_fake.pio = bus.master
412 self.mmc_fake.pio = bus.master
413 self.rtc_fake.pio = bus.master
414 self.flash_fake.pio = bus.master
415 self.smcreg_fake.pio = bus.master
416
417 # Set the clock domain for IO objects that are considered
418 # to be "far" away from the cores.
419 def offChipIOClkDomain(self, clkdomain):
420 self.uart.clk_domain = clkdomain
421 self.realview_io.clk_domain = clkdomain
422 self.timer0.clk_domain = clkdomain
423 self.timer1.clk_domain = clkdomain
--- 12 unchanged lines hidden (view full) ---
436 self.gpio2_fake.clk_domain = clkdomain
437 self.ssp_fake.clk_domain = clkdomain
438 self.sci_fake.clk_domain = clkdomain
439 self.aaci_fake.clk_domain = clkdomain
440 self.mmc_fake.clk_domain = clkdomain
441 self.rtc.clk_domain = clkdomain
442 self.flash_fake.clk_domain = clkdomain
443 self.smcreg_fake.clk_domain = clkdomain
444
445class VExpress_EMM(RealView):
446 _mem_regions = [(Addr('2GB'), Addr('2GB'))]
447 pci_cfg_base = 0x30000000
448 uart = Pl011(pio_addr=0x1c090000, int_num=37)
449 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \
450 idreg=0x02250000, pio_addr=0x1C010000)
451 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
--- 22 unchanged lines hidden (view full) ---
474 uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
475 uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
476 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
477 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
478 aaci_fake = AmbaFake(pio_addr=0x1C040000)
479 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
480 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
481 mmc_fake = AmbaFake(pio_addr=0x1c050000)
482
483 # Attach any PCI devices that are supported
484 def attachPciDevices(self):
485 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
486 InterruptLine=1, InterruptPin=1)
487 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
488 InterruptLine=2, InterruptPin=2)
489
--- 64 unchanged lines hidden (view full) ---
554 self.uart2_fake.pio = bus.master
555 self.uart3_fake.pio = bus.master
556 self.sp810_fake.pio = bus.master
557 self.watchdog_fake.pio = bus.master
558 self.aaci_fake.pio = bus.master
559 self.lan_fake.pio = bus.master
560 self.usb_fake.pio = bus.master
561 self.mmc_fake.pio = bus.master
562
563 # Try to attach the I/O if it exists
564 try:
565 self.ide.pio = bus.master
566 self.ide.config = bus.master
567 self.ide.dma = bus.slave
568 self.ethernet.pio = bus.master
569 self.ethernet.config = bus.master
--- 21 unchanged lines hidden (view full) ---
591 self.uart2_fake.clk_domain = clkdomain
592 self.uart3_fake.clk_domain = clkdomain
593 self.sp810_fake.clk_domain = clkdomain
594 self.watchdog_fake.clk_domain = clkdomain
595 self.aaci_fake.clk_domain = clkdomain
596 self.lan_fake.clk_domain = clkdomain
597 self.usb_fake.clk_domain = clkdomain
598 self.mmc_fake.clk_domain = clkdomain
599
600class VExpress_EMM64(VExpress_EMM):
601 pci_io_base = 0x2f000000
602 pci_cfg_gen_offsets = True
603 # Three memory regions are specified totalling 512GB
604 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
605 (Addr('512GB'), Addr('480GB'))]
606 def setupBootLoader(self, mem_bus, cur_sys, loc):
607 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
608 self.nvmem.port = mem_bus.master
609 cur_sys.boot_loader = loc('boot_emm.arm64')
610 cur_sys.atags_addr = 0x8000000
611 cur_sys.load_addr_mask = 0xfffffff
612 cur_sys.load_offset = 0x80000000
613
614