1# Copyright (c) 2009 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42
43from m5.params import *
44from m5.proxy import *
45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
46from Pci import PciConfigAll
47from Ethernet import NSGigE, IGbE_e1000, IGbE_igb
48from Ide import *
49from Platform import Platform
50from Terminal import Terminal
51from Uart import Uart
52
53class AmbaDevice(BasicPioDevice):
54 type = 'AmbaDevice'
55 abstract = True
56 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
57
58class AmbaIntDevice(AmbaDevice):
59 type = 'AmbaIntDevice'
60 abstract = True
61 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
62 int_num = Param.UInt32("Interrupt number that connects to GIC")
63 int_delay = Param.Latency("100ns",
64 "Time between action and interrupt generation by device")
65
66class AmbaDmaDevice(DmaDevice):
67 type = 'AmbaDmaDevice'
68 abstract = True
69 pio_addr = Param.Addr("Address for AMBA slave interface")
70 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
71 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
72 int_num = Param.UInt32("Interrupt number that connects to GIC")
73 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
74
75class A9SCU(BasicPioDevice):
76 type = 'A9SCU'
77
78class RealViewCtrl(BasicPioDevice):
79 type = 'RealViewCtrl'
80 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
81 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
82 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
83
84class Gic(PioDevice):
85 type = 'Gic'
86 platform = Param.Platform(Parent.any, "Platform this device is part of.")
87 dist_addr = Param.Addr(0x1f001000, "Address for distributor")
88 cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
89 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
90 cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
91 int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
92 it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
93
94class AmbaFake(AmbaDevice):
95 type = 'AmbaFake'
96 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
97 amba_id = 0;
98
99class Pl011(Uart):
100 type = 'Pl011'
101 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
102 int_num = Param.UInt32("Interrupt number that connects to GIC")
103 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
104 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
105
106class Sp804(AmbaDevice):
107 type = 'Sp804'
108 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
109 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
110 clock0 = Param.Clock('1MHz', "Clock speed of the input")
111 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
112 clock1 = Param.Clock('1MHz', "Clock speed of the input")
113 amba_id = 0x00141804
114
115class CpuLocalTimer(BasicPioDevice):
116 type = 'CpuLocalTimer'
117 gic = Param.Gic(Parent.any, "Gic to use for interrupting")
118 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
119 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
120 clock = Param.Clock('1GHz', "Clock speed at which the timer counts")
121
122class Pl050(AmbaIntDevice):
123 type = 'Pl050'
124 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display")
125 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
126 int_delay = '1us'
127 amba_id = 0x00141050
128
129class Pl111(AmbaDmaDevice):
130 type = 'Pl111'
131 clock = Param.Clock('24MHz', "Clock speed of the input")
132 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display")
133 amba_id = 0x00141111
134
135class RealView(Platform):
136 type = 'RealView'
137 system = Param.System(Parent.any, "system")
138 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
139
140# Reference for memory map and interrupt number
141# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
142# Chapter 4: Programmer's Reference
143class RealViewPBX(RealView):
144 uart = Pl011(pio_addr=0x10009000, int_num=44)
145 realview_io = RealViewCtrl(pio_addr=0x10000000)
146 gic = Gic()
147 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
148 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
149 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600)
150 clcd = Pl111(pio_addr=0x10020000, int_num=55)
151 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
152 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
153 a9scu = A9SCU(pio_addr=0x1f000000)
154 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
155 io_shift = 1, ctrl_offset = 2, Command = 0x1,
156 BAR0 = 0x18000000, BAR0Size = '16B',
157 BAR1 = 0x18000100, BAR1Size = '1B',
158 BAR0LegacyIO = True, BAR1LegacyIO = True)
159
160
161 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
162 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
163 fake_mem=True)
164 dmac_fake = AmbaFake(pio_addr=0x10030000)
165 uart1_fake = AmbaFake(pio_addr=0x1000a000)
166 uart2_fake = AmbaFake(pio_addr=0x1000b000)
167 uart3_fake = AmbaFake(pio_addr=0x1000c000)
168 smc_fake = AmbaFake(pio_addr=0x100e1000)
169 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
170 watchdog_fake = AmbaFake(pio_addr=0x10010000)
171 gpio0_fake = AmbaFake(pio_addr=0x10013000)
172 gpio1_fake = AmbaFake(pio_addr=0x10014000)
173 gpio2_fake = AmbaFake(pio_addr=0x10015000)
174 ssp_fake = AmbaFake(pio_addr=0x1000d000)
175 sci_fake = AmbaFake(pio_addr=0x1000e000)
176 aaci_fake = AmbaFake(pio_addr=0x10004000)
177 mmc_fake = AmbaFake(pio_addr=0x10005000)
178 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
179
180
181 # Attach I/O devices that are on chip
182 def attachOnChipIO(self, bus):
183 self.gic.pio = bus.port
184 self.l2x0_fake.pio = bus.port
185 self.a9scu.pio = bus.port
186 self.local_cpu_timer.pio = bus.port
187
188 # Attach I/O devices to specified bus object. Can't do this
189 # earlier, since the bus object itself is typically defined at the
190 # System level.
191 def attachIO(self, bus):
192 self.uart.pio = bus.port
193 self.realview_io.pio = bus.port
194 self.timer0.pio = bus.port
195 self.timer1.pio = bus.port
196 self.clcd.pio = bus.port
197 self.kmi0.pio = bus.port
198 self.kmi1.pio = bus.port
199 self.cf_ctrl.pio = bus.port
200 self.dmac_fake.pio = bus.port
201 self.uart1_fake.pio = bus.port
202 self.uart2_fake.pio = bus.port
203 self.uart3_fake.pio = bus.port
204 self.smc_fake.pio = bus.port
205 self.sp810_fake.pio = bus.port
206 self.watchdog_fake.pio = bus.port
207 self.gpio0_fake.pio = bus.port
208 self.gpio1_fake.pio = bus.port
209 self.gpio2_fake.pio = bus.port
210 self.ssp_fake.pio = bus.port
211 self.sci_fake.pio = bus.port
212 self.aaci_fake.pio = bus.port
213 self.mmc_fake.pio = bus.port
214 self.rtc_fake.pio = bus.port
215 self.flash_fake.pio = bus.port
216
217# Reference for memory map and interrupt number
218# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
219# Chapter 4: Programmer's Reference
220class RealViewEB(RealView):
221 uart = Pl011(pio_addr=0x10009000, int_num=44)
222 realview_io = RealViewCtrl(pio_addr=0x10000000)
223 gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000)
224 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
225 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
226 clcd = Pl111(pio_addr=0x10020000, int_num=23)
227 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
228 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
229
230 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
231 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
232 fake_mem=True)
233 dmac_fake = AmbaFake(pio_addr=0x10030000)
234 uart1_fake = AmbaFake(pio_addr=0x1000a000)
235 uart2_fake = AmbaFake(pio_addr=0x1000b000)
236 uart3_fake = AmbaFake(pio_addr=0x1000c000)
237 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
238 smc_fake = AmbaFake(pio_addr=0x100e1000)
239 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
240 watchdog_fake = AmbaFake(pio_addr=0x10010000)
241 gpio0_fake = AmbaFake(pio_addr=0x10013000)
242 gpio1_fake = AmbaFake(pio_addr=0x10014000)
243 gpio2_fake = AmbaFake(pio_addr=0x10015000)
244 ssp_fake = AmbaFake(pio_addr=0x1000d000)
245 sci_fake = AmbaFake(pio_addr=0x1000e000)
246 aaci_fake = AmbaFake(pio_addr=0x10004000)
247 mmc_fake = AmbaFake(pio_addr=0x10005000)
248 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
249
250
251
252 # Attach I/O devices that are on chip
253 def attachOnChipIO(self, bus):
254 self.gic.pio = bus.port
255 self.l2x0_fake.pio = bus.port
256
257 # Attach I/O devices to specified bus object. Can't do this
258 # earlier, since the bus object itself is typically defined at the
259 # System level.
260 def attachIO(self, bus):
261 self.uart.pio = bus.port
262 self.realview_io.pio = bus.port
263 self.timer0.pio = bus.port
264 self.timer1.pio = bus.port
265 self.clcd.pio = bus.port
266 self.kmi0.pio = bus.port
267 self.kmi1.pio = bus.port
268 self.dmac_fake.pio = bus.port
269 self.uart1_fake.pio = bus.port
270 self.uart2_fake.pio = bus.port
271 self.uart3_fake.pio = bus.port
272 self.smc_fake.pio = bus.port
273 self.sp810_fake.pio = bus.port
274 self.watchdog_fake.pio = bus.port
275 self.gpio0_fake.pio = bus.port
276 self.gpio1_fake.pio = bus.port
277 self.gpio2_fake.pio = bus.port
278 self.ssp_fake.pio = bus.port
279 self.sci_fake.pio = bus.port
280 self.aaci_fake.pio = bus.port
281 self.mmc_fake.pio = bus.port
282 self.rtc_fake.pio = bus.port
283 self.flash_fake.pio = bus.port
284 self.smcreg_fake.pio = bus.port
285
286class VExpress_ELT(RealView):
287 pci_cfg_base = 0xD0000000
288 elba_uart = Pl011(pio_addr=0xE0009000, int_num=42)
289 uart = Pl011(pio_addr=0xFF009000, int_num=121)
290 realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000)
291 gic = Gic(dist_addr=0xE0201000, cpu_addr=0xE0200100)
292 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0xE0200600)
293 v2m_timer0 = Sp804(int_num0=120, int_num1=120, pio_addr=0xFF011000)
294 v2m_timer1 = Sp804(int_num0=121, int_num1=121, pio_addr=0xFF012000)
295 elba_timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0xE0011000, clock0='50MHz', clock1='50MHz')
296 elba_timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0xE0012000, clock0='50MHz', clock1='50MHz')
297 clcd = Pl111(pio_addr=0xE0022000, int_num=46) # CLCD interrupt no. unknown
298 kmi0 = Pl050(pio_addr=0xFF006000, int_num=124)
299 kmi1 = Pl050(pio_addr=0xFF007000, int_num=125)
300 elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52)
301 elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53)
302 a9scu = A9SCU(pio_addr=0xE0200000)
303 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
304 io_shift = 2, ctrl_offset = 2, Command = 0x1,
305 BAR0 = 0xFF01A000, BAR0Size = '256B',
306 BAR1 = 0xFF01A100, BAR1Size = '4096B',
307 BAR0LegacyIO = True, BAR1LegacyIO = True)
308
309 pciconfig = PciConfigAll()
310 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
311 InterruptLine=1, InterruptPin=1)
312
313 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
314 InterruptLine=2, InterruptPin=2)
315
316 l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff)
317 dmac_fake = AmbaFake(pio_addr=0xE0020000)
318 uart1_fake = AmbaFake(pio_addr=0xE000A000)
319 uart2_fake = AmbaFake(pio_addr=0xE000B000)
320 uart3_fake = AmbaFake(pio_addr=0xE000C000)
321 smc_fake = AmbaFake(pio_addr=0xEC000000)
322 sp810_fake = AmbaFake(pio_addr=0xFF001000, ignore_access=True)
323 watchdog_fake = AmbaFake(pio_addr=0xE0010000)
324 aaci_fake = AmbaFake(pio_addr=0xFF004000)
325 elba_aaci_fake = AmbaFake(pio_addr=0xE0004000)
326 mmc_fake = AmbaFake(pio_addr=0xE0005000) # not sure if we need this
327 rtc_fake = AmbaFake(pio_addr=0xE0017000, amba_id=0x41031)
328 spsc_fake = IsaFake(pio_addr=0xE001B000, pio_size=0x2000)
329 lan_fake = IsaFake(pio_addr=0xFA000000, pio_size=0xffff)
330 usb_fake = IsaFake(pio_addr=0xFB000000, pio_size=0x1ffff)
331
332
333 # Attach I/O devices that are on chip
334 def attachOnChipIO(self, bus):
335 self.gic.pio = bus.port
336 self.a9scu.pio = bus.port
337
338 # Attach I/O devices to specified bus object. Can't do this
339 # earlier, since the bus object itself is typically defined at the
340 # System level.
341 def attachIO(self, bus):
342 self.elba_uart.pio = bus.port
343 self.uart.pio = bus.port
344 self.realview_io.pio = bus.port
345 self.local_cpu_timer.pio = bus.port
346 self.v2m_timer0.pio = bus.port
347 self.v2m_timer1.pio = bus.port
348 self.elba_timer0.pio = bus.port
349 self.elba_timer1.pio = bus.port
350 self.clcd.pio = bus.port
351 self.kmi0.pio = bus.port
352 self.kmi1.pio = bus.port
353 self.elba_kmi0.pio = bus.port
354 self.elba_kmi1.pio = bus.port
355 self.cf_ctrl.pio = bus.port
356 self.ide.pio = bus.port
357 self.ethernet.pio = bus.port
358 self.pciconfig.pio = bus.default
359 bus.use_default_range = True
360
361 self.l2x0_fake.pio = bus.port
362 self.dmac_fake.pio = bus.port
363 self.uart1_fake.pio = bus.port
364 self.uart2_fake.pio = bus.port
365 self.uart3_fake.pio = bus.port
366 self.smc_fake.pio = bus.port
367 self.sp810_fake.pio = bus.port
368 self.watchdog_fake.pio = bus.port
369 self.aaci_fake.pio = bus.port
370 self.elba_aaci_fake.pio = bus.port
371 self.mmc_fake.pio = bus.port
372 self.rtc_fake.pio = bus.port
373 self.spsc_fake.pio = bus.port
374 self.lan_fake.pio = bus.port
375 self.usb_fake.pio = bus.port
376