1# Copyright (c) 2009-2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42
43from m5.params import *
44from m5.proxy import *
45from ClockDomain import ClockDomain
46from VoltageDomain import VoltageDomain
47from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
48from PciHost import *
49from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
50from Ide import *
51from Platform import Platform
52from Terminal import Terminal
53from Uart import Uart
54from SimpleMemory import SimpleMemory
55from Gic import *
56from EnergyCtrl import EnergyCtrl
57from ClockDomain import SrcClockDomain
58from SubSystem import SubSystem
59from Graphics import ImageFormat
60
61# Platforms with KVM support should generally use in-kernel GIC
62# emulation. Use a GIC model that automatically switches between
63# gem5's GIC model and KVM's GIC model if KVM is available.
64try:
65 from KvmGic import MuxingKvmGic
66 kvm_gicv2_class = MuxingKvmGic
67except ImportError:
68 # KVM support wasn't compiled into gem5. Fallback to a
69 # software-only GIC.
70 kvm_gicv2_class = Pl390
71 pass
72
73class AmbaPioDevice(BasicPioDevice):
74 type = 'AmbaPioDevice'
75 abstract = True
76 cxx_header = "dev/arm/amba_device.hh"
77 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
78
79class AmbaIntDevice(AmbaPioDevice):
80 type = 'AmbaIntDevice'
81 abstract = True
82 cxx_header = "dev/arm/amba_device.hh"
83 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
84 int_num = Param.UInt32("Interrupt number that connects to GIC")
85 int_delay = Param.Latency("100ns",
86 "Time between action and interrupt generation by device")
87
88class AmbaDmaDevice(DmaDevice):
89 type = 'AmbaDmaDevice'
90 abstract = True
91 cxx_header = "dev/arm/amba_device.hh"
92 pio_addr = Param.Addr("Address for AMBA slave interface")
93 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
94 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
95 int_num = Param.UInt32("Interrupt number that connects to GIC")
96 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
97
98class A9SCU(BasicPioDevice):
99 type = 'A9SCU'
100 cxx_header = "dev/arm/a9scu.hh"
101
102class ArmPciIntRouting(Enum): vals = [
103 'ARM_PCI_INT_STATIC',
104 'ARM_PCI_INT_DEV',
105 'ARM_PCI_INT_PIN',
106 ]
107
108class GenericArmPciHost(GenericPciHost):
109 type = 'GenericArmPciHost'
110 cxx_header = "dev/arm/pci_host.hh"
111
112 int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy")
113 int_base = Param.Unsigned("PCI interrupt base")
114 int_count = Param.Unsigned("Maximum number of interrupts used by this host")
115
116class RealViewCtrl(BasicPioDevice):
117 type = 'RealViewCtrl'
118 cxx_header = "dev/arm/rv_ctrl.hh"
119 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
120 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
121 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
122
123class RealViewOsc(ClockDomain):
124 type = 'RealViewOsc'
125 cxx_header = "dev/arm/rv_ctrl.hh"
126
127 parent = Param.RealViewCtrl(Parent.any, "RealView controller")
128
129 # TODO: We currently don't have the notion of a clock source,
130 # which means we have to associate oscillators with a voltage
131 # source.
132 voltage_domain = Param.VoltageDomain(Parent.voltage_domain,
133 "Voltage domain")
134
135 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
136 # the individual core/logic tile reference manuals for details
137 # about the site/position/dcc/device allocation.
138 site = Param.UInt8("Board Site")
139 position = Param.UInt8("Position in device stack")
140 dcc = Param.UInt8("Daughterboard Configuration Controller")
141 device = Param.UInt8("Device ID")
142
143 freq = Param.Clock("Default frequency")
144
145class RealViewTemperatureSensor(SimObject):
146 type = 'RealViewTemperatureSensor'
147 cxx_header = "dev/arm/rv_ctrl.hh"
148
149 parent = Param.RealViewCtrl(Parent.any, "RealView controller")
150
151 system = Param.System(Parent.any, "system")
152
153 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
154 # the individual core/logic tile reference manuals for details
155 # about the site/position/dcc/device allocation.
156 site = Param.UInt8("Board Site")
157 position = Param.UInt8("Position in device stack")
158 dcc = Param.UInt8("Daughterboard Configuration Controller")
159 device = Param.UInt8("Device ID")
160
161class VExpressMCC(SubSystem):
162 """ARM V2M-P1 Motherboard Configuration Controller
163
164This subsystem describes a subset of the devices that sit behind the
165motherboard configuration controller on the the ARM Motherboard
166Express (V2M-P1) motherboard. See ARM DUI 0447J for details.
167 """
168
169 class Osc(RealViewOsc):
170 site, position, dcc = (0, 0, 0)
171
172 class Temperature(RealViewTemperatureSensor):
173 site, position, dcc = (0, 0, 0)
174
175 osc_mcc = Osc(device=0, freq="50MHz")
176 osc_clcd = Osc(device=1, freq="23.75MHz")
177 osc_peripheral = Osc(device=2, freq="24MHz")
178 osc_system_bus = Osc(device=4, freq="24MHz")
179
180 # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM).
181 temp_crtl = Temperature(device=0)
182
183class CoreTile2A15DCC(SubSystem):
184 """ARM CoreTile Express A15x2 Daughterboard Configuration Controller
185
186This subsystem describes a subset of the devices that sit behind the
187daughterboard configuration controller on a CoreTile Express A15x2. See
188ARM DUI 0604E for details.
189 """
190
191 class Osc(RealViewOsc):
192 site, position, dcc = (1, 0, 0)
193
194 # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM)
195 osc_cpu = Osc(device=0, freq="60MHz")
196 osc_hsbm = Osc(device=4, freq="40MHz")
197 osc_pxl = Osc(device=5, freq="23.75MHz")
198 osc_smb = Osc(device=6, freq="50MHz")
199 osc_sys = Osc(device=7, freq="60MHz")
200 osc_ddr = Osc(device=8, freq="40MHz")
201
202class VGic(PioDevice):
203 type = 'VGic'
204 cxx_header = "dev/arm/vgic.hh"
205 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
206 platform = Param.Platform(Parent.any, "Platform this device is part of.")
207 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
208 hv_addr = Param.Addr(0, "Address for hv control")
209 pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
210 # The number of list registers is not currently configurable at runtime.
211 ppint = Param.UInt32("HV maintenance interrupt number")
212
213class AmbaFake(AmbaPioDevice):
214 type = 'AmbaFake'
215 cxx_header = "dev/arm/amba_fake.hh"
216 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
217 amba_id = 0;
218
219class Pl011(Uart):
220 type = 'Pl011'
221 cxx_header = "dev/arm/pl011.hh"
222 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
223 int_num = Param.UInt32("Interrupt number that connects to GIC")
224 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
225 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
226
227class Sp804(AmbaPioDevice):
228 type = 'Sp804'
229 cxx_header = "dev/arm/timer_sp804.hh"
230 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
231 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
232 clock0 = Param.Clock('1MHz', "Clock speed of the input")
233 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
234 clock1 = Param.Clock('1MHz', "Clock speed of the input")
235 amba_id = 0x00141804
236
237class A9GlobalTimer(BasicPioDevice):
238 type = 'A9GlobalTimer'
239 cxx_header = "dev/arm/timer_a9global.hh"
240 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
241 int_num = Param.UInt32("Interrrupt number that connects to GIC")
242
243class CpuLocalTimer(BasicPioDevice):
244 type = 'CpuLocalTimer'
245 cxx_header = "dev/arm/timer_cpulocal.hh"
246 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
247 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
248 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
249
250class GenericTimer(SimObject):
251 type = 'GenericTimer'
252 cxx_header = "dev/arm/generic_timer.hh"
253 system = Param.ArmSystem(Parent.any, "system")
254 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
255 # @todo: for now only two timers per CPU is supported, which is the
256 # normal behaviour when security extensions are disabled.
257 int_phys = Param.UInt32("Physical timer interrupt number")
258 int_virt = Param.UInt32("Virtual timer interrupt number")
259
260class GenericTimerMem(PioDevice):
261 type = 'GenericTimerMem'
262 cxx_header = "dev/arm/generic_timer.hh"
263 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
264
265 base = Param.Addr(0, "Base address")
266
267 int_phys = Param.UInt32("Interrupt number")
268 int_virt = Param.UInt32("Interrupt number")
269
270class PL031(AmbaIntDevice):
271 type = 'PL031'
272 cxx_header = "dev/arm/rtc_pl031.hh"
273 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
274 amba_id = 0x00341031
275
276class Pl050(AmbaIntDevice):
277 type = 'Pl050'
278 cxx_header = "dev/arm/kmi.hh"
279 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
280 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
281 int_delay = '1us'
282 amba_id = 0x00141050
283
284class Pl111(AmbaDmaDevice):
285 type = 'Pl111'
286 cxx_header = "dev/arm/pl111.hh"
287 pixel_clock = Param.Clock('24MHz', "Pixel clock")
288 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
289 amba_id = 0x00141111
290 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
291
292class HDLcd(AmbaDmaDevice):
293 type = 'HDLcd'
294 cxx_header = "dev/arm/hdlcd.hh"
295 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer "
296 "display")
297 amba_id = 0x00141000
298 workaround_swap_rb = Param.Bool(False, "Workaround incorrect color "
299 "selector order in some kernels")
300 workaround_dma_line_count = Param.Bool(True, "Workaround incorrect "
301 "DMA line count (off by 1)")
302 enable_capture = Param.Bool(True, "capture frame to "
303 "system.framebuffer.{extension}")
304 frame_format = Param.ImageFormat("Auto",
305 "image format of the captured frame")
306
307 pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range")
308
309 pxl_clk = Param.ClockDomain("Pixel clock source")
310 pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch")
311 virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate "
312 "in KVM mode")
313
314class RealView(Platform):
315 type = 'RealView'
316 cxx_header = "dev/arm/realview.hh"
317 system = Param.System(Parent.any, "system")
318 _mem_regions = [(Addr(0), Addr('256MB'))]
319
320 def _on_chip_devices(self):
321 return []
322
323 def _off_chip_devices(self):
324 return []
325
326 _off_chip_ranges = []
327
328 def _attach_device(self, device, bus, dma_ports=None):
329 if hasattr(device, "pio"):
330 device.pio = bus.master
331 if hasattr(device, "dma"):
332 if dma_ports is None:
333 device.dma = bus.slave
334 else:
335 dma_ports.append(device.dma)
336
337 def _attach_io(self, devices, *args, **kwargs):
338 for d in devices:
339 self._attach_device(d, *args, **kwargs)
340
341 def _attach_clk(self, devices, clkdomain):
342 for d in devices:
343 if hasattr(d, "clk_domain"):
344 d.clk_domain = clkdomain
345
346 def attachPciDevices(self):
347 pass
348
349 def enableMSIX(self):
350 pass
351
352 def onChipIOClkDomain(self, clkdomain):
353 self._attach_clk(self._on_chip_devices(), clkdomain)
354
355 def offChipIOClkDomain(self, clkdomain):
356 self._attach_clk(self._off_chip_devices(), clkdomain)
357
358 def attachOnChipIO(self, bus, bridge=None, *args, **kwargs):
359 self._attach_io(self._on_chip_devices(), bus, *args, **kwargs)
360 if bridge:
361 bridge.ranges = self._off_chip_ranges
362
363 def attachIO(self, *args, **kwargs):
364 self._attach_io(self._off_chip_devices(), *args, **kwargs)
365
366 def setupBootLoader(self, mem_bus, cur_sys, loc):
367 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
368 conf_table_reported = False)
369 self.nvmem.port = mem_bus.master
370 cur_sys.boot_loader = loc('boot.arm')
371 cur_sys.atags_addr = 0x100
372 cur_sys.load_addr_mask = 0xfffffff
373 cur_sys.load_offset = 0
374
375
376# Reference for memory map and interrupt number
377# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
378# Chapter 4: Programmer's Reference
379class RealViewPBX(RealView):
380 uart = Pl011(pio_addr=0x10009000, int_num=44)
381 realview_io = RealViewCtrl(pio_addr=0x10000000)
382 mcc = VExpressMCC()
383 dcc = CoreTile2A15DCC()
384 gic = Pl390()
385 pci_host = GenericPciHost(
386 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
387 pci_pio_base=0)
388 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
389 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
390 global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200)
391 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
392 pio_addr=0x1f000600)
393 clcd = Pl111(pio_addr=0x10020000, int_num=55)
394 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
395 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
396 a9scu = A9SCU(pio_addr=0x1f000000)
397 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
398 io_shift = 1, ctrl_offset = 2, Command = 0x1,
399 BAR0 = 0x18000000, BAR0Size = '16B',
400 BAR1 = 0x18000100, BAR1Size = '1B',
401 BAR0LegacyIO = True, BAR1LegacyIO = True)
402
403
404 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
405 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
406 fake_mem=True)
407 dmac_fake = AmbaFake(pio_addr=0x10030000)
408 uart1_fake = AmbaFake(pio_addr=0x1000a000)
409 uart2_fake = AmbaFake(pio_addr=0x1000b000)
410 uart3_fake = AmbaFake(pio_addr=0x1000c000)
411 smc_fake = AmbaFake(pio_addr=0x100e1000)
412 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
413 watchdog_fake = AmbaFake(pio_addr=0x10010000)
414 gpio0_fake = AmbaFake(pio_addr=0x10013000)
415 gpio1_fake = AmbaFake(pio_addr=0x10014000)
416 gpio2_fake = AmbaFake(pio_addr=0x10015000)
417 ssp_fake = AmbaFake(pio_addr=0x1000d000)
418 sci_fake = AmbaFake(pio_addr=0x1000e000)
419 aaci_fake = AmbaFake(pio_addr=0x10004000)
420 mmc_fake = AmbaFake(pio_addr=0x10005000)
421 rtc = PL031(pio_addr=0x10017000, int_num=42)
422 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
423
424
425 # Attach I/O devices that are on chip and also set the appropriate
426 # ranges for the bridge
427 def attachOnChipIO(self, bus, bridge):
428 self.gic.pio = bus.master
429 self.l2x0_fake.pio = bus.master
430 self.a9scu.pio = bus.master
431 self.global_timer.pio = bus.master
432 self.local_cpu_timer.pio = bus.master
433 # Bridge ranges based on excluding what is part of on-chip I/O
434 # (gic, l2x0, a9scu, local_cpu_timer)
435 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
436 self.a9scu.pio_addr - 1),
437 AddrRange(self.flash_fake.pio_addr,
438 self.flash_fake.pio_addr + \
439 self.flash_fake.pio_size - 1)]
440
441 # Set the clock domain for IO objects that are considered
442 # to be "close" to the cores.
443 def onChipIOClkDomain(self, clkdomain):
444 self.gic.clk_domain = clkdomain
445 self.l2x0_fake.clk_domain = clkdomain
446 self.a9scu.clkdomain = clkdomain
447 self.local_cpu_timer.clk_domain = clkdomain
448
449 # Attach I/O devices to specified bus object. Can't do this
450 # earlier, since the bus object itself is typically defined at the
451 # System level.
452 def attachIO(self, bus):
453 self.uart.pio = bus.master
454 self.realview_io.pio = bus.master
455 self.pci_host.pio = bus.master
456 self.timer0.pio = bus.master
457 self.timer1.pio = bus.master
458 self.clcd.pio = bus.master
459 self.clcd.dma = bus.slave
460 self.kmi0.pio = bus.master
461 self.kmi1.pio = bus.master
462 self.cf_ctrl.pio = bus.master
463 self.cf_ctrl.dma = bus.slave
464 self.dmac_fake.pio = bus.master
465 self.uart1_fake.pio = bus.master
466 self.uart2_fake.pio = bus.master
467 self.uart3_fake.pio = bus.master
468 self.smc_fake.pio = bus.master
469 self.sp810_fake.pio = bus.master
470 self.watchdog_fake.pio = bus.master
471 self.gpio0_fake.pio = bus.master
472 self.gpio1_fake.pio = bus.master
473 self.gpio2_fake.pio = bus.master
474 self.ssp_fake.pio = bus.master
475 self.sci_fake.pio = bus.master
476 self.aaci_fake.pio = bus.master
477 self.mmc_fake.pio = bus.master
478 self.rtc.pio = bus.master
479 self.flash_fake.pio = bus.master
480 self.energy_ctrl.pio = bus.master
481
482 # Set the clock domain for IO objects that are considered
483 # to be "far" away from the cores.
484 def offChipIOClkDomain(self, clkdomain):
485 self.uart.clk_domain = clkdomain
486 self.realview_io.clk_domain = clkdomain
487 self.timer0.clk_domain = clkdomain
488 self.timer1.clk_domain = clkdomain
489 self.clcd.clk_domain = clkdomain
490 self.kmi0.clk_domain = clkdomain
491 self.kmi1.clk_domain = clkdomain
492 self.cf_ctrl.clk_domain = clkdomain
493 self.dmac_fake.clk_domain = clkdomain
494 self.uart1_fake.clk_domain = clkdomain
495 self.uart2_fake.clk_domain = clkdomain
496 self.uart3_fake.clk_domain = clkdomain
497 self.smc_fake.clk_domain = clkdomain
498 self.sp810_fake.clk_domain = clkdomain
499 self.watchdog_fake.clk_domain = clkdomain
500 self.gpio0_fake.clk_domain = clkdomain
501 self.gpio1_fake.clk_domain = clkdomain
502 self.gpio2_fake.clk_domain = clkdomain
503 self.ssp_fake.clk_domain = clkdomain
504 self.sci_fake.clk_domain = clkdomain
505 self.aaci_fake.clk_domain = clkdomain
506 self.mmc_fake.clk_domain = clkdomain
507 self.rtc.clk_domain = clkdomain
508 self.flash_fake.clk_domain = clkdomain
509 self.energy_ctrl.clk_domain = clkdomain
510
511# Reference for memory map and interrupt number
512# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
513# Chapter 4: Programmer's Reference
514class RealViewEB(RealView):
515 uart = Pl011(pio_addr=0x10009000, int_num=44)
516 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
517 mcc = VExpressMCC()
518 dcc = CoreTile2A15DCC()
519 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
520 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
521 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
522 clcd = Pl111(pio_addr=0x10020000, int_num=23)
523 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
524 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
525
526 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
527 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
528 fake_mem=True)
529 dmac_fake = AmbaFake(pio_addr=0x10030000)
530 uart1_fake = AmbaFake(pio_addr=0x1000a000)
531 uart2_fake = AmbaFake(pio_addr=0x1000b000)
532 uart3_fake = AmbaFake(pio_addr=0x1000c000)
533 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
534 smc_fake = AmbaFake(pio_addr=0x100e1000)
535 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
536 watchdog_fake = AmbaFake(pio_addr=0x10010000)
537 gpio0_fake = AmbaFake(pio_addr=0x10013000)
538 gpio1_fake = AmbaFake(pio_addr=0x10014000)
539 gpio2_fake = AmbaFake(pio_addr=0x10015000)
540 ssp_fake = AmbaFake(pio_addr=0x1000d000)
541 sci_fake = AmbaFake(pio_addr=0x1000e000)
542 aaci_fake = AmbaFake(pio_addr=0x10004000)
543 mmc_fake = AmbaFake(pio_addr=0x10005000)
544 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
545 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
546
547 # Attach I/O devices that are on chip and also set the appropriate
548 # ranges for the bridge
549 def attachOnChipIO(self, bus, bridge):
550 self.gic.pio = bus.master
551 self.l2x0_fake.pio = bus.master
552 # Bridge ranges based on excluding what is part of on-chip I/O
553 # (gic, l2x0)
554 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
555 self.gic.cpu_addr - 1),
556 AddrRange(self.flash_fake.pio_addr, Addr.max)]
557
558 # Set the clock domain for IO objects that are considered
559 # to be "close" to the cores.
560 def onChipIOClkDomain(self, clkdomain):
561 self.gic.clk_domain = clkdomain
562 self.l2x0_fake.clk_domain = clkdomain
563
564 # Attach I/O devices to specified bus object. Can't do this
565 # earlier, since the bus object itself is typically defined at the
566 # System level.
567 def attachIO(self, bus):
568 self.uart.pio = bus.master
569 self.realview_io.pio = bus.master
570 self.pci_host.pio = bus.master
571 self.timer0.pio = bus.master
572 self.timer1.pio = bus.master
573 self.clcd.pio = bus.master
574 self.clcd.dma = bus.slave
575 self.kmi0.pio = bus.master
576 self.kmi1.pio = bus.master
577 self.dmac_fake.pio = bus.master
578 self.uart1_fake.pio = bus.master
579 self.uart2_fake.pio = bus.master
580 self.uart3_fake.pio = bus.master
581 self.smc_fake.pio = bus.master
582 self.sp810_fake.pio = bus.master
583 self.watchdog_fake.pio = bus.master
584 self.gpio0_fake.pio = bus.master
585 self.gpio1_fake.pio = bus.master
586 self.gpio2_fake.pio = bus.master
587 self.ssp_fake.pio = bus.master
588 self.sci_fake.pio = bus.master
589 self.aaci_fake.pio = bus.master
590 self.mmc_fake.pio = bus.master
591 self.rtc_fake.pio = bus.master
592 self.flash_fake.pio = bus.master
593 self.smcreg_fake.pio = bus.master
594 self.energy_ctrl.pio = bus.master
595
596 # Set the clock domain for IO objects that are considered
597 # to be "far" away from the cores.
598 def offChipIOClkDomain(self, clkdomain):
599 self.uart.clk_domain = clkdomain
600 self.realview_io.clk_domain = clkdomain
601 self.timer0.clk_domain = clkdomain
602 self.timer1.clk_domain = clkdomain
603 self.clcd.clk_domain = clkdomain
604 self.kmi0.clk_domain = clkdomain
605 self.kmi1.clk_domain = clkdomain
606 self.dmac_fake.clk_domain = clkdomain
607 self.uart1_fake.clk_domain = clkdomain
608 self.uart2_fake.clk_domain = clkdomain
609 self.uart3_fake.clk_domain = clkdomain
610 self.smc_fake.clk_domain = clkdomain
611 self.sp810_fake.clk_domain = clkdomain
612 self.watchdog_fake.clk_domain = clkdomain
613 self.gpio0_fake.clk_domain = clkdomain
614 self.gpio1_fake.clk_domain = clkdomain
615 self.gpio2_fake.clk_domain = clkdomain
616 self.ssp_fake.clk_domain = clkdomain
617 self.sci_fake.clk_domain = clkdomain
618 self.aaci_fake.clk_domain = clkdomain
619 self.mmc_fake.clk_domain = clkdomain
620 self.rtc.clk_domain = clkdomain
621 self.flash_fake.clk_domain = clkdomain
622 self.smcreg_fake.clk_domain = clkdomain
623 self.energy_ctrl.clk_domain = clkdomain
624
625class VExpress_EMM(RealView):
626 _mem_regions = [(Addr('2GB'), Addr('2GB'))]
627
628 # Ranges based on excluding what is part of on-chip I/O (gic,
629 # a9scu)
630 _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'),
631 AddrRange(0x30000000, size='256MB'),
632 AddrRange(0x40000000, size='512MB'),
633 AddrRange(0x18000000, size='64MB'),
634 AddrRange(0x1C000000, size='64MB')]
635
636 # Platform control device (off-chip)
637 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
638 idreg=0x02250000, pio_addr=0x1C010000)
639
640 mcc = VExpressMCC()
641 dcc = CoreTile2A15DCC()
642
643 ### On-chip devices ###
644 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
645 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
646
647 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
648 pio_addr=0x2C080000)
649
650 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
651 pio_addr=0x2b000000, int_num=117,
652 workaround_swap_rb=True)
653
654 def _on_chip_devices(self):
655 devices = [
656 self.gic, self.vgic,
657 self.local_cpu_timer
658 ]
659 if hasattr(self, "gicv2m"):
660 devices.append(self.gicv2m)
661 devices.append(self.hdlcd)
662 return devices
663
664 ### Off-chip devices ###
665 uart = Pl011(pio_addr=0x1c090000, int_num=37)
666 pci_host = GenericPciHost(
667 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
668 pci_pio_base=0)
669
670 generic_timer = GenericTimer(int_phys=29, int_virt=27)
671 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
672 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
673 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
674 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
675 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
676 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
677 io_shift = 2, ctrl_offset = 2, Command = 0x1,
678 BAR0 = 0x1C1A0000, BAR0Size = '256B',
679 BAR1 = 0x1C1A0100, BAR1Size = '4096B',
680 BAR0LegacyIO = True, BAR1LegacyIO = True)
681
682 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
683 conf_table_reported = False)
684 rtc = PL031(pio_addr=0x1C170000, int_num=36)
685
686 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
687 uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
688 uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
689 uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
690 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
691 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
692 aaci_fake = AmbaFake(pio_addr=0x1C040000)
693 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
694 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
695 mmc_fake = AmbaFake(pio_addr=0x1c050000)
696 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000)
697
698 def _off_chip_devices(self):
699 devices = [
700 self.uart,
701 self.realview_io,
702 self.pci_host,
703 self.timer0,
704 self.timer1,
705 self.clcd,
706 self.kmi0,
707 self.kmi1,
708 self.cf_ctrl,
709 self.rtc,
710 self.vram,
711 self.l2x0_fake,
712 self.uart1_fake,
713 self.uart2_fake,
714 self.uart3_fake,
715 self.sp810_fake,
716 self.watchdog_fake,
717 self.aaci_fake,
718 self.lan_fake,
719 self.usb_fake,
720 self.mmc_fake,
721 self.energy_ctrl,
722 ]
723 # Try to attach the I/O if it exists
724 if hasattr(self, "ide"):
725 devices.append(self.ide)
726 if hasattr(self, "ethernet"):
727 devices.append(self.ethernet)
728 return devices
729
730 # Attach any PCI devices that are supported
731 def attachPciDevices(self):
732 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
733 InterruptLine=1, InterruptPin=1)
734 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
735 InterruptLine=2, InterruptPin=2)
736
737 def enableMSIX(self):
738 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
739 self.gicv2m = Gicv2m()
740 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
741
742 def setupBootLoader(self, mem_bus, cur_sys, loc):
743 self.nvmem = SimpleMemory(range = AddrRange('64MB'),
744 conf_table_reported = False)
745 self.nvmem.port = mem_bus.master
746 if not cur_sys.boot_loader:
747 cur_sys.boot_loader = loc('boot_emm.arm')
748 cur_sys.atags_addr = 0x8000000
749 cur_sys.load_addr_mask = 0xfffffff
750 cur_sys.load_offset = 0x80000000
751
752class VExpress_EMM64(VExpress_EMM):
753 # Three memory regions are specified totalling 512GB
754 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
755 (Addr('512GB'), Addr('480GB'))]
756 pci_host = GenericPciHost(
757 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
758 pci_pio_base=0x2f000000)
759
760 def setupBootLoader(self, mem_bus, cur_sys, loc):
761 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
762 conf_table_reported=False)
763 self.nvmem.port = mem_bus.master
764 if not cur_sys.boot_loader:
765 cur_sys.boot_loader = loc('boot_emm.arm64')
766 cur_sys.atags_addr = 0x8000000
767 cur_sys.load_addr_mask = 0xfffffff
768 cur_sys.load_offset = 0x80000000
769
770
771class VExpress_GEM5_V1(RealView):
772 """
773The VExpress gem5 memory map is loosely based on a modified
774Versatile Express RS1 memory map.
775
776The gem5 platform has been designed to implement a subset of the
777original Versatile Express RS1 memory map. Off-chip peripherals should,
778when possible, adhere to the Versatile Express memory map. Non-PCI
779off-chip devices that are gem5-specific should live in the CS5 memory
780space to avoid conflicts with existing devices that we might want to
781model in the future. Such devices should normally have interrupts in
782the gem5-specific SPI range.
783
784On-chip peripherals are loosely modeled after the ARM CoreTile Express
785A15x2 A7x3 memory and interrupt map. In particular, the GIC and
786Generic Timer have the same interrupt lines and base addresses. Other
787on-chip devices are gem5 specific.
788
789Unlike the original Versatile Express RS2 extended platform, gem5 implements a
790large contigious DRAM space, without aliases or holes, starting at the
7912GiB boundary. This means that PCI memory is limited to 1GiB.
792
793Memory map:
794 0x00000000-0x03ffffff: Boot memory (CS0)
795 0x04000000-0x07ffffff: Reserved
796 0x08000000-0x0bffffff: Reserved (CS0 alias)
797 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4)
798 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
799 0x10000000-0x1000ffff: gem5 energy controller
800 0x10010000-0x1001ffff: gem5 pseudo-ops
801
802 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1)
803 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2)
804 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3):
805 0x1c010000-0x1c01ffff: realview_io (VE system control regs.)
806 0x1c060000-0x1c06ffff: KMI0 (keyboard)
807 0x1c070000-0x1c07ffff: KMI1 (mouse)
808 0x1c090000-0x1c09ffff: UART0
809 0x1c0a0000-0x1c0affff: UART1 (reserved)
810 0x1c0b0000-0x1c0bffff: UART2 (reserved)
811 0x1c0c0000-0x1c0cffff: UART3 (reserved)
812 0x1c170000-0x1c17ffff: RTC
813
814 0x20000000-0x3fffffff: On-chip peripherals:
815 0x2b000000-0x2b00ffff: HDLCD
816
817 0x2c001000-0x2c001fff: GIC (distributor)
818 0x2c002000-0x2c0020ff: GIC (CPU interface)
819 0x2c004000-0x2c005fff: vGIC (HV)
820 0x2c006000-0x2c007fff: vGIC (VCPU)
821 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0
822
823 0x2d000000-0x2d00ffff: GPU (reserved)
824
825 0x2f000000-0x2fffffff: PCI IO space
826 0x30000000-0x3fffffff: PCI config space
827
828 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory
829
830 0x80000000-X: DRAM
831
832Interrupts:
833 0- 15: Software generated interrupts (SGIs)
834 16- 31: On-chip private peripherals (PPIs)
835 25 : vgic
836 26 : generic_timer (hyp)
837 27 : generic_timer (virt)
838 28 : Reserved (Legacy FIQ)
839 29 : generic_timer (phys, sec)
840 30 : generic_timer (phys, non-sec)
841 31 : Reserved (Legacy IRQ)
842 32- 95: Mother board peripherals (SPIs)
843 32 : Reserved (SP805)
844 33 : Reserved (IOFPGA SW int)
845 34-35: Reserved (SP804)
846 36 : RTC
847 37-40: uart0-uart3
848 41-42: Reserved (PL180)
849 43 : Reserved (AACI)
850 44-45: kmi0-kmi1
851 46 : Reserved (CLCD)
852 47 : Reserved (Ethernet)
853 48 : Reserved (USB)
854 95-255: On-chip interrupt sources (we use these for
855 gem5-specific devices, SPIs)
856 95 : HDLCD
857 96- 98: GPU (reserved)
858 100-103: PCI
859 256-319: MSI frame 0 (gem5-specific, SPIs)
860 320-511: Unused
861
862 """
863
864 # Everything above 2GiB is memory
865 _mem_regions = [(Addr('2GB'), Addr('510GB'))]
866
867 _off_chip_ranges = [
868 # CS1-CS5
869 AddrRange(0x0c000000, 0x1fffffff),
870 # External AXI interface (PCI)
871 AddrRange(0x2f000000, 0x7fffffff),
872 ]
873
874 # Platform control device (off-chip)
875 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
876 idreg=0x02250000, pio_addr=0x1c010000)
877 mcc = VExpressMCC()
878 dcc = CoreTile2A15DCC()
879
880 ### On-chip devices ###
881 gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000,
882 it_lines=512)
883 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
884 gicv2m = Gicv2m()
885 gicv2m.frames = [
886 Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000),
887 ]
888
889 generic_timer = GenericTimer(int_phys=29, int_virt=27)
890
891 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
892 pio_addr=0x2b000000, int_num=95)
893
894 def _on_chip_devices(self):
895 return [
896 self.gic, self.vgic, self.gicv2m,
897 self.hdlcd,
898 self.generic_timer,
899 ]
900
901 ### Off-chip devices ###
902 uart0 = Pl011(pio_addr=0x1c090000, int_num=37)
903
904 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
905 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
906
907 rtc = PL031(pio_addr=0x1c170000, int_num=36)
908
909 ### gem5-specific off-chip devices ###
910 pci_host = GenericArmPciHost(
911 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
912 pci_pio_base=0x2f000000,
913 int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
914
915 energy_ctrl = EnergyCtrl(pio_addr=0x10000000)
916
917
918 def _off_chip_devices(self):
919 return [
920 self.realview_io,
921 self.uart0,
922 self.kmi0, self.kmi1,
923 self.rtc,
924 self.pci_host,
925 self.energy_ctrl,
926 ]
927
928 def attachPciDevice(self, device, *args, **kwargs):
929 device.host = self.pci_host
930 self._attach_device(device, *args, **kwargs)
931
932 def setupBootLoader(self, mem_bus, cur_sys, loc):
933 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
934 conf_table_reported=False)
935 self.nvmem.port = mem_bus.master
936 if not cur_sys.boot_loader:
937 cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ]
938 cur_sys.atags_addr = 0x8000000
939 # the old load_add_mask 0xfffffff works for 32-bit kernel
940 # but not the 64-bit one. The new value 0x7ffffff works for both
941 cur_sys.load_addr_mask = 0x7ffffff
942 cur_sys.load_offset = 0x80000000
943
944 # Setup m5ops. It's technically not a part of the boot
945 # loader, but this is the only place we can configure the
946 # system.
947 cur_sys.m5ops_base = 0x10010000
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40# Gabe Black
41# William Wang
42
43from m5.params import *
44from m5.proxy import *
45from ClockDomain import ClockDomain
46from VoltageDomain import VoltageDomain
47from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
48from PciHost import *
49from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
50from Ide import *
51from Platform import Platform
52from Terminal import Terminal
53from Uart import Uart
54from SimpleMemory import SimpleMemory
55from Gic import *
56from EnergyCtrl import EnergyCtrl
57from ClockDomain import SrcClockDomain
58from SubSystem import SubSystem
59from Graphics import ImageFormat
60
61# Platforms with KVM support should generally use in-kernel GIC
62# emulation. Use a GIC model that automatically switches between
63# gem5's GIC model and KVM's GIC model if KVM is available.
64try:
65 from KvmGic import MuxingKvmGic
66 kvm_gicv2_class = MuxingKvmGic
67except ImportError:
68 # KVM support wasn't compiled into gem5. Fallback to a
69 # software-only GIC.
70 kvm_gicv2_class = Pl390
71 pass
72
73class AmbaPioDevice(BasicPioDevice):
74 type = 'AmbaPioDevice'
75 abstract = True
76 cxx_header = "dev/arm/amba_device.hh"
77 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
78
79class AmbaIntDevice(AmbaPioDevice):
80 type = 'AmbaIntDevice'
81 abstract = True
82 cxx_header = "dev/arm/amba_device.hh"
83 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
84 int_num = Param.UInt32("Interrupt number that connects to GIC")
85 int_delay = Param.Latency("100ns",
86 "Time between action and interrupt generation by device")
87
88class AmbaDmaDevice(DmaDevice):
89 type = 'AmbaDmaDevice'
90 abstract = True
91 cxx_header = "dev/arm/amba_device.hh"
92 pio_addr = Param.Addr("Address for AMBA slave interface")
93 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
94 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
95 int_num = Param.UInt32("Interrupt number that connects to GIC")
96 amba_id = Param.UInt32("ID of AMBA device for kernel detection")
97
98class A9SCU(BasicPioDevice):
99 type = 'A9SCU'
100 cxx_header = "dev/arm/a9scu.hh"
101
102class ArmPciIntRouting(Enum): vals = [
103 'ARM_PCI_INT_STATIC',
104 'ARM_PCI_INT_DEV',
105 'ARM_PCI_INT_PIN',
106 ]
107
108class GenericArmPciHost(GenericPciHost):
109 type = 'GenericArmPciHost'
110 cxx_header = "dev/arm/pci_host.hh"
111
112 int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy")
113 int_base = Param.Unsigned("PCI interrupt base")
114 int_count = Param.Unsigned("Maximum number of interrupts used by this host")
115
116class RealViewCtrl(BasicPioDevice):
117 type = 'RealViewCtrl'
118 cxx_header = "dev/arm/rv_ctrl.hh"
119 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
120 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
121 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
122
123class RealViewOsc(ClockDomain):
124 type = 'RealViewOsc'
125 cxx_header = "dev/arm/rv_ctrl.hh"
126
127 parent = Param.RealViewCtrl(Parent.any, "RealView controller")
128
129 # TODO: We currently don't have the notion of a clock source,
130 # which means we have to associate oscillators with a voltage
131 # source.
132 voltage_domain = Param.VoltageDomain(Parent.voltage_domain,
133 "Voltage domain")
134
135 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
136 # the individual core/logic tile reference manuals for details
137 # about the site/position/dcc/device allocation.
138 site = Param.UInt8("Board Site")
139 position = Param.UInt8("Position in device stack")
140 dcc = Param.UInt8("Daughterboard Configuration Controller")
141 device = Param.UInt8("Device ID")
142
143 freq = Param.Clock("Default frequency")
144
145class RealViewTemperatureSensor(SimObject):
146 type = 'RealViewTemperatureSensor'
147 cxx_header = "dev/arm/rv_ctrl.hh"
148
149 parent = Param.RealViewCtrl(Parent.any, "RealView controller")
150
151 system = Param.System(Parent.any, "system")
152
153 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
154 # the individual core/logic tile reference manuals for details
155 # about the site/position/dcc/device allocation.
156 site = Param.UInt8("Board Site")
157 position = Param.UInt8("Position in device stack")
158 dcc = Param.UInt8("Daughterboard Configuration Controller")
159 device = Param.UInt8("Device ID")
160
161class VExpressMCC(SubSystem):
162 """ARM V2M-P1 Motherboard Configuration Controller
163
164This subsystem describes a subset of the devices that sit behind the
165motherboard configuration controller on the the ARM Motherboard
166Express (V2M-P1) motherboard. See ARM DUI 0447J for details.
167 """
168
169 class Osc(RealViewOsc):
170 site, position, dcc = (0, 0, 0)
171
172 class Temperature(RealViewTemperatureSensor):
173 site, position, dcc = (0, 0, 0)
174
175 osc_mcc = Osc(device=0, freq="50MHz")
176 osc_clcd = Osc(device=1, freq="23.75MHz")
177 osc_peripheral = Osc(device=2, freq="24MHz")
178 osc_system_bus = Osc(device=4, freq="24MHz")
179
180 # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM).
181 temp_crtl = Temperature(device=0)
182
183class CoreTile2A15DCC(SubSystem):
184 """ARM CoreTile Express A15x2 Daughterboard Configuration Controller
185
186This subsystem describes a subset of the devices that sit behind the
187daughterboard configuration controller on a CoreTile Express A15x2. See
188ARM DUI 0604E for details.
189 """
190
191 class Osc(RealViewOsc):
192 site, position, dcc = (1, 0, 0)
193
194 # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM)
195 osc_cpu = Osc(device=0, freq="60MHz")
196 osc_hsbm = Osc(device=4, freq="40MHz")
197 osc_pxl = Osc(device=5, freq="23.75MHz")
198 osc_smb = Osc(device=6, freq="50MHz")
199 osc_sys = Osc(device=7, freq="60MHz")
200 osc_ddr = Osc(device=8, freq="40MHz")
201
202class VGic(PioDevice):
203 type = 'VGic'
204 cxx_header = "dev/arm/vgic.hh"
205 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
206 platform = Param.Platform(Parent.any, "Platform this device is part of.")
207 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
208 hv_addr = Param.Addr(0, "Address for hv control")
209 pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
210 # The number of list registers is not currently configurable at runtime.
211 ppint = Param.UInt32("HV maintenance interrupt number")
212
213class AmbaFake(AmbaPioDevice):
214 type = 'AmbaFake'
215 cxx_header = "dev/arm/amba_fake.hh"
216 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
217 amba_id = 0;
218
219class Pl011(Uart):
220 type = 'Pl011'
221 cxx_header = "dev/arm/pl011.hh"
222 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
223 int_num = Param.UInt32("Interrupt number that connects to GIC")
224 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
225 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
226
227class Sp804(AmbaPioDevice):
228 type = 'Sp804'
229 cxx_header = "dev/arm/timer_sp804.hh"
230 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
231 int_num0 = Param.UInt32("Interrupt number that connects to GIC")
232 clock0 = Param.Clock('1MHz', "Clock speed of the input")
233 int_num1 = Param.UInt32("Interrupt number that connects to GIC")
234 clock1 = Param.Clock('1MHz', "Clock speed of the input")
235 amba_id = 0x00141804
236
237class A9GlobalTimer(BasicPioDevice):
238 type = 'A9GlobalTimer'
239 cxx_header = "dev/arm/timer_a9global.hh"
240 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
241 int_num = Param.UInt32("Interrrupt number that connects to GIC")
242
243class CpuLocalTimer(BasicPioDevice):
244 type = 'CpuLocalTimer'
245 cxx_header = "dev/arm/timer_cpulocal.hh"
246 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
247 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
248 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
249
250class GenericTimer(SimObject):
251 type = 'GenericTimer'
252 cxx_header = "dev/arm/generic_timer.hh"
253 system = Param.ArmSystem(Parent.any, "system")
254 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
255 # @todo: for now only two timers per CPU is supported, which is the
256 # normal behaviour when security extensions are disabled.
257 int_phys = Param.UInt32("Physical timer interrupt number")
258 int_virt = Param.UInt32("Virtual timer interrupt number")
259
260class GenericTimerMem(PioDevice):
261 type = 'GenericTimerMem'
262 cxx_header = "dev/arm/generic_timer.hh"
263 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
264
265 base = Param.Addr(0, "Base address")
266
267 int_phys = Param.UInt32("Interrupt number")
268 int_virt = Param.UInt32("Interrupt number")
269
270class PL031(AmbaIntDevice):
271 type = 'PL031'
272 cxx_header = "dev/arm/rtc_pl031.hh"
273 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
274 amba_id = 0x00341031
275
276class Pl050(AmbaIntDevice):
277 type = 'Pl050'
278 cxx_header = "dev/arm/kmi.hh"
279 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
280 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
281 int_delay = '1us'
282 amba_id = 0x00141050
283
284class Pl111(AmbaDmaDevice):
285 type = 'Pl111'
286 cxx_header = "dev/arm/pl111.hh"
287 pixel_clock = Param.Clock('24MHz', "Pixel clock")
288 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
289 amba_id = 0x00141111
290 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
291
292class HDLcd(AmbaDmaDevice):
293 type = 'HDLcd'
294 cxx_header = "dev/arm/hdlcd.hh"
295 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer "
296 "display")
297 amba_id = 0x00141000
298 workaround_swap_rb = Param.Bool(False, "Workaround incorrect color "
299 "selector order in some kernels")
300 workaround_dma_line_count = Param.Bool(True, "Workaround incorrect "
301 "DMA line count (off by 1)")
302 enable_capture = Param.Bool(True, "capture frame to "
303 "system.framebuffer.{extension}")
304 frame_format = Param.ImageFormat("Auto",
305 "image format of the captured frame")
306
307 pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range")
308
309 pxl_clk = Param.ClockDomain("Pixel clock source")
310 pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch")
311 virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate "
312 "in KVM mode")
313
314class RealView(Platform):
315 type = 'RealView'
316 cxx_header = "dev/arm/realview.hh"
317 system = Param.System(Parent.any, "system")
318 _mem_regions = [(Addr(0), Addr('256MB'))]
319
320 def _on_chip_devices(self):
321 return []
322
323 def _off_chip_devices(self):
324 return []
325
326 _off_chip_ranges = []
327
328 def _attach_device(self, device, bus, dma_ports=None):
329 if hasattr(device, "pio"):
330 device.pio = bus.master
331 if hasattr(device, "dma"):
332 if dma_ports is None:
333 device.dma = bus.slave
334 else:
335 dma_ports.append(device.dma)
336
337 def _attach_io(self, devices, *args, **kwargs):
338 for d in devices:
339 self._attach_device(d, *args, **kwargs)
340
341 def _attach_clk(self, devices, clkdomain):
342 for d in devices:
343 if hasattr(d, "clk_domain"):
344 d.clk_domain = clkdomain
345
346 def attachPciDevices(self):
347 pass
348
349 def enableMSIX(self):
350 pass
351
352 def onChipIOClkDomain(self, clkdomain):
353 self._attach_clk(self._on_chip_devices(), clkdomain)
354
355 def offChipIOClkDomain(self, clkdomain):
356 self._attach_clk(self._off_chip_devices(), clkdomain)
357
358 def attachOnChipIO(self, bus, bridge=None, *args, **kwargs):
359 self._attach_io(self._on_chip_devices(), bus, *args, **kwargs)
360 if bridge:
361 bridge.ranges = self._off_chip_ranges
362
363 def attachIO(self, *args, **kwargs):
364 self._attach_io(self._off_chip_devices(), *args, **kwargs)
365
366 def setupBootLoader(self, mem_bus, cur_sys, loc):
367 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
368 conf_table_reported = False)
369 self.nvmem.port = mem_bus.master
370 cur_sys.boot_loader = loc('boot.arm')
371 cur_sys.atags_addr = 0x100
372 cur_sys.load_addr_mask = 0xfffffff
373 cur_sys.load_offset = 0
374
375
376# Reference for memory map and interrupt number
377# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
378# Chapter 4: Programmer's Reference
379class RealViewPBX(RealView):
380 uart = Pl011(pio_addr=0x10009000, int_num=44)
381 realview_io = RealViewCtrl(pio_addr=0x10000000)
382 mcc = VExpressMCC()
383 dcc = CoreTile2A15DCC()
384 gic = Pl390()
385 pci_host = GenericPciHost(
386 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
387 pci_pio_base=0)
388 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
389 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
390 global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200)
391 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
392 pio_addr=0x1f000600)
393 clcd = Pl111(pio_addr=0x10020000, int_num=55)
394 kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
395 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
396 a9scu = A9SCU(pio_addr=0x1f000000)
397 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
398 io_shift = 1, ctrl_offset = 2, Command = 0x1,
399 BAR0 = 0x18000000, BAR0Size = '16B',
400 BAR1 = 0x18000100, BAR1Size = '1B',
401 BAR0LegacyIO = True, BAR1LegacyIO = True)
402
403
404 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
405 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
406 fake_mem=True)
407 dmac_fake = AmbaFake(pio_addr=0x10030000)
408 uart1_fake = AmbaFake(pio_addr=0x1000a000)
409 uart2_fake = AmbaFake(pio_addr=0x1000b000)
410 uart3_fake = AmbaFake(pio_addr=0x1000c000)
411 smc_fake = AmbaFake(pio_addr=0x100e1000)
412 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
413 watchdog_fake = AmbaFake(pio_addr=0x10010000)
414 gpio0_fake = AmbaFake(pio_addr=0x10013000)
415 gpio1_fake = AmbaFake(pio_addr=0x10014000)
416 gpio2_fake = AmbaFake(pio_addr=0x10015000)
417 ssp_fake = AmbaFake(pio_addr=0x1000d000)
418 sci_fake = AmbaFake(pio_addr=0x1000e000)
419 aaci_fake = AmbaFake(pio_addr=0x10004000)
420 mmc_fake = AmbaFake(pio_addr=0x10005000)
421 rtc = PL031(pio_addr=0x10017000, int_num=42)
422 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
423
424
425 # Attach I/O devices that are on chip and also set the appropriate
426 # ranges for the bridge
427 def attachOnChipIO(self, bus, bridge):
428 self.gic.pio = bus.master
429 self.l2x0_fake.pio = bus.master
430 self.a9scu.pio = bus.master
431 self.global_timer.pio = bus.master
432 self.local_cpu_timer.pio = bus.master
433 # Bridge ranges based on excluding what is part of on-chip I/O
434 # (gic, l2x0, a9scu, local_cpu_timer)
435 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
436 self.a9scu.pio_addr - 1),
437 AddrRange(self.flash_fake.pio_addr,
438 self.flash_fake.pio_addr + \
439 self.flash_fake.pio_size - 1)]
440
441 # Set the clock domain for IO objects that are considered
442 # to be "close" to the cores.
443 def onChipIOClkDomain(self, clkdomain):
444 self.gic.clk_domain = clkdomain
445 self.l2x0_fake.clk_domain = clkdomain
446 self.a9scu.clkdomain = clkdomain
447 self.local_cpu_timer.clk_domain = clkdomain
448
449 # Attach I/O devices to specified bus object. Can't do this
450 # earlier, since the bus object itself is typically defined at the
451 # System level.
452 def attachIO(self, bus):
453 self.uart.pio = bus.master
454 self.realview_io.pio = bus.master
455 self.pci_host.pio = bus.master
456 self.timer0.pio = bus.master
457 self.timer1.pio = bus.master
458 self.clcd.pio = bus.master
459 self.clcd.dma = bus.slave
460 self.kmi0.pio = bus.master
461 self.kmi1.pio = bus.master
462 self.cf_ctrl.pio = bus.master
463 self.cf_ctrl.dma = bus.slave
464 self.dmac_fake.pio = bus.master
465 self.uart1_fake.pio = bus.master
466 self.uart2_fake.pio = bus.master
467 self.uart3_fake.pio = bus.master
468 self.smc_fake.pio = bus.master
469 self.sp810_fake.pio = bus.master
470 self.watchdog_fake.pio = bus.master
471 self.gpio0_fake.pio = bus.master
472 self.gpio1_fake.pio = bus.master
473 self.gpio2_fake.pio = bus.master
474 self.ssp_fake.pio = bus.master
475 self.sci_fake.pio = bus.master
476 self.aaci_fake.pio = bus.master
477 self.mmc_fake.pio = bus.master
478 self.rtc.pio = bus.master
479 self.flash_fake.pio = bus.master
480 self.energy_ctrl.pio = bus.master
481
482 # Set the clock domain for IO objects that are considered
483 # to be "far" away from the cores.
484 def offChipIOClkDomain(self, clkdomain):
485 self.uart.clk_domain = clkdomain
486 self.realview_io.clk_domain = clkdomain
487 self.timer0.clk_domain = clkdomain
488 self.timer1.clk_domain = clkdomain
489 self.clcd.clk_domain = clkdomain
490 self.kmi0.clk_domain = clkdomain
491 self.kmi1.clk_domain = clkdomain
492 self.cf_ctrl.clk_domain = clkdomain
493 self.dmac_fake.clk_domain = clkdomain
494 self.uart1_fake.clk_domain = clkdomain
495 self.uart2_fake.clk_domain = clkdomain
496 self.uart3_fake.clk_domain = clkdomain
497 self.smc_fake.clk_domain = clkdomain
498 self.sp810_fake.clk_domain = clkdomain
499 self.watchdog_fake.clk_domain = clkdomain
500 self.gpio0_fake.clk_domain = clkdomain
501 self.gpio1_fake.clk_domain = clkdomain
502 self.gpio2_fake.clk_domain = clkdomain
503 self.ssp_fake.clk_domain = clkdomain
504 self.sci_fake.clk_domain = clkdomain
505 self.aaci_fake.clk_domain = clkdomain
506 self.mmc_fake.clk_domain = clkdomain
507 self.rtc.clk_domain = clkdomain
508 self.flash_fake.clk_domain = clkdomain
509 self.energy_ctrl.clk_domain = clkdomain
510
511# Reference for memory map and interrupt number
512# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
513# Chapter 4: Programmer's Reference
514class RealViewEB(RealView):
515 uart = Pl011(pio_addr=0x10009000, int_num=44)
516 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
517 mcc = VExpressMCC()
518 dcc = CoreTile2A15DCC()
519 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
520 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
521 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
522 clcd = Pl111(pio_addr=0x10020000, int_num=23)
523 kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
524 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
525
526 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
527 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
528 fake_mem=True)
529 dmac_fake = AmbaFake(pio_addr=0x10030000)
530 uart1_fake = AmbaFake(pio_addr=0x1000a000)
531 uart2_fake = AmbaFake(pio_addr=0x1000b000)
532 uart3_fake = AmbaFake(pio_addr=0x1000c000)
533 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
534 smc_fake = AmbaFake(pio_addr=0x100e1000)
535 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
536 watchdog_fake = AmbaFake(pio_addr=0x10010000)
537 gpio0_fake = AmbaFake(pio_addr=0x10013000)
538 gpio1_fake = AmbaFake(pio_addr=0x10014000)
539 gpio2_fake = AmbaFake(pio_addr=0x10015000)
540 ssp_fake = AmbaFake(pio_addr=0x1000d000)
541 sci_fake = AmbaFake(pio_addr=0x1000e000)
542 aaci_fake = AmbaFake(pio_addr=0x10004000)
543 mmc_fake = AmbaFake(pio_addr=0x10005000)
544 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
545 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
546
547 # Attach I/O devices that are on chip and also set the appropriate
548 # ranges for the bridge
549 def attachOnChipIO(self, bus, bridge):
550 self.gic.pio = bus.master
551 self.l2x0_fake.pio = bus.master
552 # Bridge ranges based on excluding what is part of on-chip I/O
553 # (gic, l2x0)
554 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
555 self.gic.cpu_addr - 1),
556 AddrRange(self.flash_fake.pio_addr, Addr.max)]
557
558 # Set the clock domain for IO objects that are considered
559 # to be "close" to the cores.
560 def onChipIOClkDomain(self, clkdomain):
561 self.gic.clk_domain = clkdomain
562 self.l2x0_fake.clk_domain = clkdomain
563
564 # Attach I/O devices to specified bus object. Can't do this
565 # earlier, since the bus object itself is typically defined at the
566 # System level.
567 def attachIO(self, bus):
568 self.uart.pio = bus.master
569 self.realview_io.pio = bus.master
570 self.pci_host.pio = bus.master
571 self.timer0.pio = bus.master
572 self.timer1.pio = bus.master
573 self.clcd.pio = bus.master
574 self.clcd.dma = bus.slave
575 self.kmi0.pio = bus.master
576 self.kmi1.pio = bus.master
577 self.dmac_fake.pio = bus.master
578 self.uart1_fake.pio = bus.master
579 self.uart2_fake.pio = bus.master
580 self.uart3_fake.pio = bus.master
581 self.smc_fake.pio = bus.master
582 self.sp810_fake.pio = bus.master
583 self.watchdog_fake.pio = bus.master
584 self.gpio0_fake.pio = bus.master
585 self.gpio1_fake.pio = bus.master
586 self.gpio2_fake.pio = bus.master
587 self.ssp_fake.pio = bus.master
588 self.sci_fake.pio = bus.master
589 self.aaci_fake.pio = bus.master
590 self.mmc_fake.pio = bus.master
591 self.rtc_fake.pio = bus.master
592 self.flash_fake.pio = bus.master
593 self.smcreg_fake.pio = bus.master
594 self.energy_ctrl.pio = bus.master
595
596 # Set the clock domain for IO objects that are considered
597 # to be "far" away from the cores.
598 def offChipIOClkDomain(self, clkdomain):
599 self.uart.clk_domain = clkdomain
600 self.realview_io.clk_domain = clkdomain
601 self.timer0.clk_domain = clkdomain
602 self.timer1.clk_domain = clkdomain
603 self.clcd.clk_domain = clkdomain
604 self.kmi0.clk_domain = clkdomain
605 self.kmi1.clk_domain = clkdomain
606 self.dmac_fake.clk_domain = clkdomain
607 self.uart1_fake.clk_domain = clkdomain
608 self.uart2_fake.clk_domain = clkdomain
609 self.uart3_fake.clk_domain = clkdomain
610 self.smc_fake.clk_domain = clkdomain
611 self.sp810_fake.clk_domain = clkdomain
612 self.watchdog_fake.clk_domain = clkdomain
613 self.gpio0_fake.clk_domain = clkdomain
614 self.gpio1_fake.clk_domain = clkdomain
615 self.gpio2_fake.clk_domain = clkdomain
616 self.ssp_fake.clk_domain = clkdomain
617 self.sci_fake.clk_domain = clkdomain
618 self.aaci_fake.clk_domain = clkdomain
619 self.mmc_fake.clk_domain = clkdomain
620 self.rtc.clk_domain = clkdomain
621 self.flash_fake.clk_domain = clkdomain
622 self.smcreg_fake.clk_domain = clkdomain
623 self.energy_ctrl.clk_domain = clkdomain
624
625class VExpress_EMM(RealView):
626 _mem_regions = [(Addr('2GB'), Addr('2GB'))]
627
628 # Ranges based on excluding what is part of on-chip I/O (gic,
629 # a9scu)
630 _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'),
631 AddrRange(0x30000000, size='256MB'),
632 AddrRange(0x40000000, size='512MB'),
633 AddrRange(0x18000000, size='64MB'),
634 AddrRange(0x1C000000, size='64MB')]
635
636 # Platform control device (off-chip)
637 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
638 idreg=0x02250000, pio_addr=0x1C010000)
639
640 mcc = VExpressMCC()
641 dcc = CoreTile2A15DCC()
642
643 ### On-chip devices ###
644 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
645 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
646
647 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
648 pio_addr=0x2C080000)
649
650 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
651 pio_addr=0x2b000000, int_num=117,
652 workaround_swap_rb=True)
653
654 def _on_chip_devices(self):
655 devices = [
656 self.gic, self.vgic,
657 self.local_cpu_timer
658 ]
659 if hasattr(self, "gicv2m"):
660 devices.append(self.gicv2m)
661 devices.append(self.hdlcd)
662 return devices
663
664 ### Off-chip devices ###
665 uart = Pl011(pio_addr=0x1c090000, int_num=37)
666 pci_host = GenericPciHost(
667 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
668 pci_pio_base=0)
669
670 generic_timer = GenericTimer(int_phys=29, int_virt=27)
671 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
672 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
673 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
674 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
675 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
676 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
677 io_shift = 2, ctrl_offset = 2, Command = 0x1,
678 BAR0 = 0x1C1A0000, BAR0Size = '256B',
679 BAR1 = 0x1C1A0100, BAR1Size = '4096B',
680 BAR0LegacyIO = True, BAR1LegacyIO = True)
681
682 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
683 conf_table_reported = False)
684 rtc = PL031(pio_addr=0x1C170000, int_num=36)
685
686 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
687 uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
688 uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
689 uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
690 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
691 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
692 aaci_fake = AmbaFake(pio_addr=0x1C040000)
693 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
694 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
695 mmc_fake = AmbaFake(pio_addr=0x1c050000)
696 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000)
697
698 def _off_chip_devices(self):
699 devices = [
700 self.uart,
701 self.realview_io,
702 self.pci_host,
703 self.timer0,
704 self.timer1,
705 self.clcd,
706 self.kmi0,
707 self.kmi1,
708 self.cf_ctrl,
709 self.rtc,
710 self.vram,
711 self.l2x0_fake,
712 self.uart1_fake,
713 self.uart2_fake,
714 self.uart3_fake,
715 self.sp810_fake,
716 self.watchdog_fake,
717 self.aaci_fake,
718 self.lan_fake,
719 self.usb_fake,
720 self.mmc_fake,
721 self.energy_ctrl,
722 ]
723 # Try to attach the I/O if it exists
724 if hasattr(self, "ide"):
725 devices.append(self.ide)
726 if hasattr(self, "ethernet"):
727 devices.append(self.ethernet)
728 return devices
729
730 # Attach any PCI devices that are supported
731 def attachPciDevices(self):
732 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
733 InterruptLine=1, InterruptPin=1)
734 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
735 InterruptLine=2, InterruptPin=2)
736
737 def enableMSIX(self):
738 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
739 self.gicv2m = Gicv2m()
740 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
741
742 def setupBootLoader(self, mem_bus, cur_sys, loc):
743 self.nvmem = SimpleMemory(range = AddrRange('64MB'),
744 conf_table_reported = False)
745 self.nvmem.port = mem_bus.master
746 if not cur_sys.boot_loader:
747 cur_sys.boot_loader = loc('boot_emm.arm')
748 cur_sys.atags_addr = 0x8000000
749 cur_sys.load_addr_mask = 0xfffffff
750 cur_sys.load_offset = 0x80000000
751
752class VExpress_EMM64(VExpress_EMM):
753 # Three memory regions are specified totalling 512GB
754 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
755 (Addr('512GB'), Addr('480GB'))]
756 pci_host = GenericPciHost(
757 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
758 pci_pio_base=0x2f000000)
759
760 def setupBootLoader(self, mem_bus, cur_sys, loc):
761 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
762 conf_table_reported=False)
763 self.nvmem.port = mem_bus.master
764 if not cur_sys.boot_loader:
765 cur_sys.boot_loader = loc('boot_emm.arm64')
766 cur_sys.atags_addr = 0x8000000
767 cur_sys.load_addr_mask = 0xfffffff
768 cur_sys.load_offset = 0x80000000
769
770
771class VExpress_GEM5_V1(RealView):
772 """
773The VExpress gem5 memory map is loosely based on a modified
774Versatile Express RS1 memory map.
775
776The gem5 platform has been designed to implement a subset of the
777original Versatile Express RS1 memory map. Off-chip peripherals should,
778when possible, adhere to the Versatile Express memory map. Non-PCI
779off-chip devices that are gem5-specific should live in the CS5 memory
780space to avoid conflicts with existing devices that we might want to
781model in the future. Such devices should normally have interrupts in
782the gem5-specific SPI range.
783
784On-chip peripherals are loosely modeled after the ARM CoreTile Express
785A15x2 A7x3 memory and interrupt map. In particular, the GIC and
786Generic Timer have the same interrupt lines and base addresses. Other
787on-chip devices are gem5 specific.
788
789Unlike the original Versatile Express RS2 extended platform, gem5 implements a
790large contigious DRAM space, without aliases or holes, starting at the
7912GiB boundary. This means that PCI memory is limited to 1GiB.
792
793Memory map:
794 0x00000000-0x03ffffff: Boot memory (CS0)
795 0x04000000-0x07ffffff: Reserved
796 0x08000000-0x0bffffff: Reserved (CS0 alias)
797 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4)
798 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
799 0x10000000-0x1000ffff: gem5 energy controller
800 0x10010000-0x1001ffff: gem5 pseudo-ops
801
802 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1)
803 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2)
804 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3):
805 0x1c010000-0x1c01ffff: realview_io (VE system control regs.)
806 0x1c060000-0x1c06ffff: KMI0 (keyboard)
807 0x1c070000-0x1c07ffff: KMI1 (mouse)
808 0x1c090000-0x1c09ffff: UART0
809 0x1c0a0000-0x1c0affff: UART1 (reserved)
810 0x1c0b0000-0x1c0bffff: UART2 (reserved)
811 0x1c0c0000-0x1c0cffff: UART3 (reserved)
812 0x1c170000-0x1c17ffff: RTC
813
814 0x20000000-0x3fffffff: On-chip peripherals:
815 0x2b000000-0x2b00ffff: HDLCD
816
817 0x2c001000-0x2c001fff: GIC (distributor)
818 0x2c002000-0x2c0020ff: GIC (CPU interface)
819 0x2c004000-0x2c005fff: vGIC (HV)
820 0x2c006000-0x2c007fff: vGIC (VCPU)
821 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0
822
823 0x2d000000-0x2d00ffff: GPU (reserved)
824
825 0x2f000000-0x2fffffff: PCI IO space
826 0x30000000-0x3fffffff: PCI config space
827
828 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory
829
830 0x80000000-X: DRAM
831
832Interrupts:
833 0- 15: Software generated interrupts (SGIs)
834 16- 31: On-chip private peripherals (PPIs)
835 25 : vgic
836 26 : generic_timer (hyp)
837 27 : generic_timer (virt)
838 28 : Reserved (Legacy FIQ)
839 29 : generic_timer (phys, sec)
840 30 : generic_timer (phys, non-sec)
841 31 : Reserved (Legacy IRQ)
842 32- 95: Mother board peripherals (SPIs)
843 32 : Reserved (SP805)
844 33 : Reserved (IOFPGA SW int)
845 34-35: Reserved (SP804)
846 36 : RTC
847 37-40: uart0-uart3
848 41-42: Reserved (PL180)
849 43 : Reserved (AACI)
850 44-45: kmi0-kmi1
851 46 : Reserved (CLCD)
852 47 : Reserved (Ethernet)
853 48 : Reserved (USB)
854 95-255: On-chip interrupt sources (we use these for
855 gem5-specific devices, SPIs)
856 95 : HDLCD
857 96- 98: GPU (reserved)
858 100-103: PCI
859 256-319: MSI frame 0 (gem5-specific, SPIs)
860 320-511: Unused
861
862 """
863
864 # Everything above 2GiB is memory
865 _mem_regions = [(Addr('2GB'), Addr('510GB'))]
866
867 _off_chip_ranges = [
868 # CS1-CS5
869 AddrRange(0x0c000000, 0x1fffffff),
870 # External AXI interface (PCI)
871 AddrRange(0x2f000000, 0x7fffffff),
872 ]
873
874 # Platform control device (off-chip)
875 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
876 idreg=0x02250000, pio_addr=0x1c010000)
877 mcc = VExpressMCC()
878 dcc = CoreTile2A15DCC()
879
880 ### On-chip devices ###
881 gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000,
882 it_lines=512)
883 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
884 gicv2m = Gicv2m()
885 gicv2m.frames = [
886 Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000),
887 ]
888
889 generic_timer = GenericTimer(int_phys=29, int_virt=27)
890
891 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
892 pio_addr=0x2b000000, int_num=95)
893
894 def _on_chip_devices(self):
895 return [
896 self.gic, self.vgic, self.gicv2m,
897 self.hdlcd,
898 self.generic_timer,
899 ]
900
901 ### Off-chip devices ###
902 uart0 = Pl011(pio_addr=0x1c090000, int_num=37)
903
904 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
905 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
906
907 rtc = PL031(pio_addr=0x1c170000, int_num=36)
908
909 ### gem5-specific off-chip devices ###
910 pci_host = GenericArmPciHost(
911 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
912 pci_pio_base=0x2f000000,
913 int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
914
915 energy_ctrl = EnergyCtrl(pio_addr=0x10000000)
916
917
918 def _off_chip_devices(self):
919 return [
920 self.realview_io,
921 self.uart0,
922 self.kmi0, self.kmi1,
923 self.rtc,
924 self.pci_host,
925 self.energy_ctrl,
926 ]
927
928 def attachPciDevice(self, device, *args, **kwargs):
929 device.host = self.pci_host
930 self._attach_device(device, *args, **kwargs)
931
932 def setupBootLoader(self, mem_bus, cur_sys, loc):
933 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
934 conf_table_reported=False)
935 self.nvmem.port = mem_bus.master
936 if not cur_sys.boot_loader:
937 cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ]
938 cur_sys.atags_addr = 0x8000000
939 # the old load_add_mask 0xfffffff works for 32-bit kernel
940 # but not the 64-bit one. The new value 0x7ffffff works for both
941 cur_sys.load_addr_mask = 0x7ffffff
942 cur_sys.load_offset = 0x80000000
943
944 # Setup m5ops. It's technically not a part of the boot
945 # loader, but this is the only place we can configure the
946 # system.
947 cur_sys.m5ops_base = 0x10010000