Gic.py (13996:8a567118e670) Gic.py (14152:72230d99538e)
1# Copyright (c) 2012-2013, 2017-2019 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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43from m5.objects.Device import PioDevice, BasicPioDevice
44from m5.objects.Platform import Platform
45
46class BaseGic(PioDevice):
47 type = 'BaseGic'
48 abstract = True
49 cxx_header = "dev/arm/base_gic.hh"
50
1# Copyright (c) 2012-2013, 2017-2019 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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43from m5.objects.Device import PioDevice, BasicPioDevice
44from m5.objects.Platform import Platform
45
46class BaseGic(PioDevice):
47 type = 'BaseGic'
48 abstract = True
49 cxx_header = "dev/arm/base_gic.hh"
50
51 # Used for DTB autogeneration
52 _state = FdtState(addr_cells=0, interrupt_cells=3)
53
51 platform = Param.Platform(Parent.any, "Platform this device is part of.")
52
53 gicd_iidr = Param.UInt32(0,
54 "Distributor Implementer Identification Register")
55 gicd_pidr = Param.UInt32(0,
56 "Peripheral Identification Register")
57 gicc_iidr = Param.UInt32(0,
58 "CPU Interface Identification Register")
59 gicv_iidr = Param.UInt32(0,
60 "VM CPU Interface Identification Register")
61
54 platform = Param.Platform(Parent.any, "Platform this device is part of.")
55
56 gicd_iidr = Param.UInt32(0,
57 "Distributor Implementer Identification Register")
58 gicd_pidr = Param.UInt32(0,
59 "Peripheral Identification Register")
60 gicc_iidr = Param.UInt32(0,
61 "CPU Interface Identification Register")
62 gicv_iidr = Param.UInt32(0,
63 "VM CPU Interface Identification Register")
64
65 def interruptCells(self, int_type, int_num, int_flag):
66 """
67 Interupt cells generation helper:
68 Following specifications described in
69
70 Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
71 """
72 assert self._state.interrupt_cells == 3
73 return [ int_type, int_num, int_flag ]
74
62class ArmInterruptPin(SimObject):
63 type = 'ArmInterruptPin'
64 cxx_header = "dev/arm/base_gic.hh"
65 cxx_class = "ArmInterruptPinGen"
66 abstract = True
67
68 platform = Param.Platform(Parent.any, "Platform with interrupt controller")
69 num = Param.UInt32("Interrupt number in GIC")

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135 "VM CPU Interface Identification Register")
136
137 def generateDeviceTree(self, state):
138 gic = self.gic.unproxy(self)
139
140 node = FdtNode("interrupt-controller")
141 node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic",
142 "arm,cortex-a9-gic"])
75class ArmInterruptPin(SimObject):
76 type = 'ArmInterruptPin'
77 cxx_header = "dev/arm/base_gic.hh"
78 cxx_class = "ArmInterruptPinGen"
79 abstract = True
80
81 platform = Param.Platform(Parent.any, "Platform with interrupt controller")
82 num = Param.UInt32("Interrupt number in GIC")

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148 "VM CPU Interface Identification Register")
149
150 def generateDeviceTree(self, state):
151 gic = self.gic.unproxy(self)
152
153 node = FdtNode("interrupt-controller")
154 node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic",
155 "arm,cortex-a9-gic"])
143 node.append(FdtPropertyWords("#interrupt-cells", [3]))
144 node.append(FdtPropertyWords("#address-cells", [0]))
156 node.append(gic._state.interruptCellsProperty())
157 node.append(gic._state.addrCellsProperty())
145 node.append(FdtProperty("interrupt-controller"))
146
147 regs = (
148 state.addrCells(gic.dist_addr) +
149 state.sizeCells(0x1000) +
150 state.addrCells(gic.cpu_addr) +
151 state.sizeCells(0x1000) +
152 state.addrCells(self.hv_addr) +

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173 # Devbits [17:13] = 0b100011: ITS supports 23 DeviceID bits
174 # ID_bits [12:8] = 0b11111: ITS supports 31 EventID bits
175 gits_typer = Param.UInt64(0x30023F01, "GITS_TYPER RO value")
176
177class Gicv3(BaseGic):
178 type = 'Gicv3'
179 cxx_header = "dev/arm/gic_v3.hh"
180
158 node.append(FdtProperty("interrupt-controller"))
159
160 regs = (
161 state.addrCells(gic.dist_addr) +
162 state.sizeCells(0x1000) +
163 state.addrCells(gic.cpu_addr) +
164 state.sizeCells(0x1000) +
165 state.addrCells(self.hv_addr) +

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186 # Devbits [17:13] = 0b100011: ITS supports 23 DeviceID bits
187 # ID_bits [12:8] = 0b11111: ITS supports 31 EventID bits
188 gits_typer = Param.UInt64(0x30023F01, "GITS_TYPER RO value")
189
190class Gicv3(BaseGic):
191 type = 'Gicv3'
192 cxx_header = "dev/arm/gic_v3.hh"
193
194 # Used for DTB autogeneration
195 _state = FdtState(addr_cells=2, interrupt_cells=3)
196
181 its = Param.Gicv3Its(Gicv3Its(), "GICv3 Interrupt Translation Service")
182
183 dist_addr = Param.Addr("Address for distributor")
184 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
185 redist_addr = Param.Addr("Address for redistributors")
186 redist_pio_delay = Param.Latency('10ns',
187 "Delay for PIO r/w to redistributors")
188 it_lines = Param.UInt32(1020,

--- 12 unchanged lines hidden --- 		197 its = Param.Gicv3Its(Gicv3Its(), "GICv3 Interrupt Translation Service")
198
199 dist_addr = Param.Addr("Address for distributor")
200 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
201 redist_addr = Param.Addr("Address for redistributors")
202 redist_pio_delay = Param.Latency('10ns',
203 "Delay for PIO r/w to redistributors")
204 it_lines = Param.UInt32(1020,

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