1# Copyright (c) 2012-2013, 2017-2019 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 34 unchanged lines hidden (view full) --- 43from m5.objects.Device import PioDevice, BasicPioDevice 44from m5.objects.Platform import Platform 45 46class BaseGic(PioDevice): 47 type = 'BaseGic' 48 abstract = True 49 cxx_header = "dev/arm/base_gic.hh" 50 |
51 # Used for DTB autogeneration 52 _state = FdtState(addr_cells=0, interrupt_cells=3) 53 |
54 platform = Param.Platform(Parent.any, "Platform this device is part of.") 55 56 gicd_iidr = Param.UInt32(0, 57 "Distributor Implementer Identification Register") 58 gicd_pidr = Param.UInt32(0, 59 "Peripheral Identification Register") 60 gicc_iidr = Param.UInt32(0, 61 "CPU Interface Identification Register") 62 gicv_iidr = Param.UInt32(0, 63 "VM CPU Interface Identification Register") 64 |
65 def interruptCells(self, int_type, int_num, int_flag): 66 """ 67 Interupt cells generation helper: 68 Following specifications described in 69 70 Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt 71 """ 72 assert self._state.interrupt_cells == 3 73 return [ int_type, int_num, int_flag ] 74 |
75class ArmInterruptPin(SimObject): 76 type = 'ArmInterruptPin' 77 cxx_header = "dev/arm/base_gic.hh" 78 cxx_class = "ArmInterruptPinGen" 79 abstract = True 80 81 platform = Param.Platform(Parent.any, "Platform with interrupt controller") 82 num = Param.UInt32("Interrupt number in GIC") --- 65 unchanged lines hidden (view full) --- 148 "VM CPU Interface Identification Register") 149 150 def generateDeviceTree(self, state): 151 gic = self.gic.unproxy(self) 152 153 node = FdtNode("interrupt-controller") 154 node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic", 155 "arm,cortex-a9-gic"]) |
156 node.append(gic._state.interruptCellsProperty()) 157 node.append(gic._state.addrCellsProperty()) |
158 node.append(FdtProperty("interrupt-controller")) 159 160 regs = ( 161 state.addrCells(gic.dist_addr) + 162 state.sizeCells(0x1000) + 163 state.addrCells(gic.cpu_addr) + 164 state.sizeCells(0x1000) + 165 state.addrCells(self.hv_addr) + --- 20 unchanged lines hidden (view full) --- 186 # Devbits [17:13] = 0b100011: ITS supports 23 DeviceID bits 187 # ID_bits [12:8] = 0b11111: ITS supports 31 EventID bits 188 gits_typer = Param.UInt64(0x30023F01, "GITS_TYPER RO value") 189 190class Gicv3(BaseGic): 191 type = 'Gicv3' 192 cxx_header = "dev/arm/gic_v3.hh" 193 |
194 # Used for DTB autogeneration 195 _state = FdtState(addr_cells=2, interrupt_cells=3) 196 |
197 its = Param.Gicv3Its(Gicv3Its(), "GICv3 Interrupt Translation Service") 198 199 dist_addr = Param.Addr("Address for distributor") 200 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 201 redist_addr = Param.Addr("Address for redistributors") 202 redist_pio_delay = Param.Latency('10ns', 203 "Delay for PIO r/w to redistributors") 204 it_lines = Param.UInt32(1020, --- 12 unchanged lines hidden --- |