1# Copyright (c) 2012-2013, 2017-2018 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37
38from m5.params import *
39from m5.proxy import *
40from m5.SimObject import SimObject
41
42from Device import PioDevice
43from Platform import Platform
44
45class BaseGic(PioDevice):
46 type = 'BaseGic'
47 abstract = True
48 cxx_header = "dev/arm/base_gic.hh"
49
50 platform = Param.Platform(Parent.any, "Platform this device is part of.")
51
52class ArmInterruptPin(SimObject):
53 type = 'ArmInterruptPin'
54 cxx_header = "dev/arm/base_gic.hh"
55 cxx_class = "ArmInterruptPinGen"
56 abstract = True
57
58 platform = Param.Platform(Parent.any, "Platform with interrupt controller")
59 num = Param.UInt32("Interrupt number in GIC")
60
61class ArmSPI(ArmInterruptPin):
62 type = 'ArmSPI'
63 cxx_header = "dev/arm/base_gic.hh"
64 cxx_class = "ArmSPIGen"
65
66class ArmPPI(ArmInterruptPin):
67 type = 'ArmPPI'
68 cxx_header = "dev/arm/base_gic.hh"
69 cxx_class = "ArmPPIGen"
70
71class GicV2(BaseGic):
72 type = 'GicV2'
73 cxx_header = "dev/arm/gic_v2.hh"
74
75 dist_addr = Param.Addr("Address for distributor")
76 cpu_addr = Param.Addr("Address for cpu")
77 cpu_size = Param.Addr(0x2000, "Size of cpu register bank")
78 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
79 cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
80 int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
81 it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
82 gem5_extensions = Param.Bool(False, "Enable gem5 extensions")
83
84class Gicv2mFrame(SimObject):
85 type = 'Gicv2mFrame'
86 cxx_header = "dev/arm/gic_v2m.hh"
87 spi_base = Param.UInt32(0x0, "Frame SPI base number");
88 spi_len = Param.UInt32(0x0, "Frame SPI total number");
89 addr = Param.Addr("Address for frame PIO")
90
91class Gicv2m(PioDevice):
92 type = 'Gicv2m'
93 cxx_header = "dev/arm/gic_v2m.hh"
94
95 pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
96 gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts")
97 frames = VectorParam.Gicv2mFrame([], "Power of two number of frames")
| 1# Copyright (c) 2012-2013, 2017-2018 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37
38from m5.params import *
39from m5.proxy import *
40from m5.SimObject import SimObject
41
42from Device import PioDevice
43from Platform import Platform
44
45class BaseGic(PioDevice):
46 type = 'BaseGic'
47 abstract = True
48 cxx_header = "dev/arm/base_gic.hh"
49
50 platform = Param.Platform(Parent.any, "Platform this device is part of.")
51
52class ArmInterruptPin(SimObject):
53 type = 'ArmInterruptPin'
54 cxx_header = "dev/arm/base_gic.hh"
55 cxx_class = "ArmInterruptPinGen"
56 abstract = True
57
58 platform = Param.Platform(Parent.any, "Platform with interrupt controller")
59 num = Param.UInt32("Interrupt number in GIC")
60
61class ArmSPI(ArmInterruptPin):
62 type = 'ArmSPI'
63 cxx_header = "dev/arm/base_gic.hh"
64 cxx_class = "ArmSPIGen"
65
66class ArmPPI(ArmInterruptPin):
67 type = 'ArmPPI'
68 cxx_header = "dev/arm/base_gic.hh"
69 cxx_class = "ArmPPIGen"
70
71class GicV2(BaseGic):
72 type = 'GicV2'
73 cxx_header = "dev/arm/gic_v2.hh"
74
75 dist_addr = Param.Addr("Address for distributor")
76 cpu_addr = Param.Addr("Address for cpu")
77 cpu_size = Param.Addr(0x2000, "Size of cpu register bank")
78 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
79 cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
80 int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
81 it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
82 gem5_extensions = Param.Bool(False, "Enable gem5 extensions")
83
84class Gicv2mFrame(SimObject):
85 type = 'Gicv2mFrame'
86 cxx_header = "dev/arm/gic_v2m.hh"
87 spi_base = Param.UInt32(0x0, "Frame SPI base number");
88 spi_len = Param.UInt32(0x0, "Frame SPI total number");
89 addr = Param.Addr("Address for frame PIO")
90
91class Gicv2m(PioDevice):
92 type = 'Gicv2m'
93 cxx_header = "dev/arm/gic_v2m.hh"
94
95 pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
96 gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts")
97 frames = VectorParam.Gicv2mFrame([], "Power of two number of frames")
|
| 98
99class VGic(PioDevice):
100 type = 'VGic'
101 cxx_header = "dev/arm/vgic.hh"
102 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
103 platform = Param.Platform(Parent.any, "Platform this device is part of.")
104 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
105 hv_addr = Param.Addr(0, "Address for hv control")
106 pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
107 # The number of list registers is not currently configurable at runtime.
108 ppint = Param.UInt32("HV maintenance interrupt number")
109
110 def generateDeviceTree(self, state):
111 gic = self.gic.unproxy(self)
112
113 node = FdtNode("interrupt-controller")
114 node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic",
115 "arm,cortex-a9-gic"])
116 node.append(FdtPropertyWords("#interrupt-cells", [3]))
117 node.append(FdtPropertyWords("#address-cells", [0]))
118 node.append(FdtProperty("interrupt-controller"))
119
120 regs = (
121 state.addrCells(gic.dist_addr) +
122 state.sizeCells(0x1000) +
123 state.addrCells(gic.cpu_addr) +
124 state.sizeCells(0x1000) +
125 state.addrCells(self.hv_addr) +
126 state.sizeCells(0x2000) +
127 state.addrCells(self.vcpu_addr) +
128 state.sizeCells(0x2000) )
129
130 node.append(FdtPropertyWords("reg", regs))
131 node.append(FdtPropertyWords("interrupts",
132 [1, int(self.ppint)-16, 0xf04]))
133
134 node.appendPhandle(gic)
135
136 yield node
|