tsunamireg.h (3540:87e83423cb36) | tsunamireg.h (4059:e9cef915589f) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 122 unchanged lines hidden (view full) --- 131#define TSDEV_DMA2_CMND 0xD0 132#define TSDEV_DMA2_STAT TSDEV_DMA2_CMND 133#define TSDEV_DMA1_MMASK 0x0F 134#define TSDEV_DMA2_MMASK 0xDE 135 136/* Added for keyboard accesses */ 137#define TSDEV_KBD 0x64 138 | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 122 unchanged lines hidden (view full) --- 131#define TSDEV_DMA2_CMND 0xD0 132#define TSDEV_DMA2_STAT TSDEV_DMA2_CMND 133#define TSDEV_DMA1_MMASK 0x0F 134#define TSDEV_DMA2_MMASK 0xDE 135 136/* Added for keyboard accesses */ 137#define TSDEV_KBD 0x64 138 |
139/* Added for ATA PCI DMA */ 140#define ATA_PCI_DMA 0x00 141#define ATA_PCI_DMA2 0x02 142#define ATA_PCI_DMA3 0x16 143#define ATA_PCI_DMA4 0x17 144#define ATA_PCI_DMA5 0x1a 145#define ATA_PCI_DMA6 0x11 146#define ATA_PCI_DMA7 0x14 147 | |
148#define TSDEV_RTC_ADDR 0x70 149#define TSDEV_RTC_DATA 0x71 150 151#define PCHIP_PCI0_MEMORY ULL(0x00000000000) 152#define PCHIP_PCI0_IO ULL(0x001FC000000) 153#define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000) 154#define TSUNAMI_PCI0_MEMORY TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY 155#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO 156 157 | 139#define TSDEV_RTC_ADDR 0x70 140#define TSDEV_RTC_DATA 0x71 141 142#define PCHIP_PCI0_MEMORY ULL(0x00000000000) 143#define PCHIP_PCI0_IO ULL(0x001FC000000) 144#define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000) 145#define TSUNAMI_PCI0_MEMORY TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY 146#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO 147 148 |
158// UART Defines 159#define UART_IER_RDI 0x01 160#define UART_IER_THRI 0x02 161#define UART_IER_RLSI 0x04 162 163 164#define UART_LSR_TEMT 0x40 165#define UART_LSR_THRE 0x20 166#define UART_LSR_DR 0x01 167 168#define UART_MCR_LOOP 0x10 169 | |
170// System Control PortB Status Bits 171#define PORTB_SPKR_HIGH 0x20 172 173#endif // __TSUNAMIREG_H__ | 149// System Control PortB Status Bits 150#define PORTB_SPKR_HIGH 0x20 151 152#endif // __TSUNAMIREG_H__ |