1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 122 unchanged lines hidden (view full) --- 131#define TSDEV_DMA2_CMND 0xD0 132#define TSDEV_DMA2_STAT TSDEV_DMA2_CMND 133#define TSDEV_DMA1_MMASK 0x0F 134#define TSDEV_DMA2_MMASK 0xDE 135 136/* Added for keyboard accesses */ 137#define TSDEV_KBD 0x64 138 |
139#define TSDEV_RTC_ADDR 0x70 140#define TSDEV_RTC_DATA 0x71 141 142#define PCHIP_PCI0_MEMORY ULL(0x00000000000) 143#define PCHIP_PCI0_IO ULL(0x001FC000000) 144#define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000) 145#define TSUNAMI_PCI0_MEMORY TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY 146#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO 147 148 |
149// System Control PortB Status Bits 150#define PORTB_SPKR_HIGH 0x20 151 152#endif // __TSUNAMIREG_H__ |