1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Andrew Schultz
30 * Miguel Serrano
31 */
32
33/** @file
34 * Tsunami I/O including PIC, PIT, RTC, DMA
35 */
36
37#include <sys/time.h>
38
39#include <deque>
40#include <string>
41#include <vector>
42
43#include "base/time.hh"
44#include "base/trace.hh"
45#include "dev/rtcreg.h"
46#include "dev/alpha/tsunami_cchip.hh"
47#include "dev/alpha/tsunami.hh"
48#include "dev/alpha/tsunami_io.hh"
49#include "dev/alpha/tsunamireg.h"
50#include "mem/packet.hh"
51#include "mem/packet_access.hh"
52#include "mem/port.hh"
53#include "sim/system.hh"
54
55using namespace std;
56//Should this be AlphaISA?
57using namespace TheISA;
58
59TsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p)
60 : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency),
61 tsunami(p->tsunami)
62{
63}
64
65TsunamiIO::TsunamiIO(const Params *p)
66 : BasicPioDevice(p), tsunami(p->tsunami),
67 pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p)
68{
69 pioSize = 0x100;
70
71 // set the back pointer from tsunami to myself
72 tsunami->io = this;
73
74 timerData = 0;
75 picr = 0;
76 picInterrupting = false;
77}
78
79Tick
80TsunamiIO::frequency() const
81{
82 return Clock::Frequency / params()->frequency;
83}
84
85Tick
86TsunamiIO::read(PacketPtr pkt)
87{
88 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
89
90 Addr daddr = pkt->getAddr() - pioAddr;
91
92 DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(),
93 pkt->getSize(), daddr);
94
95 pkt->allocate();
96
97 if (pkt->getSize() == sizeof(uint8_t)) {
98 switch(daddr) {
99 // PIC1 mask read
100 case TSDEV_PIC1_MASK:
101 pkt->set(~mask1);
102 break;
103 case TSDEV_PIC2_MASK:
104 pkt->set(~mask2);
105 break;
106 case TSDEV_PIC1_ISR:
107 // !!! If this is modified 64bit case needs to be too
108 // Pal code has to do a 64 bit physical read because there is
109 // no load physical byte instruction
110 pkt->set(picr);
111 break;
112 case TSDEV_PIC2_ISR:
113 // PIC2 not implemnted... just return 0
114 pkt->set(0x00);
115 break;
116 case TSDEV_TMR0_DATA:
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Andrew Schultz
30 * Miguel Serrano
31 */
32
33/** @file
34 * Tsunami I/O including PIC, PIT, RTC, DMA
35 */
36
37#include <sys/time.h>
38
39#include <deque>
40#include <string>
41#include <vector>
42
43#include "base/time.hh"
44#include "base/trace.hh"
45#include "dev/rtcreg.h"
46#include "dev/alpha/tsunami_cchip.hh"
47#include "dev/alpha/tsunami.hh"
48#include "dev/alpha/tsunami_io.hh"
49#include "dev/alpha/tsunamireg.h"
50#include "mem/packet.hh"
51#include "mem/packet_access.hh"
52#include "mem/port.hh"
53#include "sim/system.hh"
54
55using namespace std;
56//Should this be AlphaISA?
57using namespace TheISA;
58
59TsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p)
60 : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency),
61 tsunami(p->tsunami)
62{
63}
64
65TsunamiIO::TsunamiIO(const Params *p)
66 : BasicPioDevice(p), tsunami(p->tsunami),
67 pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p)
68{
69 pioSize = 0x100;
70
71 // set the back pointer from tsunami to myself
72 tsunami->io = this;
73
74 timerData = 0;
75 picr = 0;
76 picInterrupting = false;
77}
78
79Tick
80TsunamiIO::frequency() const
81{
82 return Clock::Frequency / params()->frequency;
83}
84
85Tick
86TsunamiIO::read(PacketPtr pkt)
87{
88 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
89
90 Addr daddr = pkt->getAddr() - pioAddr;
91
92 DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(),
93 pkt->getSize(), daddr);
94
95 pkt->allocate();
96
97 if (pkt->getSize() == sizeof(uint8_t)) {
98 switch(daddr) {
99 // PIC1 mask read
100 case TSDEV_PIC1_MASK:
101 pkt->set(~mask1);
102 break;
103 case TSDEV_PIC2_MASK:
104 pkt->set(~mask2);
105 break;
106 case TSDEV_PIC1_ISR:
107 // !!! If this is modified 64bit case needs to be too
108 // Pal code has to do a 64 bit physical read because there is
109 // no load physical byte instruction
110 pkt->set(picr);
111 break;
112 case TSDEV_PIC2_ISR:
113 // PIC2 not implemnted... just return 0
114 pkt->set(0x00);
115 break;
116 case TSDEV_TMR0_DATA:
|
117 pkt->set(pitimer.counter0.read());
| 117 pkt->set(pitimer.readCounter(0));
|
118 break;
119 case TSDEV_TMR1_DATA:
| 118 break;
119 case TSDEV_TMR1_DATA:
|
120 pkt->set(pitimer.counter1.read());
| 120 pkt->set(pitimer.readCounter(1));
|
121 break;
122 case TSDEV_TMR2_DATA:
| 121 break;
122 case TSDEV_TMR2_DATA:
|
123 pkt->set(pitimer.counter2.read());
| 123 pkt->set(pitimer.readCounter(2));
|
124 break;
125 case TSDEV_RTC_DATA:
126 pkt->set(rtc.readData(rtcAddr));
127 break;
128 case TSDEV_CTRL_PORTB:
| 124 break;
125 case TSDEV_RTC_DATA:
126 pkt->set(rtc.readData(rtcAddr));
127 break;
128 case TSDEV_CTRL_PORTB:
|
129 if (pitimer.counter2.outputHigh())
| 129 if (pitimer.outputHigh(2))
|
130 pkt->set(PORTB_SPKR_HIGH);
131 else
132 pkt->set(0x00);
133 break;
134 default:
135 panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize());
136 }
137 } else if (pkt->getSize() == sizeof(uint64_t)) {
138 if (daddr == TSDEV_PIC1_ISR)
139 pkt->set<uint64_t>(picr);
140 else
141 panic("I/O Read - invalid addr - va %#x size %d\n",
142 pkt->getAddr(), pkt->getSize());
143 } else {
144 panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize());
145 }
146 pkt->makeAtomicResponse();
147 return pioDelay;
148}
149
150Tick
151TsunamiIO::write(PacketPtr pkt)
152{
153 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
154 Addr daddr = pkt->getAddr() - pioAddr;
155
156 DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
157 pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get<uint8_t>());
158
159 assert(pkt->getSize() == sizeof(uint8_t));
160
161 switch(daddr) {
162 case TSDEV_PIC1_MASK:
163 mask1 = ~(pkt->get<uint8_t>());
164 if ((picr & mask1) && !picInterrupting) {
165 picInterrupting = true;
166 tsunami->cchip->postDRIR(55);
167 DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
168 }
169 if ((!(picr & mask1)) && picInterrupting) {
170 picInterrupting = false;
171 tsunami->cchip->clearDRIR(55);
172 DPRINTF(Tsunami, "clearing pic interrupt\n");
173 }
174 break;
175 case TSDEV_PIC2_MASK:
176 mask2 = pkt->get<uint8_t>();
177 //PIC2 Not implemented to interrupt
178 break;
179 case TSDEV_PIC1_ACK:
180 // clear the interrupt on the PIC
181 picr &= ~(1 << (pkt->get<uint8_t>() & 0xF));
182 if (!(picr & mask1))
183 tsunami->cchip->clearDRIR(55);
184 break;
185 case TSDEV_DMA1_MODE:
186 mode1 = pkt->get<uint8_t>();
187 break;
188 case TSDEV_DMA2_MODE:
189 mode2 = pkt->get<uint8_t>();
190 break;
191 case TSDEV_TMR0_DATA:
| 130 pkt->set(PORTB_SPKR_HIGH);
131 else
132 pkt->set(0x00);
133 break;
134 default:
135 panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize());
136 }
137 } else if (pkt->getSize() == sizeof(uint64_t)) {
138 if (daddr == TSDEV_PIC1_ISR)
139 pkt->set<uint64_t>(picr);
140 else
141 panic("I/O Read - invalid addr - va %#x size %d\n",
142 pkt->getAddr(), pkt->getSize());
143 } else {
144 panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize());
145 }
146 pkt->makeAtomicResponse();
147 return pioDelay;
148}
149
150Tick
151TsunamiIO::write(PacketPtr pkt)
152{
153 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
154 Addr daddr = pkt->getAddr() - pioAddr;
155
156 DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
157 pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get<uint8_t>());
158
159 assert(pkt->getSize() == sizeof(uint8_t));
160
161 switch(daddr) {
162 case TSDEV_PIC1_MASK:
163 mask1 = ~(pkt->get<uint8_t>());
164 if ((picr & mask1) && !picInterrupting) {
165 picInterrupting = true;
166 tsunami->cchip->postDRIR(55);
167 DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
168 }
169 if ((!(picr & mask1)) && picInterrupting) {
170 picInterrupting = false;
171 tsunami->cchip->clearDRIR(55);
172 DPRINTF(Tsunami, "clearing pic interrupt\n");
173 }
174 break;
175 case TSDEV_PIC2_MASK:
176 mask2 = pkt->get<uint8_t>();
177 //PIC2 Not implemented to interrupt
178 break;
179 case TSDEV_PIC1_ACK:
180 // clear the interrupt on the PIC
181 picr &= ~(1 << (pkt->get<uint8_t>() & 0xF));
182 if (!(picr & mask1))
183 tsunami->cchip->clearDRIR(55);
184 break;
185 case TSDEV_DMA1_MODE:
186 mode1 = pkt->get<uint8_t>();
187 break;
188 case TSDEV_DMA2_MODE:
189 mode2 = pkt->get<uint8_t>();
190 break;
191 case TSDEV_TMR0_DATA:
|
192 pitimer.counter0.write(pkt->get<uint8_t>());
| 192 pitimer.writeCounter(0, pkt->get<uint8_t>());
|
193 break;
194 case TSDEV_TMR1_DATA:
| 193 break;
194 case TSDEV_TMR1_DATA:
|
195 pitimer.counter1.write(pkt->get<uint8_t>());
| 195 pitimer.writeCounter(1, pkt->get<uint8_t>());
|
196 break;
197 case TSDEV_TMR2_DATA:
| 196 break;
197 case TSDEV_TMR2_DATA:
|
198 pitimer.counter2.write(pkt->get<uint8_t>());
| 198 pitimer.writeCounter(2, pkt->get<uint8_t>());
|
199 break;
200 case TSDEV_TMR_CTRL:
201 pitimer.writeControl(pkt->get<uint8_t>());
202 break;
203 case TSDEV_RTC_ADDR:
204 rtcAddr = pkt->get<uint8_t>();
205 break;
206 case TSDEV_RTC_DATA:
207 rtc.writeData(rtcAddr, pkt->get<uint8_t>());
208 break;
209 case TSDEV_KBD:
210 case TSDEV_DMA1_CMND:
211 case TSDEV_DMA2_CMND:
212 case TSDEV_DMA1_MMASK:
213 case TSDEV_DMA2_MMASK:
214 case TSDEV_PIC2_ACK:
215 case TSDEV_DMA1_RESET:
216 case TSDEV_DMA2_RESET:
217 case TSDEV_DMA1_MASK:
218 case TSDEV_DMA2_MASK:
219 case TSDEV_CTRL_PORTB:
220 break;
221 default:
222 panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>());
223 }
224
225 pkt->makeAtomicResponse();
226 return pioDelay;
227}
228
229void
230TsunamiIO::postPIC(uint8_t bitvector)
231{
232 //PIC2 Is not implemented, because nothing of interest there
233 picr |= bitvector;
234 if (picr & mask1) {
235 tsunami->cchip->postDRIR(55);
236 DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
237 }
238}
239
240void
241TsunamiIO::clearPIC(uint8_t bitvector)
242{
243 //PIC2 Is not implemented, because nothing of interest there
244 picr &= ~bitvector;
245 if (!(picr & mask1)) {
246 tsunami->cchip->clearDRIR(55);
247 DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
248 }
249}
250
251void
252TsunamiIO::serialize(ostream &os)
253{
254 SERIALIZE_SCALAR(rtcAddr);
255 SERIALIZE_SCALAR(timerData);
256 SERIALIZE_SCALAR(mask1);
257 SERIALIZE_SCALAR(mask2);
258 SERIALIZE_SCALAR(mode1);
259 SERIALIZE_SCALAR(mode2);
260 SERIALIZE_SCALAR(picr);
261 SERIALIZE_SCALAR(picInterrupting);
262
263 // Serialize the timers
264 pitimer.serialize("pitimer", os);
265 rtc.serialize("rtc", os);
266}
267
268void
269TsunamiIO::unserialize(Checkpoint *cp, const string §ion)
270{
271 UNSERIALIZE_SCALAR(rtcAddr);
272 UNSERIALIZE_SCALAR(timerData);
273 UNSERIALIZE_SCALAR(mask1);
274 UNSERIALIZE_SCALAR(mask2);
275 UNSERIALIZE_SCALAR(mode1);
276 UNSERIALIZE_SCALAR(mode2);
277 UNSERIALIZE_SCALAR(picr);
278 UNSERIALIZE_SCALAR(picInterrupting);
279
280 // Unserialize the timers
281 pitimer.unserialize("pitimer", cp, section);
282 rtc.unserialize("rtc", cp, section);
283}
284
285TsunamiIO *
286TsunamiIOParams::create()
287{
288 return new TsunamiIO(this);
289}
| 199 break;
200 case TSDEV_TMR_CTRL:
201 pitimer.writeControl(pkt->get<uint8_t>());
202 break;
203 case TSDEV_RTC_ADDR:
204 rtcAddr = pkt->get<uint8_t>();
205 break;
206 case TSDEV_RTC_DATA:
207 rtc.writeData(rtcAddr, pkt->get<uint8_t>());
208 break;
209 case TSDEV_KBD:
210 case TSDEV_DMA1_CMND:
211 case TSDEV_DMA2_CMND:
212 case TSDEV_DMA1_MMASK:
213 case TSDEV_DMA2_MMASK:
214 case TSDEV_PIC2_ACK:
215 case TSDEV_DMA1_RESET:
216 case TSDEV_DMA2_RESET:
217 case TSDEV_DMA1_MASK:
218 case TSDEV_DMA2_MASK:
219 case TSDEV_CTRL_PORTB:
220 break;
221 default:
222 panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>());
223 }
224
225 pkt->makeAtomicResponse();
226 return pioDelay;
227}
228
229void
230TsunamiIO::postPIC(uint8_t bitvector)
231{
232 //PIC2 Is not implemented, because nothing of interest there
233 picr |= bitvector;
234 if (picr & mask1) {
235 tsunami->cchip->postDRIR(55);
236 DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
237 }
238}
239
240void
241TsunamiIO::clearPIC(uint8_t bitvector)
242{
243 //PIC2 Is not implemented, because nothing of interest there
244 picr &= ~bitvector;
245 if (!(picr & mask1)) {
246 tsunami->cchip->clearDRIR(55);
247 DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
248 }
249}
250
251void
252TsunamiIO::serialize(ostream &os)
253{
254 SERIALIZE_SCALAR(rtcAddr);
255 SERIALIZE_SCALAR(timerData);
256 SERIALIZE_SCALAR(mask1);
257 SERIALIZE_SCALAR(mask2);
258 SERIALIZE_SCALAR(mode1);
259 SERIALIZE_SCALAR(mode2);
260 SERIALIZE_SCALAR(picr);
261 SERIALIZE_SCALAR(picInterrupting);
262
263 // Serialize the timers
264 pitimer.serialize("pitimer", os);
265 rtc.serialize("rtc", os);
266}
267
268void
269TsunamiIO::unserialize(Checkpoint *cp, const string §ion)
270{
271 UNSERIALIZE_SCALAR(rtcAddr);
272 UNSERIALIZE_SCALAR(timerData);
273 UNSERIALIZE_SCALAR(mask1);
274 UNSERIALIZE_SCALAR(mask2);
275 UNSERIALIZE_SCALAR(mode1);
276 UNSERIALIZE_SCALAR(mode2);
277 UNSERIALIZE_SCALAR(picr);
278 UNSERIALIZE_SCALAR(picInterrupting);
279
280 // Unserialize the timers
281 pitimer.unserialize("pitimer", cp, section);
282 rtc.unserialize("rtc", cp, section);
283}
284
285TsunamiIO *
286TsunamiIOParams::create()
287{
288 return new TsunamiIO(this);
289}
|