1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Andrew Schultz
30 * Miguel Serrano
31 */
32
33/** @file
34 * Tsunami I/O including PIC, PIT, RTC, DMA
35 */
36
37#include "dev/alpha/tsunami_io.hh"
38
39#include <sys/time.h>
40
41#include <deque>
42#include <string>
43#include <vector>
44
45#include "base/time.hh"
46#include "base/trace.hh"
47#include "config/the_isa.hh"
48#include "debug/Tsunami.hh"
49#include "dev/alpha/tsunami.hh"
50#include "dev/alpha/tsunami_cchip.hh"
51#include "dev/alpha/tsunamireg.h"
52#include "dev/rtcreg.h"
53#include "mem/packet.hh"
54#include "mem/packet_access.hh"
55#include "mem/port.hh"
56#include "sim/system.hh"
57
58// clang complains about std::set being overloaded with Packet::set if
59// we open up the entire namespace std
60using std::string;
61using std::ostream;
62
63//Should this be AlphaISA?
64using namespace TheISA;
65
66TsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p)
67 : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency),
68 tsunami(p->tsunami)
69{
70}
71
72TsunamiIO::TsunamiIO(const Params *p)
73 : BasicPioDevice(p, 0x100), tsunami(p->tsunami),
74 pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p)
75{
76 // set the back pointer from tsunami to myself
77 tsunami->io = this;
78
79 timerData = 0;
80 picr = 0;
81 picInterrupting = false;
82}
83
84Tick
85TsunamiIO::frequency() const
86{
87 return SimClock::Frequency / params()->frequency;
88}
89
90Tick
91TsunamiIO::read(PacketPtr pkt)
92{
93 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
94
95 Addr daddr = pkt->getAddr() - pioAddr;
96
97 DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(),
98 pkt->getSize(), daddr);
99
100 if (pkt->getSize() == sizeof(uint8_t)) {
101 switch(daddr) {
102 // PIC1 mask read
103 case TSDEV_PIC1_MASK:
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Andrew Schultz
30 * Miguel Serrano
31 */
32
33/** @file
34 * Tsunami I/O including PIC, PIT, RTC, DMA
35 */
36
37#include "dev/alpha/tsunami_io.hh"
38
39#include <sys/time.h>
40
41#include <deque>
42#include <string>
43#include <vector>
44
45#include "base/time.hh"
46#include "base/trace.hh"
47#include "config/the_isa.hh"
48#include "debug/Tsunami.hh"
49#include "dev/alpha/tsunami.hh"
50#include "dev/alpha/tsunami_cchip.hh"
51#include "dev/alpha/tsunamireg.h"
52#include "dev/rtcreg.h"
53#include "mem/packet.hh"
54#include "mem/packet_access.hh"
55#include "mem/port.hh"
56#include "sim/system.hh"
57
58// clang complains about std::set being overloaded with Packet::set if
59// we open up the entire namespace std
60using std::string;
61using std::ostream;
62
63//Should this be AlphaISA?
64using namespace TheISA;
65
66TsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p)
67 : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency),
68 tsunami(p->tsunami)
69{
70}
71
72TsunamiIO::TsunamiIO(const Params *p)
73 : BasicPioDevice(p, 0x100), tsunami(p->tsunami),
74 pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p)
75{
76 // set the back pointer from tsunami to myself
77 tsunami->io = this;
78
79 timerData = 0;
80 picr = 0;
81 picInterrupting = false;
82}
83
84Tick
85TsunamiIO::frequency() const
86{
87 return SimClock::Frequency / params()->frequency;
88}
89
90Tick
91TsunamiIO::read(PacketPtr pkt)
92{
93 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
94
95 Addr daddr = pkt->getAddr() - pioAddr;
96
97 DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(),
98 pkt->getSize(), daddr);
99
100 if (pkt->getSize() == sizeof(uint8_t)) {
101 switch(daddr) {
102 // PIC1 mask read
103 case TSDEV_PIC1_MASK:
|
104 pkt->set(~mask1);
| 104 pkt->setLE(~mask1);
|
105 break;
106 case TSDEV_PIC2_MASK:
| 105 break;
106 case TSDEV_PIC2_MASK:
|
107 pkt->set(~mask2);
| 107 pkt->setLE(~mask2);
|
108 break;
109 case TSDEV_PIC1_ISR:
110 // !!! If this is modified 64bit case needs to be too
111 // Pal code has to do a 64 bit physical read because there is
112 // no load physical byte instruction
| 108 break;
109 case TSDEV_PIC1_ISR:
110 // !!! If this is modified 64bit case needs to be too
111 // Pal code has to do a 64 bit physical read because there is
112 // no load physical byte instruction
|
113 pkt->set(picr);
| 113 pkt->setLE(picr);
|
114 break;
115 case TSDEV_PIC2_ISR:
116 // PIC2 not implemnted... just return 0
| 114 break;
115 case TSDEV_PIC2_ISR:
116 // PIC2 not implemnted... just return 0
|
117 pkt->set(0x00);
| 117 pkt->setLE(0x00);
|
118 break;
119 case TSDEV_TMR0_DATA:
| 118 break;
119 case TSDEV_TMR0_DATA:
|
120 pkt->set(pitimer.readCounter(0));
| 120 pkt->setLE(pitimer.readCounter(0));
|
121 break;
122 case TSDEV_TMR1_DATA:
| 121 break;
122 case TSDEV_TMR1_DATA:
|
123 pkt->set(pitimer.readCounter(1));
| 123 pkt->setLE(pitimer.readCounter(1));
|
124 break;
125 case TSDEV_TMR2_DATA:
| 124 break;
125 case TSDEV_TMR2_DATA:
|
126 pkt->set(pitimer.readCounter(2));
| 126 pkt->setLE(pitimer.readCounter(2));
|
127 break;
128 case TSDEV_RTC_DATA:
| 127 break;
128 case TSDEV_RTC_DATA:
|
129 pkt->set(rtc.readData(rtcAddr));
| 129 pkt->setLE(rtc.readData(rtcAddr));
|
130 break;
131 case TSDEV_CTRL_PORTB:
132 if (pitimer.outputHigh(2))
| 130 break;
131 case TSDEV_CTRL_PORTB:
132 if (pitimer.outputHigh(2))
|
133 pkt->set(PORTB_SPKR_HIGH);
| 133 pkt->setLE(PORTB_SPKR_HIGH);
|
134 else
| 134 else
|
135 pkt->set(0x00);
| 135 pkt->setLE(0x00);
|
136 break;
137 default:
138 panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize());
139 }
140 } else if (pkt->getSize() == sizeof(uint64_t)) {
141 if (daddr == TSDEV_PIC1_ISR)
| 136 break;
137 default:
138 panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize());
139 }
140 } else if (pkt->getSize() == sizeof(uint64_t)) {
141 if (daddr == TSDEV_PIC1_ISR)
|
142 pkt->set(picr);
| 142 pkt->setLE<uint64_t>(picr);
|
143 else
144 panic("I/O Read - invalid addr - va %#x size %d\n",
145 pkt->getAddr(), pkt->getSize());
146 } else {
147 panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize());
148 }
149 pkt->makeAtomicResponse();
150 return pioDelay;
151}
152
153Tick
154TsunamiIO::write(PacketPtr pkt)
155{
156 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
157 Addr daddr = pkt->getAddr() - pioAddr;
158
159 DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
| 143 else
144 panic("I/O Read - invalid addr - va %#x size %d\n",
145 pkt->getAddr(), pkt->getSize());
146 } else {
147 panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize());
148 }
149 pkt->makeAtomicResponse();
150 return pioDelay;
151}
152
153Tick
154TsunamiIO::write(PacketPtr pkt)
155{
156 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
157 Addr daddr = pkt->getAddr() - pioAddr;
158
159 DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
|
160 pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get<uint8_t>());
| 160 pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff,
161 (uint32_t)pkt->getLE<uint8_t>());
|
161
162 assert(pkt->getSize() == sizeof(uint8_t));
163
164 switch(daddr) {
165 case TSDEV_PIC1_MASK:
| 162
163 assert(pkt->getSize() == sizeof(uint8_t));
164
165 switch(daddr) {
166 case TSDEV_PIC1_MASK:
|
166 mask1 = ~(pkt->get());
| 167 mask1 = ~(pkt->getLE<uint8_t>());
|
167 if ((picr & mask1) && !picInterrupting) {
168 picInterrupting = true;
169 tsunami->cchip->postDRIR(55);
170 DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
171 }
172 if ((!(picr & mask1)) && picInterrupting) {
173 picInterrupting = false;
174 tsunami->cchip->clearDRIR(55);
175 DPRINTF(Tsunami, "clearing pic interrupt\n");
176 }
177 break;
178 case TSDEV_PIC2_MASK:
| 168 if ((picr & mask1) && !picInterrupting) {
169 picInterrupting = true;
170 tsunami->cchip->postDRIR(55);
171 DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
172 }
173 if ((!(picr & mask1)) && picInterrupting) {
174 picInterrupting = false;
175 tsunami->cchip->clearDRIR(55);
176 DPRINTF(Tsunami, "clearing pic interrupt\n");
177 }
178 break;
179 case TSDEV_PIC2_MASK:
|
179 mask2 = pkt->get();
| 180 mask2 = pkt->getLE<uint8_t>();
|
180 //PIC2 Not implemented to interrupt
181 break;
182 case TSDEV_PIC1_ACK:
183 // clear the interrupt on the PIC
| 181 //PIC2 Not implemented to interrupt
182 break;
183 case TSDEV_PIC1_ACK:
184 // clear the interrupt on the PIC
|
184 picr &= ~(1 << (pkt->get() & 0xF));
| 185 picr &= ~(1 << (pkt->getLE<uint8_t>() & 0xF));
|
185 if (!(picr & mask1))
186 tsunami->cchip->clearDRIR(55);
187 break;
188 case TSDEV_DMA1_MODE:
| 186 if (!(picr & mask1))
187 tsunami->cchip->clearDRIR(55);
188 break;
189 case TSDEV_DMA1_MODE:
|
189 mode1 = pkt->get();
| 190 mode1 = pkt->getLE<uint8_t>();
|
190 break;
191 case TSDEV_DMA2_MODE:
| 191 break;
192 case TSDEV_DMA2_MODE:
|
192 mode2 = pkt->get();
| 193 mode2 = pkt->getLE<uint8_t>();
|
193 break;
194 case TSDEV_TMR0_DATA:
| 194 break;
195 case TSDEV_TMR0_DATA:
|
195 pitimer.writeCounter(0, pkt->get());
| 196 pitimer.writeCounter(0, pkt->getLE<uint8_t>());
|
196 break;
197 case TSDEV_TMR1_DATA:
| 197 break;
198 case TSDEV_TMR1_DATA:
|
198 pitimer.writeCounter(1, pkt->get());
| 199 pitimer.writeCounter(1, pkt->getLE<uint8_t>());
|
199 break;
200 case TSDEV_TMR2_DATA:
| 200 break;
201 case TSDEV_TMR2_DATA:
|
201 pitimer.writeCounter(2, pkt->get());
| 202 pitimer.writeCounter(2, pkt->getLE<uint8_t>());
|
202 break;
203 case TSDEV_TMR_CTRL:
| 203 break;
204 case TSDEV_TMR_CTRL:
|
204 pitimer.writeControl(pkt->get());
| 205 pitimer.writeControl(pkt->getLE<uint8_t>());
|
205 break;
206 case TSDEV_RTC_ADDR:
| 206 break;
207 case TSDEV_RTC_ADDR:
|
207 rtcAddr = pkt->get();
| 208 rtcAddr = pkt->getLE<uint8_t>();
|
208 break;
209 case TSDEV_RTC_DATA:
| 209 break;
210 case TSDEV_RTC_DATA:
|
210 rtc.writeData(rtcAddr, pkt->get());
| 211 rtc.writeData(rtcAddr, pkt->getLE<uint8_t>());
|
211 break;
212 case TSDEV_KBD:
213 case TSDEV_DMA1_CMND:
214 case TSDEV_DMA2_CMND:
215 case TSDEV_DMA1_MMASK:
216 case TSDEV_DMA2_MMASK:
217 case TSDEV_PIC2_ACK:
218 case TSDEV_DMA1_RESET:
219 case TSDEV_DMA2_RESET:
220 case TSDEV_DMA1_MASK:
221 case TSDEV_DMA2_MASK:
222 case TSDEV_CTRL_PORTB:
223 break;
224 default:
| 212 break;
213 case TSDEV_KBD:
214 case TSDEV_DMA1_CMND:
215 case TSDEV_DMA2_CMND:
216 case TSDEV_DMA1_MMASK:
217 case TSDEV_DMA2_MMASK:
218 case TSDEV_PIC2_ACK:
219 case TSDEV_DMA1_RESET:
220 case TSDEV_DMA2_RESET:
221 case TSDEV_DMA1_MASK:
222 case TSDEV_DMA2_MASK:
223 case TSDEV_CTRL_PORTB:
224 break;
225 default:
|
225 panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>());
| 226 panic("I/O Write - va%#x size %d data %#x\n",
227 pkt->getAddr(), pkt->getSize(), pkt->getLE<uint8_t>());
|
226 }
227
228 pkt->makeAtomicResponse();
229 return pioDelay;
230}
231
232void
233TsunamiIO::postPIC(uint8_t bitvector)
234{
235 //PIC2 Is not implemented, because nothing of interest there
236 picr |= bitvector;
237 if (picr & mask1) {
238 tsunami->cchip->postDRIR(55);
239 DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
240 }
241}
242
243void
244TsunamiIO::clearPIC(uint8_t bitvector)
245{
246 //PIC2 Is not implemented, because nothing of interest there
247 picr &= ~bitvector;
248 if (!(picr & mask1)) {
249 tsunami->cchip->clearDRIR(55);
250 DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
251 }
252}
253
254void
255TsunamiIO::serialize(CheckpointOut &cp) const
256{
257 SERIALIZE_SCALAR(rtcAddr);
258 SERIALIZE_SCALAR(timerData);
259 SERIALIZE_SCALAR(mask1);
260 SERIALIZE_SCALAR(mask2);
261 SERIALIZE_SCALAR(mode1);
262 SERIALIZE_SCALAR(mode2);
263 SERIALIZE_SCALAR(picr);
264 SERIALIZE_SCALAR(picInterrupting);
265
266 // Serialize the timers
267 pitimer.serialize("pitimer", cp);
268 rtc.serialize("rtc", cp);
269}
270
271void
272TsunamiIO::unserialize(CheckpointIn &cp)
273{
274 UNSERIALIZE_SCALAR(rtcAddr);
275 UNSERIALIZE_SCALAR(timerData);
276 UNSERIALIZE_SCALAR(mask1);
277 UNSERIALIZE_SCALAR(mask2);
278 UNSERIALIZE_SCALAR(mode1);
279 UNSERIALIZE_SCALAR(mode2);
280 UNSERIALIZE_SCALAR(picr);
281 UNSERIALIZE_SCALAR(picInterrupting);
282
283 // Unserialize the timers
284 pitimer.unserialize("pitimer", cp);
285 rtc.unserialize("rtc", cp);
286}
287
288void
289TsunamiIO::startup()
290{
291 rtc.startup();
292 pitimer.startup();
293}
294
295TsunamiIO *
296TsunamiIOParams::create()
297{
298 return new TsunamiIO(this);
299}
| 228 }
229
230 pkt->makeAtomicResponse();
231 return pioDelay;
232}
233
234void
235TsunamiIO::postPIC(uint8_t bitvector)
236{
237 //PIC2 Is not implemented, because nothing of interest there
238 picr |= bitvector;
239 if (picr & mask1) {
240 tsunami->cchip->postDRIR(55);
241 DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
242 }
243}
244
245void
246TsunamiIO::clearPIC(uint8_t bitvector)
247{
248 //PIC2 Is not implemented, because nothing of interest there
249 picr &= ~bitvector;
250 if (!(picr & mask1)) {
251 tsunami->cchip->clearDRIR(55);
252 DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
253 }
254}
255
256void
257TsunamiIO::serialize(CheckpointOut &cp) const
258{
259 SERIALIZE_SCALAR(rtcAddr);
260 SERIALIZE_SCALAR(timerData);
261 SERIALIZE_SCALAR(mask1);
262 SERIALIZE_SCALAR(mask2);
263 SERIALIZE_SCALAR(mode1);
264 SERIALIZE_SCALAR(mode2);
265 SERIALIZE_SCALAR(picr);
266 SERIALIZE_SCALAR(picInterrupting);
267
268 // Serialize the timers
269 pitimer.serialize("pitimer", cp);
270 rtc.serialize("rtc", cp);
271}
272
273void
274TsunamiIO::unserialize(CheckpointIn &cp)
275{
276 UNSERIALIZE_SCALAR(rtcAddr);
277 UNSERIALIZE_SCALAR(timerData);
278 UNSERIALIZE_SCALAR(mask1);
279 UNSERIALIZE_SCALAR(mask2);
280 UNSERIALIZE_SCALAR(mode1);
281 UNSERIALIZE_SCALAR(mode2);
282 UNSERIALIZE_SCALAR(picr);
283 UNSERIALIZE_SCALAR(picInterrupting);
284
285 // Unserialize the timers
286 pitimer.unserialize("pitimer", cp);
287 rtc.unserialize("rtc", cp);
288}
289
290void
291TsunamiIO::startup()
292{
293 rtc.startup();
294 pitimer.startup();
295}
296
297TsunamiIO *
298TsunamiIOParams::create()
299{
300 return new TsunamiIO(this);
301}
|