1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 21 unchanged lines hidden (view full) --- 30 31/** @file 32 * Emulation of the Tsunami CChip CSRs 33 */ 34 35#ifndef __TSUNAMI_CCHIP_HH__ 36#define __TSUNAMI_CCHIP_HH__ 37 |
38#include "base/range.hh" |
39#include "dev/alpha/tsunami.hh" |
40#include "dev/io_device.hh" |
41#include "params/TsunamiCChip.hh" |
42 |
43/** 44 * Tsunami CChip CSR Emulation. This device includes all the interrupt 45 * handling code for the chipset. 46 */ 47class TsunamiCChip : public BasicPioDevice 48{ 49 protected: 50 /** --- 23 unchanged lines hidden (view full) --- 74 75 /** Indicator of which CPUs have an IPI interrupt */ 76 uint64_t ipint; 77 78 /** Indicator of which CPUs have an RTC interrupt */ 79 uint64_t itint; 80 81 public: |
82 typedef TsunamiCChipParams Params; |
83 /** 84 * Initialize the Tsunami CChip by setting all of the 85 * device register to 0. 86 * @param p params struct 87 */ |
88 TsunamiCChip(const Params *p); |
89 |
90 const Params * 91 params() const 92 { 93 return dynamic_cast<const Params *>(_params); 94 } 95 |
96 virtual Tick read(PacketPtr pkt); 97 98 virtual Tick write(PacketPtr pkt); 99 100 /** 101 * post an RTC interrupt to the CPU 102 */ 103 void postRTC(); --- 48 unchanged lines hidden --- |