1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Ron Dreslinski
30 */
31
32/** @file
33 * Emulation of the Tsunami CChip CSRs
34 */
35
36#include <deque>
37#include <string>
38#include <vector>
39
40#include "arch/alpha/ev5.hh"
41#include "base/trace.hh"
42#include "config/the_isa.hh"
43#include "cpu/intr_control.hh"
44#include "cpu/thread_context.hh"
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Ron Dreslinski
30 */
31
32/** @file
33 * Emulation of the Tsunami CChip CSRs
34 */
35
36#include <deque>
37#include <string>
38#include <vector>
39
40#include "arch/alpha/ev5.hh"
41#include "base/trace.hh"
42#include "config/the_isa.hh"
43#include "cpu/intr_control.hh"
44#include "cpu/thread_context.hh"
|
45#include "dev/alpha/tsunami.hh"
46#include "dev/alpha/tsunami_cchip.hh"
47#include "dev/alpha/tsunamireg.h"
48#include "mem/packet.hh"
49#include "mem/packet_access.hh"
50#include "mem/port.hh"
51#include "params/TsunamiCChip.hh"
52#include "sim/system.hh"
53
54using namespace std;
55//Should this be AlphaISA?
56using namespace TheISA;
57
58TsunamiCChip::TsunamiCChip(const Params *p)
59 : BasicPioDevice(p), tsunami(p->tsunami)
60{
61 pioSize = 0x10000000;
62
63 drir = 0;
64 ipint = 0;
65 itint = 0;
66
67 for (int x = 0; x < Tsunami::Max_CPUs; x++)
68 {
69 dim[x] = 0;
70 dir[x] = 0;
71 }
72
73 //Put back pointer in tsunami
74 tsunami->cchip = this;
75}
76
77Tick
78TsunamiCChip::read(PacketPtr pkt)
79{
80 DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
81
82 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
83
84 Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
85 Addr daddr = (pkt->getAddr() - pioAddr);
86
87 pkt->allocate();
88 switch (pkt->getSize()) {
89
90 case sizeof(uint64_t):
91 pkt->set<uint64_t>(0);
92
93 if (daddr & TSDEV_CC_BDIMS)
94 {
95 pkt->set(dim[(daddr >> 4) & 0x3F]);
96 break;
97 }
98
99 if (daddr & TSDEV_CC_BDIRS)
100 {
101 pkt->set(dir[(daddr >> 4) & 0x3F]);
102 break;
103 }
104
105 switch(regnum) {
106 case TSDEV_CC_CSR:
107 pkt->set(0x0);
108 break;
109 case TSDEV_CC_MTR:
110 panic("TSDEV_CC_MTR not implemeted\n");
111 break;
112 case TSDEV_CC_MISC:
113 pkt->set(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) |
114 (pkt->req->contextId() & 0x3));
115 // currently, FS cannot handle MT so contextId and
116 // cpuId are effectively the same, don't know if it will
117 // matter if FS becomes MT enabled. I suspect no because
118 // we are currently able to boot up to 64 procs anyway
119 // which would render the CPUID of this register useless
120 // anyway
121 break;
122 case TSDEV_CC_AAR0:
123 case TSDEV_CC_AAR1:
124 case TSDEV_CC_AAR2:
125 case TSDEV_CC_AAR3:
126 pkt->set(0);
127 break;
128 case TSDEV_CC_DIM0:
129 pkt->set(dim[0]);
130 break;
131 case TSDEV_CC_DIM1:
132 pkt->set(dim[1]);
133 break;
134 case TSDEV_CC_DIM2:
135 pkt->set(dim[2]);
136 break;
137 case TSDEV_CC_DIM3:
138 pkt->set(dim[3]);
139 break;
140 case TSDEV_CC_DIR0:
141 pkt->set(dir[0]);
142 break;
143 case TSDEV_CC_DIR1:
144 pkt->set(dir[1]);
145 break;
146 case TSDEV_CC_DIR2:
147 pkt->set(dir[2]);
148 break;
149 case TSDEV_CC_DIR3:
150 pkt->set(dir[3]);
151 break;
152 case TSDEV_CC_DRIR:
153 pkt->set(drir);
154 break;
155 case TSDEV_CC_PRBEN:
156 panic("TSDEV_CC_PRBEN not implemented\n");
157 break;
158 case TSDEV_CC_IIC0:
159 case TSDEV_CC_IIC1:
160 case TSDEV_CC_IIC2:
161 case TSDEV_CC_IIC3:
162 panic("TSDEV_CC_IICx not implemented\n");
163 break;
164 case TSDEV_CC_MPR0:
165 case TSDEV_CC_MPR1:
166 case TSDEV_CC_MPR2:
167 case TSDEV_CC_MPR3:
168 panic("TSDEV_CC_MPRx not implemented\n");
169 break;
170 case TSDEV_CC_IPIR:
171 pkt->set(ipint);
172 break;
173 case TSDEV_CC_ITIR:
174 pkt->set(itint);
175 break;
176 default:
177 panic("default in cchip read reached, accessing 0x%x\n");
178 } // uint64_t
179
180 break;
181 case sizeof(uint32_t):
182 case sizeof(uint16_t):
183 case sizeof(uint8_t):
184 default:
185 panic("invalid access size(?) for tsunami register!\n");
186 }
187 DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
188 regnum, pkt->getSize(), pkt->get<uint64_t>());
189
190 pkt->makeAtomicResponse();
191 return pioDelay;
192}
193
194Tick
195TsunamiCChip::write(PacketPtr pkt)
196{
197 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
198 Addr daddr = pkt->getAddr() - pioAddr;
199 Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
200
201
202 assert(pkt->getSize() == sizeof(uint64_t));
203
204 DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
205
206 bool supportedWrite = false;
207
208
209 if (daddr & TSDEV_CC_BDIMS)
210 {
211 int number = (daddr >> 4) & 0x3F;
212
213 uint64_t bitvector;
214 uint64_t olddim;
215 uint64_t olddir;
216
217 olddim = dim[number];
218 olddir = dir[number];
219 dim[number] = pkt->get<uint64_t>();
220 dir[number] = dim[number] & drir;
221 for(int x = 0; x < Tsunami::Max_CPUs; x++)
222 {
223 bitvector = ULL(1) << x;
224 // Figure out which bits have changed
225 if ((dim[number] & bitvector) != (olddim & bitvector))
226 {
227 // The bit is now set and it wasn't before (set)
228 if((dim[number] & bitvector) && (dir[number] & bitvector))
229 {
230 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
231 DPRINTF(Tsunami, "dim write resulting in posting dir"
232 " interrupt to cpu %d\n", number);
233 }
234 else if ((olddir & bitvector) &&
235 !(dir[number] & bitvector))
236 {
237 // The bit was set and now its now clear and
238 // we were interrupting on that bit before
239 tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
240 DPRINTF(Tsunami, "dim write resulting in clear"
241 " dir interrupt to cpu %d\n", number);
242
243 }
244
245
246 }
247 }
248 } else {
249 switch(regnum) {
250 case TSDEV_CC_CSR:
251 panic("TSDEV_CC_CSR write\n");
252 case TSDEV_CC_MTR:
253 panic("TSDEV_CC_MTR write not implemented\n");
254 case TSDEV_CC_MISC:
255 uint64_t ipreq;
256 ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
257 //If it is bit 12-15, this is an IPI post
258 if (ipreq) {
259 reqIPI(ipreq);
260 supportedWrite = true;
261 }
262
263 //If it is bit 8-11, this is an IPI clear
264 uint64_t ipintr;
265 ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
266 if (ipintr) {
267 clearIPI(ipintr);
268 supportedWrite = true;
269 }
270
271 //If it is the 4-7th bit, clear the RTC interrupt
272 uint64_t itintr;
273 itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
274 if (itintr) {
275 clearITI(itintr);
276 supportedWrite = true;
277 }
278
279 // ignore NXMs
280 if (pkt->get<uint64_t>() & 0x10000000)
281 supportedWrite = true;
282
283 if(!supportedWrite)
284 panic("TSDEV_CC_MISC write not implemented\n");
285
286 break;
287 case TSDEV_CC_AAR0:
288 case TSDEV_CC_AAR1:
289 case TSDEV_CC_AAR2:
290 case TSDEV_CC_AAR3:
291 panic("TSDEV_CC_AARx write not implemeted\n");
292 case TSDEV_CC_DIM0:
293 case TSDEV_CC_DIM1:
294 case TSDEV_CC_DIM2:
295 case TSDEV_CC_DIM3:
296 int number;
297 if(regnum == TSDEV_CC_DIM0)
298 number = 0;
299 else if(regnum == TSDEV_CC_DIM1)
300 number = 1;
301 else if(regnum == TSDEV_CC_DIM2)
302 number = 2;
303 else
304 number = 3;
305
306 uint64_t bitvector;
307 uint64_t olddim;
308 uint64_t olddir;
309
310 olddim = dim[number];
311 olddir = dir[number];
312 dim[number] = pkt->get<uint64_t>();
313 dir[number] = dim[number] & drir;
314 for(int x = 0; x < 64; x++)
315 {
316 bitvector = ULL(1) << x;
317 // Figure out which bits have changed
318 if ((dim[number] & bitvector) != (olddim & bitvector))
319 {
320 // The bit is now set and it wasn't before (set)
321 if((dim[number] & bitvector) && (dir[number] & bitvector))
322 {
323 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
324 DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
325 }
326 else if ((olddir & bitvector) &&
327 !(dir[number] & bitvector))
328 {
329 // The bit was set and now its now clear and
330 // we were interrupting on that bit before
331 tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
332 DPRINTF(Tsunami, "dim write resulting in clear"
333 " dir interrupt to cpu %d\n",
334 x);
335
336 }
337
338
339 }
340 }
341 break;
342 case TSDEV_CC_DIR0:
343 case TSDEV_CC_DIR1:
344 case TSDEV_CC_DIR2:
345 case TSDEV_CC_DIR3:
346 panic("TSDEV_CC_DIR write not implemented\n");
347 case TSDEV_CC_DRIR:
348 panic("TSDEV_CC_DRIR write not implemented\n");
349 case TSDEV_CC_PRBEN:
350 panic("TSDEV_CC_PRBEN write not implemented\n");
351 case TSDEV_CC_IIC0:
352 case TSDEV_CC_IIC1:
353 case TSDEV_CC_IIC2:
354 case TSDEV_CC_IIC3:
355 panic("TSDEV_CC_IICx write not implemented\n");
356 case TSDEV_CC_MPR0:
357 case TSDEV_CC_MPR1:
358 case TSDEV_CC_MPR2:
359 case TSDEV_CC_MPR3:
360 panic("TSDEV_CC_MPRx write not implemented\n");
361 case TSDEV_CC_IPIR:
362 clearIPI(pkt->get<uint64_t>());
363 break;
364 case TSDEV_CC_ITIR:
365 clearITI(pkt->get<uint64_t>());
366 break;
367 case TSDEV_CC_IPIQ:
368 reqIPI(pkt->get<uint64_t>());
369 break;
370 default:
371 panic("default in cchip read reached, accessing 0x%x\n");
372 } // swtich(regnum)
373 } // not BIG_TSUNAMI write
374 pkt->makeAtomicResponse();
375 return pioDelay;
376}
377
378void
379TsunamiCChip::clearIPI(uint64_t ipintr)
380{
381 int numcpus = sys->threadContexts.size();
382 assert(numcpus <= Tsunami::Max_CPUs);
383
384 if (ipintr) {
385 for (int cpunum=0; cpunum < numcpus; cpunum++) {
386 // Check each cpu bit
387 uint64_t cpumask = ULL(1) << cpunum;
388 if (ipintr & cpumask) {
389 // Check if there is a pending ipi
390 if (ipint & cpumask) {
391 ipint &= ~cpumask;
392 tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
393 DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
394 }
395 else
396 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
397 }
398 }
399 }
400 else
401 panic("Big IPI Clear, but not processors indicated\n");
402}
403
404void
405TsunamiCChip::clearITI(uint64_t itintr)
406{
407 int numcpus = sys->threadContexts.size();
408 assert(numcpus <= Tsunami::Max_CPUs);
409
410 if (itintr) {
411 for (int i=0; i < numcpus; i++) {
412 uint64_t cpumask = ULL(1) << i;
413 if (itintr & cpumask & itint) {
414 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
415 itint &= ~cpumask;
416 DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
417 }
418 }
419 }
420 else
421 panic("Big ITI Clear, but not processors indicated\n");
422}
423
424void
425TsunamiCChip::reqIPI(uint64_t ipreq)
426{
427 int numcpus = sys->threadContexts.size();
428 assert(numcpus <= Tsunami::Max_CPUs);
429
430 if (ipreq) {
431 for (int cpunum=0; cpunum < numcpus; cpunum++) {
432 // Check each cpu bit
433 uint64_t cpumask = ULL(1) << cpunum;
434 if (ipreq & cpumask) {
435 // Check if there is already an ipi (bits 8:11)
436 if (!(ipint & cpumask)) {
437 ipint |= cpumask;
438 tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
439 DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
440 }
441 else
442 warn("post IPI for CPU=%d, but IPI already\n", cpunum);
443 }
444 }
445 }
446 else
447 panic("Big IPI Request, but not processors indicated\n");
448}
449
450
451void
452TsunamiCChip::postRTC()
453{
454 int size = sys->threadContexts.size();
455 assert(size <= Tsunami::Max_CPUs);
456
457 for (int i = 0; i < size; i++) {
458 uint64_t cpumask = ULL(1) << i;
459 if (!(cpumask & itint)) {
460 itint |= cpumask;
461 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
462 DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d\n", i);
463 }
464 }
465
466}
467
468void
469TsunamiCChip::postDRIR(uint32_t interrupt)
470{
471 uint64_t bitvector = ULL(1) << interrupt;
472 uint64_t size = sys->threadContexts.size();
473 assert(size <= Tsunami::Max_CPUs);
474 drir |= bitvector;
475
476 for(int i=0; i < size; i++) {
477 dir[i] = dim[i] & drir;
478 if (dim[i] & bitvector) {
479 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
480 DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
481 "interrupt %d\n",i, interrupt);
482 }
483 }
484}
485
486void
487TsunamiCChip::clearDRIR(uint32_t interrupt)
488{
489 uint64_t bitvector = ULL(1) << interrupt;
490 uint64_t size = sys->threadContexts.size();
491 assert(size <= Tsunami::Max_CPUs);
492
493 if (drir & bitvector)
494 {
495 drir &= ~bitvector;
496 for(int i=0; i < size; i++) {
497 if (dir[i] & bitvector) {
498 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
499 DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
500 "interrupt %d\n",i, interrupt);
501
502 }
503 dir[i] = dim[i] & drir;
504 }
505 }
506 else
507 DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
508}
509
510
511void
512TsunamiCChip::serialize(std::ostream &os)
513{
514 SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
515 SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
516 SERIALIZE_SCALAR(ipint);
517 SERIALIZE_SCALAR(itint);
518 SERIALIZE_SCALAR(drir);
519}
520
521void
522TsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion)
523{
524 UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
525 UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
526 UNSERIALIZE_SCALAR(ipint);
527 UNSERIALIZE_SCALAR(itint);
528 UNSERIALIZE_SCALAR(drir);
529}
530
531TsunamiCChip *
532TsunamiCChipParams::create()
533{
534 return new TsunamiCChip(this);
535}
| 47#include "dev/alpha/tsunami.hh"
48#include "dev/alpha/tsunami_cchip.hh"
49#include "dev/alpha/tsunamireg.h"
50#include "mem/packet.hh"
51#include "mem/packet_access.hh"
52#include "mem/port.hh"
53#include "params/TsunamiCChip.hh"
54#include "sim/system.hh"
55
56using namespace std;
57//Should this be AlphaISA?
58using namespace TheISA;
59
60TsunamiCChip::TsunamiCChip(const Params *p)
61 : BasicPioDevice(p), tsunami(p->tsunami)
62{
63 pioSize = 0x10000000;
64
65 drir = 0;
66 ipint = 0;
67 itint = 0;
68
69 for (int x = 0; x < Tsunami::Max_CPUs; x++)
70 {
71 dim[x] = 0;
72 dir[x] = 0;
73 }
74
75 //Put back pointer in tsunami
76 tsunami->cchip = this;
77}
78
79Tick
80TsunamiCChip::read(PacketPtr pkt)
81{
82 DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
83
84 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
85
86 Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
87 Addr daddr = (pkt->getAddr() - pioAddr);
88
89 pkt->allocate();
90 switch (pkt->getSize()) {
91
92 case sizeof(uint64_t):
93 pkt->set<uint64_t>(0);
94
95 if (daddr & TSDEV_CC_BDIMS)
96 {
97 pkt->set(dim[(daddr >> 4) & 0x3F]);
98 break;
99 }
100
101 if (daddr & TSDEV_CC_BDIRS)
102 {
103 pkt->set(dir[(daddr >> 4) & 0x3F]);
104 break;
105 }
106
107 switch(regnum) {
108 case TSDEV_CC_CSR:
109 pkt->set(0x0);
110 break;
111 case TSDEV_CC_MTR:
112 panic("TSDEV_CC_MTR not implemeted\n");
113 break;
114 case TSDEV_CC_MISC:
115 pkt->set(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) |
116 (pkt->req->contextId() & 0x3));
117 // currently, FS cannot handle MT so contextId and
118 // cpuId are effectively the same, don't know if it will
119 // matter if FS becomes MT enabled. I suspect no because
120 // we are currently able to boot up to 64 procs anyway
121 // which would render the CPUID of this register useless
122 // anyway
123 break;
124 case TSDEV_CC_AAR0:
125 case TSDEV_CC_AAR1:
126 case TSDEV_CC_AAR2:
127 case TSDEV_CC_AAR3:
128 pkt->set(0);
129 break;
130 case TSDEV_CC_DIM0:
131 pkt->set(dim[0]);
132 break;
133 case TSDEV_CC_DIM1:
134 pkt->set(dim[1]);
135 break;
136 case TSDEV_CC_DIM2:
137 pkt->set(dim[2]);
138 break;
139 case TSDEV_CC_DIM3:
140 pkt->set(dim[3]);
141 break;
142 case TSDEV_CC_DIR0:
143 pkt->set(dir[0]);
144 break;
145 case TSDEV_CC_DIR1:
146 pkt->set(dir[1]);
147 break;
148 case TSDEV_CC_DIR2:
149 pkt->set(dir[2]);
150 break;
151 case TSDEV_CC_DIR3:
152 pkt->set(dir[3]);
153 break;
154 case TSDEV_CC_DRIR:
155 pkt->set(drir);
156 break;
157 case TSDEV_CC_PRBEN:
158 panic("TSDEV_CC_PRBEN not implemented\n");
159 break;
160 case TSDEV_CC_IIC0:
161 case TSDEV_CC_IIC1:
162 case TSDEV_CC_IIC2:
163 case TSDEV_CC_IIC3:
164 panic("TSDEV_CC_IICx not implemented\n");
165 break;
166 case TSDEV_CC_MPR0:
167 case TSDEV_CC_MPR1:
168 case TSDEV_CC_MPR2:
169 case TSDEV_CC_MPR3:
170 panic("TSDEV_CC_MPRx not implemented\n");
171 break;
172 case TSDEV_CC_IPIR:
173 pkt->set(ipint);
174 break;
175 case TSDEV_CC_ITIR:
176 pkt->set(itint);
177 break;
178 default:
179 panic("default in cchip read reached, accessing 0x%x\n");
180 } // uint64_t
181
182 break;
183 case sizeof(uint32_t):
184 case sizeof(uint16_t):
185 case sizeof(uint8_t):
186 default:
187 panic("invalid access size(?) for tsunami register!\n");
188 }
189 DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
190 regnum, pkt->getSize(), pkt->get<uint64_t>());
191
192 pkt->makeAtomicResponse();
193 return pioDelay;
194}
195
196Tick
197TsunamiCChip::write(PacketPtr pkt)
198{
199 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
200 Addr daddr = pkt->getAddr() - pioAddr;
201 Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
202
203
204 assert(pkt->getSize() == sizeof(uint64_t));
205
206 DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
207
208 bool supportedWrite = false;
209
210
211 if (daddr & TSDEV_CC_BDIMS)
212 {
213 int number = (daddr >> 4) & 0x3F;
214
215 uint64_t bitvector;
216 uint64_t olddim;
217 uint64_t olddir;
218
219 olddim = dim[number];
220 olddir = dir[number];
221 dim[number] = pkt->get<uint64_t>();
222 dir[number] = dim[number] & drir;
223 for(int x = 0; x < Tsunami::Max_CPUs; x++)
224 {
225 bitvector = ULL(1) << x;
226 // Figure out which bits have changed
227 if ((dim[number] & bitvector) != (olddim & bitvector))
228 {
229 // The bit is now set and it wasn't before (set)
230 if((dim[number] & bitvector) && (dir[number] & bitvector))
231 {
232 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
233 DPRINTF(Tsunami, "dim write resulting in posting dir"
234 " interrupt to cpu %d\n", number);
235 }
236 else if ((olddir & bitvector) &&
237 !(dir[number] & bitvector))
238 {
239 // The bit was set and now its now clear and
240 // we were interrupting on that bit before
241 tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
242 DPRINTF(Tsunami, "dim write resulting in clear"
243 " dir interrupt to cpu %d\n", number);
244
245 }
246
247
248 }
249 }
250 } else {
251 switch(regnum) {
252 case TSDEV_CC_CSR:
253 panic("TSDEV_CC_CSR write\n");
254 case TSDEV_CC_MTR:
255 panic("TSDEV_CC_MTR write not implemented\n");
256 case TSDEV_CC_MISC:
257 uint64_t ipreq;
258 ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
259 //If it is bit 12-15, this is an IPI post
260 if (ipreq) {
261 reqIPI(ipreq);
262 supportedWrite = true;
263 }
264
265 //If it is bit 8-11, this is an IPI clear
266 uint64_t ipintr;
267 ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
268 if (ipintr) {
269 clearIPI(ipintr);
270 supportedWrite = true;
271 }
272
273 //If it is the 4-7th bit, clear the RTC interrupt
274 uint64_t itintr;
275 itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
276 if (itintr) {
277 clearITI(itintr);
278 supportedWrite = true;
279 }
280
281 // ignore NXMs
282 if (pkt->get<uint64_t>() & 0x10000000)
283 supportedWrite = true;
284
285 if(!supportedWrite)
286 panic("TSDEV_CC_MISC write not implemented\n");
287
288 break;
289 case TSDEV_CC_AAR0:
290 case TSDEV_CC_AAR1:
291 case TSDEV_CC_AAR2:
292 case TSDEV_CC_AAR3:
293 panic("TSDEV_CC_AARx write not implemeted\n");
294 case TSDEV_CC_DIM0:
295 case TSDEV_CC_DIM1:
296 case TSDEV_CC_DIM2:
297 case TSDEV_CC_DIM3:
298 int number;
299 if(regnum == TSDEV_CC_DIM0)
300 number = 0;
301 else if(regnum == TSDEV_CC_DIM1)
302 number = 1;
303 else if(regnum == TSDEV_CC_DIM2)
304 number = 2;
305 else
306 number = 3;
307
308 uint64_t bitvector;
309 uint64_t olddim;
310 uint64_t olddir;
311
312 olddim = dim[number];
313 olddir = dir[number];
314 dim[number] = pkt->get<uint64_t>();
315 dir[number] = dim[number] & drir;
316 for(int x = 0; x < 64; x++)
317 {
318 bitvector = ULL(1) << x;
319 // Figure out which bits have changed
320 if ((dim[number] & bitvector) != (olddim & bitvector))
321 {
322 // The bit is now set and it wasn't before (set)
323 if((dim[number] & bitvector) && (dir[number] & bitvector))
324 {
325 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
326 DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
327 }
328 else if ((olddir & bitvector) &&
329 !(dir[number] & bitvector))
330 {
331 // The bit was set and now its now clear and
332 // we were interrupting on that bit before
333 tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
334 DPRINTF(Tsunami, "dim write resulting in clear"
335 " dir interrupt to cpu %d\n",
336 x);
337
338 }
339
340
341 }
342 }
343 break;
344 case TSDEV_CC_DIR0:
345 case TSDEV_CC_DIR1:
346 case TSDEV_CC_DIR2:
347 case TSDEV_CC_DIR3:
348 panic("TSDEV_CC_DIR write not implemented\n");
349 case TSDEV_CC_DRIR:
350 panic("TSDEV_CC_DRIR write not implemented\n");
351 case TSDEV_CC_PRBEN:
352 panic("TSDEV_CC_PRBEN write not implemented\n");
353 case TSDEV_CC_IIC0:
354 case TSDEV_CC_IIC1:
355 case TSDEV_CC_IIC2:
356 case TSDEV_CC_IIC3:
357 panic("TSDEV_CC_IICx write not implemented\n");
358 case TSDEV_CC_MPR0:
359 case TSDEV_CC_MPR1:
360 case TSDEV_CC_MPR2:
361 case TSDEV_CC_MPR3:
362 panic("TSDEV_CC_MPRx write not implemented\n");
363 case TSDEV_CC_IPIR:
364 clearIPI(pkt->get<uint64_t>());
365 break;
366 case TSDEV_CC_ITIR:
367 clearITI(pkt->get<uint64_t>());
368 break;
369 case TSDEV_CC_IPIQ:
370 reqIPI(pkt->get<uint64_t>());
371 break;
372 default:
373 panic("default in cchip read reached, accessing 0x%x\n");
374 } // swtich(regnum)
375 } // not BIG_TSUNAMI write
376 pkt->makeAtomicResponse();
377 return pioDelay;
378}
379
380void
381TsunamiCChip::clearIPI(uint64_t ipintr)
382{
383 int numcpus = sys->threadContexts.size();
384 assert(numcpus <= Tsunami::Max_CPUs);
385
386 if (ipintr) {
387 for (int cpunum=0; cpunum < numcpus; cpunum++) {
388 // Check each cpu bit
389 uint64_t cpumask = ULL(1) << cpunum;
390 if (ipintr & cpumask) {
391 // Check if there is a pending ipi
392 if (ipint & cpumask) {
393 ipint &= ~cpumask;
394 tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
395 DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
396 }
397 else
398 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
399 }
400 }
401 }
402 else
403 panic("Big IPI Clear, but not processors indicated\n");
404}
405
406void
407TsunamiCChip::clearITI(uint64_t itintr)
408{
409 int numcpus = sys->threadContexts.size();
410 assert(numcpus <= Tsunami::Max_CPUs);
411
412 if (itintr) {
413 for (int i=0; i < numcpus; i++) {
414 uint64_t cpumask = ULL(1) << i;
415 if (itintr & cpumask & itint) {
416 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
417 itint &= ~cpumask;
418 DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
419 }
420 }
421 }
422 else
423 panic("Big ITI Clear, but not processors indicated\n");
424}
425
426void
427TsunamiCChip::reqIPI(uint64_t ipreq)
428{
429 int numcpus = sys->threadContexts.size();
430 assert(numcpus <= Tsunami::Max_CPUs);
431
432 if (ipreq) {
433 for (int cpunum=0; cpunum < numcpus; cpunum++) {
434 // Check each cpu bit
435 uint64_t cpumask = ULL(1) << cpunum;
436 if (ipreq & cpumask) {
437 // Check if there is already an ipi (bits 8:11)
438 if (!(ipint & cpumask)) {
439 ipint |= cpumask;
440 tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
441 DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
442 }
443 else
444 warn("post IPI for CPU=%d, but IPI already\n", cpunum);
445 }
446 }
447 }
448 else
449 panic("Big IPI Request, but not processors indicated\n");
450}
451
452
453void
454TsunamiCChip::postRTC()
455{
456 int size = sys->threadContexts.size();
457 assert(size <= Tsunami::Max_CPUs);
458
459 for (int i = 0; i < size; i++) {
460 uint64_t cpumask = ULL(1) << i;
461 if (!(cpumask & itint)) {
462 itint |= cpumask;
463 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
464 DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d\n", i);
465 }
466 }
467
468}
469
470void
471TsunamiCChip::postDRIR(uint32_t interrupt)
472{
473 uint64_t bitvector = ULL(1) << interrupt;
474 uint64_t size = sys->threadContexts.size();
475 assert(size <= Tsunami::Max_CPUs);
476 drir |= bitvector;
477
478 for(int i=0; i < size; i++) {
479 dir[i] = dim[i] & drir;
480 if (dim[i] & bitvector) {
481 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
482 DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
483 "interrupt %d\n",i, interrupt);
484 }
485 }
486}
487
488void
489TsunamiCChip::clearDRIR(uint32_t interrupt)
490{
491 uint64_t bitvector = ULL(1) << interrupt;
492 uint64_t size = sys->threadContexts.size();
493 assert(size <= Tsunami::Max_CPUs);
494
495 if (drir & bitvector)
496 {
497 drir &= ~bitvector;
498 for(int i=0; i < size; i++) {
499 if (dir[i] & bitvector) {
500 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
501 DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
502 "interrupt %d\n",i, interrupt);
503
504 }
505 dir[i] = dim[i] & drir;
506 }
507 }
508 else
509 DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
510}
511
512
513void
514TsunamiCChip::serialize(std::ostream &os)
515{
516 SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
517 SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
518 SERIALIZE_SCALAR(ipint);
519 SERIALIZE_SCALAR(itint);
520 SERIALIZE_SCALAR(drir);
521}
522
523void
524TsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion)
525{
526 UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
527 UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
528 UNSERIALIZE_SCALAR(ipint);
529 UNSERIALIZE_SCALAR(itint);
530 UNSERIALIZE_SCALAR(drir);
531}
532
533TsunamiCChip *
534TsunamiCChipParams::create()
535{
536 return new TsunamiCChip(this);
537}
|