1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Ron Dreslinski
30 */
31
32/** @file
33 * Emulation of the Tsunami CChip CSRs
34 */
35
36#include <deque>
37#include <string>
38#include <vector>
39
40#include "arch/alpha/ev5.hh"
41#include "base/trace.hh"
42#include "config/the_isa.hh"
43#include "cpu/intr_control.hh"
44#include "cpu/thread_context.hh"
45#include "debug/IPI.hh"
46#include "debug/Tsunami.hh"
47#include "dev/alpha/tsunami.hh"
48#include "dev/alpha/tsunami_cchip.hh"
49#include "dev/alpha/tsunamireg.h"
50#include "mem/packet.hh"
51#include "mem/packet_access.hh"
52#include "mem/port.hh"
53#include "params/TsunamiCChip.hh"
54#include "sim/system.hh"
55
56//Should this be AlphaISA?
57using namespace TheISA;
58
59TsunamiCChip::TsunamiCChip(const Params *p)
60 : BasicPioDevice(p, 0x10000000), tsunami(p->tsunami)
61{
62 drir = 0;
63 ipint = 0;
64 itint = 0;
65
66 for (int x = 0; x < Tsunami::Max_CPUs; x++)
67 {
68 dim[x] = 0;
69 dir[x] = 0;
70 }
71
72 //Put back pointer in tsunami
73 tsunami->cchip = this;
74}
75
76Tick
77TsunamiCChip::read(PacketPtr pkt)
78{
79 DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
80
81 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
82
83 Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
84 Addr daddr = (pkt->getAddr() - pioAddr);
85
86 switch (pkt->getSize()) {
87
88 case sizeof(uint64_t):
89 pkt->set<uint64_t>(0);
90
91 if (daddr & TSDEV_CC_BDIMS)
92 {
93 pkt->set(dim[(daddr >> 4) & 0x3F]);
94 break;
95 }
96
97 if (daddr & TSDEV_CC_BDIRS)
98 {
99 pkt->set(dir[(daddr >> 4) & 0x3F]);
100 break;
101 }
102
103 switch(regnum) {
104 case TSDEV_CC_CSR:
105 pkt->set(0x0);
106 break;
107 case TSDEV_CC_MTR:
108 panic("TSDEV_CC_MTR not implemeted\n");
109 break;
110 case TSDEV_CC_MISC:
111 pkt->set(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) |
112 (pkt->req->contextId() & 0x3));
113 // currently, FS cannot handle MT so contextId and
114 // cpuId are effectively the same, don't know if it will
115 // matter if FS becomes MT enabled. I suspect no because
116 // we are currently able to boot up to 64 procs anyway
117 // which would render the CPUID of this register useless
118 // anyway
119 break;
120 case TSDEV_CC_AAR0:
121 case TSDEV_CC_AAR1:
122 case TSDEV_CC_AAR2:
123 case TSDEV_CC_AAR3:
124 pkt->set(0);
125 break;
126 case TSDEV_CC_DIM0:
127 pkt->set(dim[0]);
128 break;
129 case TSDEV_CC_DIM1:
130 pkt->set(dim[1]);
131 break;
132 case TSDEV_CC_DIM2:
133 pkt->set(dim[2]);
134 break;
135 case TSDEV_CC_DIM3:
136 pkt->set(dim[3]);
137 break;
138 case TSDEV_CC_DIR0:
139 pkt->set(dir[0]);
140 break;
141 case TSDEV_CC_DIR1:
142 pkt->set(dir[1]);
143 break;
144 case TSDEV_CC_DIR2:
145 pkt->set(dir[2]);
146 break;
147 case TSDEV_CC_DIR3:
148 pkt->set(dir[3]);
149 break;
150 case TSDEV_CC_DRIR:
151 pkt->set(drir);
152 break;
153 case TSDEV_CC_PRBEN:
154 panic("TSDEV_CC_PRBEN not implemented\n");
155 break;
156 case TSDEV_CC_IIC0:
157 case TSDEV_CC_IIC1:
158 case TSDEV_CC_IIC2:
159 case TSDEV_CC_IIC3:
160 panic("TSDEV_CC_IICx not implemented\n");
161 break;
162 case TSDEV_CC_MPR0:
163 case TSDEV_CC_MPR1:
164 case TSDEV_CC_MPR2:
165 case TSDEV_CC_MPR3:
166 panic("TSDEV_CC_MPRx not implemented\n");
167 break;
168 case TSDEV_CC_IPIR:
169 pkt->set(ipint);
170 break;
171 case TSDEV_CC_ITIR:
172 pkt->set(itint);
173 break;
174 default:
175 panic("default in cchip read reached, accessing 0x%x\n");
176 } // uint64_t
177
178 break;
179 case sizeof(uint32_t):
180 case sizeof(uint16_t):
181 case sizeof(uint8_t):
182 default:
183 panic("invalid access size(?) for tsunami register!\n");
184 }
185 DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
186 regnum, pkt->getSize(), pkt->get<uint64_t>());
187
188 pkt->makeAtomicResponse();
189 return pioDelay;
190}
191
192Tick
193TsunamiCChip::write(PacketPtr pkt)
194{
195 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
196 Addr daddr = pkt->getAddr() - pioAddr;
197 Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
198
199
200 assert(pkt->getSize() == sizeof(uint64_t));
201
202 DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
203
204 bool supportedWrite = false;
205
206
207 if (daddr & TSDEV_CC_BDIMS)
208 {
209 int number = (daddr >> 4) & 0x3F;
210
211 uint64_t bitvector;
212 uint64_t olddim;
213 uint64_t olddir;
214
215 olddim = dim[number];
216 olddir = dir[number];
217 dim[number] = pkt->get<uint64_t>();
218 dir[number] = dim[number] & drir;
219 for(int x = 0; x < Tsunami::Max_CPUs; x++)
220 {
221 bitvector = ULL(1) << x;
222 // Figure out which bits have changed
223 if ((dim[number] & bitvector) != (olddim & bitvector))
224 {
225 // The bit is now set and it wasn't before (set)
226 if((dim[number] & bitvector) && (dir[number] & bitvector))
227 {
228 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
229 DPRINTF(Tsunami, "dim write resulting in posting dir"
230 " interrupt to cpu %d\n", number);
231 }
232 else if ((olddir & bitvector) &&
233 !(dir[number] & bitvector))
234 {
235 // The bit was set and now its now clear and
236 // we were interrupting on that bit before
237 tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
238 DPRINTF(Tsunami, "dim write resulting in clear"
239 " dir interrupt to cpu %d\n", number);
240
241 }
242
243
244 }
245 }
246 } else {
247 switch(regnum) {
248 case TSDEV_CC_CSR:
249 panic("TSDEV_CC_CSR write\n");
250 case TSDEV_CC_MTR:
251 panic("TSDEV_CC_MTR write not implemented\n");
252 case TSDEV_CC_MISC:
253 uint64_t ipreq;
254 ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
255 //If it is bit 12-15, this is an IPI post
256 if (ipreq) {
257 reqIPI(ipreq);
258 supportedWrite = true;
259 }
260
261 //If it is bit 8-11, this is an IPI clear
262 uint64_t ipintr;
263 ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
264 if (ipintr) {
265 clearIPI(ipintr);
266 supportedWrite = true;
267 }
268
269 //If it is the 4-7th bit, clear the RTC interrupt
270 uint64_t itintr;
271 itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
272 if (itintr) {
273 clearITI(itintr);
274 supportedWrite = true;
275 }
276
277 // ignore NXMs
278 if (pkt->get<uint64_t>() & 0x10000000)
279 supportedWrite = true;
280
281 if(!supportedWrite)
282 panic("TSDEV_CC_MISC write not implemented\n");
283
284 break;
285 case TSDEV_CC_AAR0:
286 case TSDEV_CC_AAR1:
287 case TSDEV_CC_AAR2:
288 case TSDEV_CC_AAR3:
289 panic("TSDEV_CC_AARx write not implemeted\n");
290 case TSDEV_CC_DIM0:
291 case TSDEV_CC_DIM1:
292 case TSDEV_CC_DIM2:
293 case TSDEV_CC_DIM3:
294 int number;
295 if(regnum == TSDEV_CC_DIM0)
296 number = 0;
297 else if(regnum == TSDEV_CC_DIM1)
298 number = 1;
299 else if(regnum == TSDEV_CC_DIM2)
300 number = 2;
301 else
302 number = 3;
303
304 uint64_t bitvector;
305 uint64_t olddim;
306 uint64_t olddir;
307
308 olddim = dim[number];
309 olddir = dir[number];
310 dim[number] = pkt->get<uint64_t>();
311 dir[number] = dim[number] & drir;
312 for(int x = 0; x < 64; x++)
313 {
314 bitvector = ULL(1) << x;
315 // Figure out which bits have changed
316 if ((dim[number] & bitvector) != (olddim & bitvector))
317 {
318 // The bit is now set and it wasn't before (set)
319 if((dim[number] & bitvector) && (dir[number] & bitvector))
320 {
321 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
322 DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
323 }
324 else if ((olddir & bitvector) &&
325 !(dir[number] & bitvector))
326 {
327 // The bit was set and now its now clear and
328 // we were interrupting on that bit before
329 tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
330 DPRINTF(Tsunami, "dim write resulting in clear"
331 " dir interrupt to cpu %d\n",
332 x);
333
334 }
335
336
337 }
338 }
339 break;
340 case TSDEV_CC_DIR0:
341 case TSDEV_CC_DIR1:
342 case TSDEV_CC_DIR2:
343 case TSDEV_CC_DIR3:
344 panic("TSDEV_CC_DIR write not implemented\n");
345 case TSDEV_CC_DRIR:
346 panic("TSDEV_CC_DRIR write not implemented\n");
347 case TSDEV_CC_PRBEN:
348 panic("TSDEV_CC_PRBEN write not implemented\n");
349 case TSDEV_CC_IIC0:
350 case TSDEV_CC_IIC1:
351 case TSDEV_CC_IIC2:
352 case TSDEV_CC_IIC3:
353 panic("TSDEV_CC_IICx write not implemented\n");
354 case TSDEV_CC_MPR0:
355 case TSDEV_CC_MPR1:
356 case TSDEV_CC_MPR2:
357 case TSDEV_CC_MPR3:
358 panic("TSDEV_CC_MPRx write not implemented\n");
359 case TSDEV_CC_IPIR:
360 clearIPI(pkt->get<uint64_t>());
361 break;
362 case TSDEV_CC_ITIR:
363 clearITI(pkt->get<uint64_t>());
364 break;
365 case TSDEV_CC_IPIQ:
366 reqIPI(pkt->get<uint64_t>());
367 break;
368 default:
369 panic("default in cchip read reached, accessing 0x%x\n");
370 } // swtich(regnum)
371 } // not BIG_TSUNAMI write
372 pkt->makeAtomicResponse();
373 return pioDelay;
374}
375
376void
377TsunamiCChip::clearIPI(uint64_t ipintr)
378{
379 int numcpus = sys->threadContexts.size();
380 assert(numcpus <= Tsunami::Max_CPUs);
381
382 if (ipintr) {
383 for (int cpunum=0; cpunum < numcpus; cpunum++) {
384 // Check each cpu bit
385 uint64_t cpumask = ULL(1) << cpunum;
386 if (ipintr & cpumask) {
387 // Check if there is a pending ipi
388 if (ipint & cpumask) {
389 ipint &= ~cpumask;
390 tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
391 DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
392 }
393 else
394 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
395 }
396 }
397 }
398 else
399 panic("Big IPI Clear, but not processors indicated\n");
400}
401
402void
403TsunamiCChip::clearITI(uint64_t itintr)
404{
405 int numcpus = sys->threadContexts.size();
406 assert(numcpus <= Tsunami::Max_CPUs);
407
408 if (itintr) {
409 for (int i=0; i < numcpus; i++) {
410 uint64_t cpumask = ULL(1) << i;
411 if (itintr & cpumask & itint) {
412 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
413 itint &= ~cpumask;
414 DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
415 }
416 }
417 }
418 else
419 panic("Big ITI Clear, but not processors indicated\n");
420}
421
422void
423TsunamiCChip::reqIPI(uint64_t ipreq)
424{
425 int numcpus = sys->threadContexts.size();
426 assert(numcpus <= Tsunami::Max_CPUs);
427
428 if (ipreq) {
429 for (int cpunum=0; cpunum < numcpus; cpunum++) {
430 // Check each cpu bit
431 uint64_t cpumask = ULL(1) << cpunum;
432 if (ipreq & cpumask) {
433 // Check if there is already an ipi (bits 8:11)
434 if (!(ipint & cpumask)) {
435 ipint |= cpumask;
436 tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
437 DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
438 }
439 else
440 warn("post IPI for CPU=%d, but IPI already\n", cpunum);
441 }
442 }
443 }
444 else
445 panic("Big IPI Request, but not processors indicated\n");
446}
447
448
449void
450TsunamiCChip::postRTC()
451{
452 int size = sys->threadContexts.size();
453 assert(size <= Tsunami::Max_CPUs);
454
455 for (int i = 0; i < size; i++) {
456 uint64_t cpumask = ULL(1) << i;
457 if (!(cpumask & itint)) {
458 itint |= cpumask;
459 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
460 DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d\n", i);
461 }
462 }
463
464}
465
466void
467TsunamiCChip::postDRIR(uint32_t interrupt)
468{
469 uint64_t bitvector = ULL(1) << interrupt;
470 uint64_t size = sys->threadContexts.size();
471 assert(size <= Tsunami::Max_CPUs);
472 drir |= bitvector;
473
474 for(int i=0; i < size; i++) {
475 dir[i] = dim[i] & drir;
476 if (dim[i] & bitvector) {
477 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
478 DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
479 "interrupt %d\n",i, interrupt);
480 }
481 }
482}
483
484void
485TsunamiCChip::clearDRIR(uint32_t interrupt)
486{
487 uint64_t bitvector = ULL(1) << interrupt;
488 uint64_t size = sys->threadContexts.size();
489 assert(size <= Tsunami::Max_CPUs);
490
491 if (drir & bitvector)
492 {
493 drir &= ~bitvector;
494 for(int i=0; i < size; i++) {
495 if (dir[i] & bitvector) {
496 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
497 DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
498 "interrupt %d\n",i, interrupt);
499
500 }
501 dir[i] = dim[i] & drir;
502 }
503 }
504 else
505 DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
506}
507
508
509void
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Ron Dreslinski
30 */
31
32/** @file
33 * Emulation of the Tsunami CChip CSRs
34 */
35
36#include <deque>
37#include <string>
38#include <vector>
39
40#include "arch/alpha/ev5.hh"
41#include "base/trace.hh"
42#include "config/the_isa.hh"
43#include "cpu/intr_control.hh"
44#include "cpu/thread_context.hh"
45#include "debug/IPI.hh"
46#include "debug/Tsunami.hh"
47#include "dev/alpha/tsunami.hh"
48#include "dev/alpha/tsunami_cchip.hh"
49#include "dev/alpha/tsunamireg.h"
50#include "mem/packet.hh"
51#include "mem/packet_access.hh"
52#include "mem/port.hh"
53#include "params/TsunamiCChip.hh"
54#include "sim/system.hh"
55
56//Should this be AlphaISA?
57using namespace TheISA;
58
59TsunamiCChip::TsunamiCChip(const Params *p)
60 : BasicPioDevice(p, 0x10000000), tsunami(p->tsunami)
61{
62 drir = 0;
63 ipint = 0;
64 itint = 0;
65
66 for (int x = 0; x < Tsunami::Max_CPUs; x++)
67 {
68 dim[x] = 0;
69 dir[x] = 0;
70 }
71
72 //Put back pointer in tsunami
73 tsunami->cchip = this;
74}
75
76Tick
77TsunamiCChip::read(PacketPtr pkt)
78{
79 DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
80
81 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
82
83 Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
84 Addr daddr = (pkt->getAddr() - pioAddr);
85
86 switch (pkt->getSize()) {
87
88 case sizeof(uint64_t):
89 pkt->set<uint64_t>(0);
90
91 if (daddr & TSDEV_CC_BDIMS)
92 {
93 pkt->set(dim[(daddr >> 4) & 0x3F]);
94 break;
95 }
96
97 if (daddr & TSDEV_CC_BDIRS)
98 {
99 pkt->set(dir[(daddr >> 4) & 0x3F]);
100 break;
101 }
102
103 switch(regnum) {
104 case TSDEV_CC_CSR:
105 pkt->set(0x0);
106 break;
107 case TSDEV_CC_MTR:
108 panic("TSDEV_CC_MTR not implemeted\n");
109 break;
110 case TSDEV_CC_MISC:
111 pkt->set(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) |
112 (pkt->req->contextId() & 0x3));
113 // currently, FS cannot handle MT so contextId and
114 // cpuId are effectively the same, don't know if it will
115 // matter if FS becomes MT enabled. I suspect no because
116 // we are currently able to boot up to 64 procs anyway
117 // which would render the CPUID of this register useless
118 // anyway
119 break;
120 case TSDEV_CC_AAR0:
121 case TSDEV_CC_AAR1:
122 case TSDEV_CC_AAR2:
123 case TSDEV_CC_AAR3:
124 pkt->set(0);
125 break;
126 case TSDEV_CC_DIM0:
127 pkt->set(dim[0]);
128 break;
129 case TSDEV_CC_DIM1:
130 pkt->set(dim[1]);
131 break;
132 case TSDEV_CC_DIM2:
133 pkt->set(dim[2]);
134 break;
135 case TSDEV_CC_DIM3:
136 pkt->set(dim[3]);
137 break;
138 case TSDEV_CC_DIR0:
139 pkt->set(dir[0]);
140 break;
141 case TSDEV_CC_DIR1:
142 pkt->set(dir[1]);
143 break;
144 case TSDEV_CC_DIR2:
145 pkt->set(dir[2]);
146 break;
147 case TSDEV_CC_DIR3:
148 pkt->set(dir[3]);
149 break;
150 case TSDEV_CC_DRIR:
151 pkt->set(drir);
152 break;
153 case TSDEV_CC_PRBEN:
154 panic("TSDEV_CC_PRBEN not implemented\n");
155 break;
156 case TSDEV_CC_IIC0:
157 case TSDEV_CC_IIC1:
158 case TSDEV_CC_IIC2:
159 case TSDEV_CC_IIC3:
160 panic("TSDEV_CC_IICx not implemented\n");
161 break;
162 case TSDEV_CC_MPR0:
163 case TSDEV_CC_MPR1:
164 case TSDEV_CC_MPR2:
165 case TSDEV_CC_MPR3:
166 panic("TSDEV_CC_MPRx not implemented\n");
167 break;
168 case TSDEV_CC_IPIR:
169 pkt->set(ipint);
170 break;
171 case TSDEV_CC_ITIR:
172 pkt->set(itint);
173 break;
174 default:
175 panic("default in cchip read reached, accessing 0x%x\n");
176 } // uint64_t
177
178 break;
179 case sizeof(uint32_t):
180 case sizeof(uint16_t):
181 case sizeof(uint8_t):
182 default:
183 panic("invalid access size(?) for tsunami register!\n");
184 }
185 DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
186 regnum, pkt->getSize(), pkt->get<uint64_t>());
187
188 pkt->makeAtomicResponse();
189 return pioDelay;
190}
191
192Tick
193TsunamiCChip::write(PacketPtr pkt)
194{
195 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
196 Addr daddr = pkt->getAddr() - pioAddr;
197 Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
198
199
200 assert(pkt->getSize() == sizeof(uint64_t));
201
202 DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
203
204 bool supportedWrite = false;
205
206
207 if (daddr & TSDEV_CC_BDIMS)
208 {
209 int number = (daddr >> 4) & 0x3F;
210
211 uint64_t bitvector;
212 uint64_t olddim;
213 uint64_t olddir;
214
215 olddim = dim[number];
216 olddir = dir[number];
217 dim[number] = pkt->get<uint64_t>();
218 dir[number] = dim[number] & drir;
219 for(int x = 0; x < Tsunami::Max_CPUs; x++)
220 {
221 bitvector = ULL(1) << x;
222 // Figure out which bits have changed
223 if ((dim[number] & bitvector) != (olddim & bitvector))
224 {
225 // The bit is now set and it wasn't before (set)
226 if((dim[number] & bitvector) && (dir[number] & bitvector))
227 {
228 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
229 DPRINTF(Tsunami, "dim write resulting in posting dir"
230 " interrupt to cpu %d\n", number);
231 }
232 else if ((olddir & bitvector) &&
233 !(dir[number] & bitvector))
234 {
235 // The bit was set and now its now clear and
236 // we were interrupting on that bit before
237 tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
238 DPRINTF(Tsunami, "dim write resulting in clear"
239 " dir interrupt to cpu %d\n", number);
240
241 }
242
243
244 }
245 }
246 } else {
247 switch(regnum) {
248 case TSDEV_CC_CSR:
249 panic("TSDEV_CC_CSR write\n");
250 case TSDEV_CC_MTR:
251 panic("TSDEV_CC_MTR write not implemented\n");
252 case TSDEV_CC_MISC:
253 uint64_t ipreq;
254 ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
255 //If it is bit 12-15, this is an IPI post
256 if (ipreq) {
257 reqIPI(ipreq);
258 supportedWrite = true;
259 }
260
261 //If it is bit 8-11, this is an IPI clear
262 uint64_t ipintr;
263 ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
264 if (ipintr) {
265 clearIPI(ipintr);
266 supportedWrite = true;
267 }
268
269 //If it is the 4-7th bit, clear the RTC interrupt
270 uint64_t itintr;
271 itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
272 if (itintr) {
273 clearITI(itintr);
274 supportedWrite = true;
275 }
276
277 // ignore NXMs
278 if (pkt->get<uint64_t>() & 0x10000000)
279 supportedWrite = true;
280
281 if(!supportedWrite)
282 panic("TSDEV_CC_MISC write not implemented\n");
283
284 break;
285 case TSDEV_CC_AAR0:
286 case TSDEV_CC_AAR1:
287 case TSDEV_CC_AAR2:
288 case TSDEV_CC_AAR3:
289 panic("TSDEV_CC_AARx write not implemeted\n");
290 case TSDEV_CC_DIM0:
291 case TSDEV_CC_DIM1:
292 case TSDEV_CC_DIM2:
293 case TSDEV_CC_DIM3:
294 int number;
295 if(regnum == TSDEV_CC_DIM0)
296 number = 0;
297 else if(regnum == TSDEV_CC_DIM1)
298 number = 1;
299 else if(regnum == TSDEV_CC_DIM2)
300 number = 2;
301 else
302 number = 3;
303
304 uint64_t bitvector;
305 uint64_t olddim;
306 uint64_t olddir;
307
308 olddim = dim[number];
309 olddir = dir[number];
310 dim[number] = pkt->get<uint64_t>();
311 dir[number] = dim[number] & drir;
312 for(int x = 0; x < 64; x++)
313 {
314 bitvector = ULL(1) << x;
315 // Figure out which bits have changed
316 if ((dim[number] & bitvector) != (olddim & bitvector))
317 {
318 // The bit is now set and it wasn't before (set)
319 if((dim[number] & bitvector) && (dir[number] & bitvector))
320 {
321 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
322 DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
323 }
324 else if ((olddir & bitvector) &&
325 !(dir[number] & bitvector))
326 {
327 // The bit was set and now its now clear and
328 // we were interrupting on that bit before
329 tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
330 DPRINTF(Tsunami, "dim write resulting in clear"
331 " dir interrupt to cpu %d\n",
332 x);
333
334 }
335
336
337 }
338 }
339 break;
340 case TSDEV_CC_DIR0:
341 case TSDEV_CC_DIR1:
342 case TSDEV_CC_DIR2:
343 case TSDEV_CC_DIR3:
344 panic("TSDEV_CC_DIR write not implemented\n");
345 case TSDEV_CC_DRIR:
346 panic("TSDEV_CC_DRIR write not implemented\n");
347 case TSDEV_CC_PRBEN:
348 panic("TSDEV_CC_PRBEN write not implemented\n");
349 case TSDEV_CC_IIC0:
350 case TSDEV_CC_IIC1:
351 case TSDEV_CC_IIC2:
352 case TSDEV_CC_IIC3:
353 panic("TSDEV_CC_IICx write not implemented\n");
354 case TSDEV_CC_MPR0:
355 case TSDEV_CC_MPR1:
356 case TSDEV_CC_MPR2:
357 case TSDEV_CC_MPR3:
358 panic("TSDEV_CC_MPRx write not implemented\n");
359 case TSDEV_CC_IPIR:
360 clearIPI(pkt->get<uint64_t>());
361 break;
362 case TSDEV_CC_ITIR:
363 clearITI(pkt->get<uint64_t>());
364 break;
365 case TSDEV_CC_IPIQ:
366 reqIPI(pkt->get<uint64_t>());
367 break;
368 default:
369 panic("default in cchip read reached, accessing 0x%x\n");
370 } // swtich(regnum)
371 } // not BIG_TSUNAMI write
372 pkt->makeAtomicResponse();
373 return pioDelay;
374}
375
376void
377TsunamiCChip::clearIPI(uint64_t ipintr)
378{
379 int numcpus = sys->threadContexts.size();
380 assert(numcpus <= Tsunami::Max_CPUs);
381
382 if (ipintr) {
383 for (int cpunum=0; cpunum < numcpus; cpunum++) {
384 // Check each cpu bit
385 uint64_t cpumask = ULL(1) << cpunum;
386 if (ipintr & cpumask) {
387 // Check if there is a pending ipi
388 if (ipint & cpumask) {
389 ipint &= ~cpumask;
390 tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
391 DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
392 }
393 else
394 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
395 }
396 }
397 }
398 else
399 panic("Big IPI Clear, but not processors indicated\n");
400}
401
402void
403TsunamiCChip::clearITI(uint64_t itintr)
404{
405 int numcpus = sys->threadContexts.size();
406 assert(numcpus <= Tsunami::Max_CPUs);
407
408 if (itintr) {
409 for (int i=0; i < numcpus; i++) {
410 uint64_t cpumask = ULL(1) << i;
411 if (itintr & cpumask & itint) {
412 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
413 itint &= ~cpumask;
414 DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
415 }
416 }
417 }
418 else
419 panic("Big ITI Clear, but not processors indicated\n");
420}
421
422void
423TsunamiCChip::reqIPI(uint64_t ipreq)
424{
425 int numcpus = sys->threadContexts.size();
426 assert(numcpus <= Tsunami::Max_CPUs);
427
428 if (ipreq) {
429 for (int cpunum=0; cpunum < numcpus; cpunum++) {
430 // Check each cpu bit
431 uint64_t cpumask = ULL(1) << cpunum;
432 if (ipreq & cpumask) {
433 // Check if there is already an ipi (bits 8:11)
434 if (!(ipint & cpumask)) {
435 ipint |= cpumask;
436 tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
437 DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
438 }
439 else
440 warn("post IPI for CPU=%d, but IPI already\n", cpunum);
441 }
442 }
443 }
444 else
445 panic("Big IPI Request, but not processors indicated\n");
446}
447
448
449void
450TsunamiCChip::postRTC()
451{
452 int size = sys->threadContexts.size();
453 assert(size <= Tsunami::Max_CPUs);
454
455 for (int i = 0; i < size; i++) {
456 uint64_t cpumask = ULL(1) << i;
457 if (!(cpumask & itint)) {
458 itint |= cpumask;
459 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
460 DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d\n", i);
461 }
462 }
463
464}
465
466void
467TsunamiCChip::postDRIR(uint32_t interrupt)
468{
469 uint64_t bitvector = ULL(1) << interrupt;
470 uint64_t size = sys->threadContexts.size();
471 assert(size <= Tsunami::Max_CPUs);
472 drir |= bitvector;
473
474 for(int i=0; i < size; i++) {
475 dir[i] = dim[i] & drir;
476 if (dim[i] & bitvector) {
477 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
478 DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
479 "interrupt %d\n",i, interrupt);
480 }
481 }
482}
483
484void
485TsunamiCChip::clearDRIR(uint32_t interrupt)
486{
487 uint64_t bitvector = ULL(1) << interrupt;
488 uint64_t size = sys->threadContexts.size();
489 assert(size <= Tsunami::Max_CPUs);
490
491 if (drir & bitvector)
492 {
493 drir &= ~bitvector;
494 for(int i=0; i < size; i++) {
495 if (dir[i] & bitvector) {
496 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
497 DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
498 "interrupt %d\n",i, interrupt);
499
500 }
501 dir[i] = dim[i] & drir;
502 }
503 }
504 else
505 DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
506}
507
508
509void
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