1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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82 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
83
84 Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
85 Addr daddr = (pkt->getAddr() - pioAddr);
86
87 switch (pkt->getSize()) {
88
89 case sizeof(uint64_t):
90 pkt->set(0);
91
92 if (daddr & TSDEV_CC_BDIMS)
93 {
94 pkt->set(dim[(daddr >> 4) & 0x3F]);
95 break;
96 }
97
98 if (daddr & TSDEV_CC_BDIRS)
99 {
100 pkt->set(dir[(daddr >> 4) & 0x3F]);
101 break;
102 }
103
104 switch(regnum) {
105 case TSDEV_CC_CSR:
106 pkt->set(0x0);
107 break;
108 case TSDEV_CC_MTR:
109 panic("TSDEV_CC_MTR not implemeted\n");
110 break;
111 case TSDEV_CC_MISC:
112 pkt->set(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) |
113 (pkt->req->contextId() & 0x3));
114 // currently, FS cannot handle MT so contextId and
115 // cpuId are effectively the same, don't know if it will
116 // matter if FS becomes MT enabled. I suspect no because
117 // we are currently able to boot up to 64 procs anyway
118 // which would render the CPUID of this register useless
119 // anyway
120 break;
121 case TSDEV_CC_AAR0:
122 case TSDEV_CC_AAR1:
123 case TSDEV_CC_AAR2:
124 case TSDEV_CC_AAR3:
125 pkt->set(0);
126 break;
127 case TSDEV_CC_DIM0:
128 pkt->set(dim[0]);
129 break;
130 case TSDEV_CC_DIM1:
131 pkt->set(dim[1]);
132 break;
133 case TSDEV_CC_DIM2:
134 pkt->set(dim[2]);
135 break;
136 case TSDEV_CC_DIM3:
137 pkt->set(dim[3]);
138 break;
139 case TSDEV_CC_DIR0:
140 pkt->set(dir[0]);
141 break;
142 case TSDEV_CC_DIR1:
143 pkt->set(dir[1]);
144 break;
145 case TSDEV_CC_DIR2:
146 pkt->set(dir[2]);
147 break;
148 case TSDEV_CC_DIR3:
149 pkt->set(dir[3]);
150 break;
151 case TSDEV_CC_DRIR:
152 pkt->set(drir);
153 break;
154 case TSDEV_CC_PRBEN:
155 panic("TSDEV_CC_PRBEN not implemented\n");
156 break;
157 case TSDEV_CC_IIC0:
158 case TSDEV_CC_IIC1:
159 case TSDEV_CC_IIC2:
160 case TSDEV_CC_IIC3:
161 panic("TSDEV_CC_IICx not implemented\n");
162 break;
163 case TSDEV_CC_MPR0:
164 case TSDEV_CC_MPR1:
165 case TSDEV_CC_MPR2:
166 case TSDEV_CC_MPR3:
167 panic("TSDEV_CC_MPRx not implemented\n");
168 break;
169 case TSDEV_CC_IPIR:
170 pkt->set(ipint);
171 break;
172 case TSDEV_CC_ITIR:
173 pkt->set(itint);
174 break;
175 default:
176 panic("default in cchip read reached, accessing 0x%x\n");
177 } // uint64_t
178
179 break;
180 case sizeof(uint32_t):
181 case sizeof(uint16_t):
182 case sizeof(uint8_t):
183 default:
184 panic("invalid access size(?) for tsunami register!\n");
185 }
186 DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
187 regnum, pkt->getSize(), pkt->get());
188
189 pkt->makeAtomicResponse();
190 return pioDelay;
191}
192
193Tick
194TsunamiCChip::write(PacketPtr pkt)
195{
196 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
197 Addr daddr = pkt->getAddr() - pioAddr;
198 Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
199
200
201 assert(pkt->getSize() == sizeof(uint64_t));
202
203 DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
204
205 bool supportedWrite = false;
206
207
208 if (daddr & TSDEV_CC_BDIMS)
209 {
210 int number = (daddr >> 4) & 0x3F;
211
212 uint64_t bitvector;
213 uint64_t olddim;
214 uint64_t olddir;
215
216 olddim = dim[number];
217 olddir = dir[number];
218 dim[number] = pkt->get();
219 dir[number] = dim[number] & drir;
220 for (int x = 0; x < Tsunami::Max_CPUs; x++)
221 {
222 bitvector = ULL(1) << x;
223 // Figure out which bits have changed
224 if ((dim[number] & bitvector) != (olddim & bitvector))
225 {
226 // The bit is now set and it wasn't before (set)

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247 } else {
248 switch(regnum) {
249 case TSDEV_CC_CSR:
250 panic("TSDEV_CC_CSR write\n");
251 case TSDEV_CC_MTR:
252 panic("TSDEV_CC_MTR write not implemented\n");
253 case TSDEV_CC_MISC:
254 uint64_t ipreq;
255 ipreq = (pkt->get() >> 12) & 0xF;
256 //If it is bit 12-15, this is an IPI post
257 if (ipreq) {
258 reqIPI(ipreq);
259 supportedWrite = true;
260 }
261
262 //If it is bit 8-11, this is an IPI clear
263 uint64_t ipintr;
264 ipintr = (pkt->get() >> 8) & 0xF;
265 if (ipintr) {
266 clearIPI(ipintr);
267 supportedWrite = true;
268 }
269
270 //If it is the 4-7th bit, clear the RTC interrupt
271 uint64_t itintr;
272 itintr = (pkt->get() >> 4) & 0xF;
273 if (itintr) {
274 clearITI(itintr);
275 supportedWrite = true;
276 }
277
278 // ignore NXMs
279 if (pkt->get() & 0x10000000)
280 supportedWrite = true;
281
282 if (!supportedWrite)
283 panic("TSDEV_CC_MISC write not implemented\n");
284
285 break;
286 case TSDEV_CC_AAR0:
287 case TSDEV_CC_AAR1:

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303 number = 3;
304
305 uint64_t bitvector;
306 uint64_t olddim;
307 uint64_t olddir;
308
309 olddim = dim[number];
310 olddir = dir[number];
311 dim[number] = pkt->get();
312 dir[number] = dim[number] & drir;
313 for (int x = 0; x < 64; x++)
314 {
315 bitvector = ULL(1) << x;
316 // Figure out which bits have changed
317 if ((dim[number] & bitvector) != (olddim & bitvector))
318 {
319 // The bit is now set and it wasn't before (set)

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353 case TSDEV_CC_IIC3:
354 panic("TSDEV_CC_IICx write not implemented\n");
355 case TSDEV_CC_MPR0:
356 case TSDEV_CC_MPR1:
357 case TSDEV_CC_MPR2:
358 case TSDEV_CC_MPR3:
359 panic("TSDEV_CC_MPRx write not implemented\n");
360 case TSDEV_CC_IPIR:
361 clearIPI(pkt->get());
362 break;
363 case TSDEV_CC_ITIR:
364 clearITI(pkt->get());
365 break;
366 case TSDEV_CC_IPIQ:
367 reqIPI(pkt->get());
368 break;
369 default:
370 panic("default in cchip read reached, accessing 0x%x\n");
371 } // swtich(regnum)
372 } // not BIG_TSUNAMI write
373 pkt->makeAtomicResponse();
374 return pioDelay;
375}

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