tsunami.hh (11168:f98eb2da15a4) tsunami.hh (11169:44b5c183c3cd)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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75 * The pchip is the interface to the PCI bus, in our case
76 * it does not have to do much.
77 */
78 TsunamiPChip *pchip;
79
80 int intr_sum_type[Tsunami::Max_CPUs];
81 int ipi_pending[Tsunami::Max_CPUs];
82
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 66 unchanged lines hidden (view full) ---

75 * The pchip is the interface to the PCI bus, in our case
76 * it does not have to do much.
77 */
78 TsunamiPChip *pchip;
79
80 int intr_sum_type[Tsunami::Max_CPUs];
81 int ipi_pending[Tsunami::Max_CPUs];
82
83 void init();
83 void init() override;
84
85 public:
86 typedef TsunamiParams Params;
87 Tsunami(const Params *p);
88
89 /**
90 * Cause the cpu to post a serial interrupt to the CPU.
91 */
84
85 public:
86 typedef TsunamiParams Params;
87 Tsunami(const Params *p);
88
89 /**
90 * Cause the cpu to post a serial interrupt to the CPU.
91 */
92 virtual void postConsoleInt();
92 void postConsoleInt() override;
93
94 /**
95 * Clear a posted CPU interrupt (id=55)
96 */
93
94 /**
95 * Clear a posted CPU interrupt (id=55)
96 */
97 virtual void clearConsoleInt();
97 void clearConsoleInt() override;
98
99 /**
100 * Cause the chipset to post a cpi interrupt to the CPU.
101 */
98
99 /**
100 * Cause the chipset to post a cpi interrupt to the CPU.
101 */
102 virtual void postPciInt(int line);
102 void postPciInt(int line) override;
103
104 /**
105 * Clear a posted PCI->CPU interrupt
106 */
103
104 /**
105 * Clear a posted PCI->CPU interrupt
106 */
107 virtual void clearPciInt(int line);
107 void clearPciInt(int line) override;
108
109
108
109
110 virtual Addr pciToDma(Addr pciAddr) const;
110 Addr pciToDma(Addr pciAddr) const override;
111
112 /**
113 * Calculate the configuration address given a bus/dev/func.
114 */
111
112 /**
113 * Calculate the configuration address given a bus/dev/func.
114 */
115 virtual Addr calcPciConfigAddr(int bus, int dev, int func);
115 Addr calcPciConfigAddr(int bus, int dev, int func) override;
116
117 /**
118 * Calculate the address for an IO location on the PCI bus.
119 */
116
117 /**
118 * Calculate the address for an IO location on the PCI bus.
119 */
120 virtual Addr calcPciIOAddr(Addr addr);
120 Addr calcPciIOAddr(Addr addr) override;
121
122 /**
123 * Calculate the address for a memory location on the PCI bus.
124 */
121
122 /**
123 * Calculate the address for a memory location on the PCI bus.
124 */
125 virtual Addr calcPciMemAddr(Addr addr);
125 Addr calcPciMemAddr(Addr addr) override;
126
127 void serialize(CheckpointOut &cp) const override;
128 void unserialize(CheckpointIn &cp) override;
129};
130
131#endif // __DEV_TSUNAMI_HH__
126
127 void serialize(CheckpointOut &cp) const override;
128 void unserialize(CheckpointIn &cp) override;
129};
130
131#endif // __DEV_TSUNAMI_HH__