1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/**
32 * @file
33 * Declaration of top level class for the Tsunami chipset. This class just
34 * retains pointers to all its children so the children can communicate.
35 */
36
37#ifndef __DEV_TSUNAMI_HH__
38#define __DEV_TSUNAMI_HH__
39
40#include "dev/platform.hh"
41#include "params/Tsunami.hh"
42
43class IdeController;
44class TsunamiCChip;
45class TsunamiPChip;
46class TsunamiIO;
47class System;
48
49/**
50 * Top level class for Tsunami Chipset emulation.
51 * This structure just contains pointers to all the
52 * children so the children can commnicate to do the
53 * read work
54 */
55
56class Tsunami : public Platform
57{
58 public:
59 /** Max number of CPUs in a Tsunami */
60 static const int Max_CPUs = 64;
61
62 /** Pointer to the system */
63 System *system;
64
65 /** Pointer to the TsunamiIO device which has the RTC */
66 TsunamiIO *io;
67
68 /** Pointer to the Tsunami CChip.
69 * The chip contains some configuration information and
70 * all the interrupt mask and status registers
71 */
72 TsunamiCChip *cchip;
73
74 /** Pointer to the Tsunami PChip.
75 * The pchip is the interface to the PCI bus, in our case
76 * it does not have to do much.
77 */
78 TsunamiPChip *pchip;
79
80 int intr_sum_type[Tsunami::Max_CPUs];
81 int ipi_pending[Tsunami::Max_CPUs];
82
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/**
32 * @file
33 * Declaration of top level class for the Tsunami chipset. This class just
34 * retains pointers to all its children so the children can communicate.
35 */
36
37#ifndef __DEV_TSUNAMI_HH__
38#define __DEV_TSUNAMI_HH__
39
40#include "dev/platform.hh"
41#include "params/Tsunami.hh"
42
43class IdeController;
44class TsunamiCChip;
45class TsunamiPChip;
46class TsunamiIO;
47class System;
48
49/**
50 * Top level class for Tsunami Chipset emulation.
51 * This structure just contains pointers to all the
52 * children so the children can commnicate to do the
53 * read work
54 */
55
56class Tsunami : public Platform
57{
58 public:
59 /** Max number of CPUs in a Tsunami */
60 static const int Max_CPUs = 64;
61
62 /** Pointer to the system */
63 System *system;
64
65 /** Pointer to the TsunamiIO device which has the RTC */
66 TsunamiIO *io;
67
68 /** Pointer to the Tsunami CChip.
69 * The chip contains some configuration information and
70 * all the interrupt mask and status registers
71 */
72 TsunamiCChip *cchip;
73
74 /** Pointer to the Tsunami PChip.
75 * The pchip is the interface to the PCI bus, in our case
76 * it does not have to do much.
77 */
78 TsunamiPChip *pchip;
79
80 int intr_sum_type[Tsunami::Max_CPUs];
81 int ipi_pending[Tsunami::Max_CPUs];
82
|
83 void init();
| 83 void init() override;
|
84
85 public:
86 typedef TsunamiParams Params;
87 Tsunami(const Params *p);
88
89 /**
90 * Cause the cpu to post a serial interrupt to the CPU.
91 */
| 84
85 public:
86 typedef TsunamiParams Params;
87 Tsunami(const Params *p);
88
89 /**
90 * Cause the cpu to post a serial interrupt to the CPU.
91 */
|
92 virtual void postConsoleInt();
| 92 void postConsoleInt() override;
|
93
94 /**
95 * Clear a posted CPU interrupt (id=55)
96 */
| 93
94 /**
95 * Clear a posted CPU interrupt (id=55)
96 */
|
97 virtual void clearConsoleInt();
| 97 void clearConsoleInt() override;
|
98
99 /**
100 * Cause the chipset to post a cpi interrupt to the CPU.
101 */
| 98
99 /**
100 * Cause the chipset to post a cpi interrupt to the CPU.
101 */
|
102 virtual void postPciInt(int line);
| 102 void postPciInt(int line) override;
|
103
104 /**
105 * Clear a posted PCI->CPU interrupt
106 */
| 103
104 /**
105 * Clear a posted PCI->CPU interrupt
106 */
|
107 virtual void clearPciInt(int line);
| 107 void clearPciInt(int line) override;
|
108
109
| 108
109
|
110 virtual Addr pciToDma(Addr pciAddr) const;
| 110 Addr pciToDma(Addr pciAddr) const override;
|
111
112 /**
113 * Calculate the configuration address given a bus/dev/func.
114 */
| 111
112 /**
113 * Calculate the configuration address given a bus/dev/func.
114 */
|
115 virtual Addr calcPciConfigAddr(int bus, int dev, int func);
| 115 Addr calcPciConfigAddr(int bus, int dev, int func) override;
|
116
117 /**
118 * Calculate the address for an IO location on the PCI bus.
119 */
| 116
117 /**
118 * Calculate the address for an IO location on the PCI bus.
119 */
|
120 virtual Addr calcPciIOAddr(Addr addr);
| 120 Addr calcPciIOAddr(Addr addr) override;
|
121
122 /**
123 * Calculate the address for a memory location on the PCI bus.
124 */
| 121
122 /**
123 * Calculate the address for a memory location on the PCI bus.
124 */
|
125 virtual Addr calcPciMemAddr(Addr addr);
| 125 Addr calcPciMemAddr(Addr addr) override;
|
126
127 void serialize(CheckpointOut &cp) const override;
128 void unserialize(CheckpointIn &cp) override;
129};
130
131#endif // __DEV_TSUNAMI_HH__
| 126
127 void serialize(CheckpointOut &cp) const override;
128 void unserialize(CheckpointIn &cp) override;
129};
130
131#endif // __DEV_TSUNAMI_HH__
|