1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/** @file
32 * Implementation of Tsunami platform.
33 */
34
35#include <deque>
36#include <string>
37#include <vector>
38
39#include "cpu/intr_control.hh"
40#include "dev/simconsole.hh"
41#include "dev/alpha/tsunami_cchip.hh"
42#include "dev/alpha/tsunami_pchip.hh"
43#include "dev/alpha/tsunami_io.hh"
44#include "dev/alpha/tsunami.hh"
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/** @file
32 * Implementation of Tsunami platform.
33 */
34
35#include <deque>
36#include <string>
37#include <vector>
38
39#include "cpu/intr_control.hh"
40#include "dev/simconsole.hh"
41#include "dev/alpha/tsunami_cchip.hh"
42#include "dev/alpha/tsunami_pchip.hh"
43#include "dev/alpha/tsunami_io.hh"
44#include "dev/alpha/tsunami.hh"
|
45#include "sim/builder.hh"
| 45#include "params/Tsunami.hh"
|
46#include "sim/system.hh"
47
48using namespace std;
49//Should this be AlphaISA?
50using namespace TheISA;
51
52Tsunami::Tsunami(const string &name, System *s, IntrControl *ic)
53 : Platform(name, ic), system(s)
54{
55 // set the back pointer from the system to myself
56 system->platform = this;
57
58 for (int i = 0; i < Tsunami::Max_CPUs; i++)
59 intr_sum_type[i] = 0;
60}
61
62Tick
63Tsunami::intrFrequency()
64{
65 return io->frequency();
66}
67
68void
69Tsunami::postConsoleInt()
70{
71 io->postPIC(0x10);
72}
73
74void
75Tsunami::clearConsoleInt()
76{
77 io->clearPIC(0x10);
78}
79
80void
81Tsunami::postPciInt(int line)
82{
83 cchip->postDRIR(line);
84}
85
86void
87Tsunami::clearPciInt(int line)
88{
89 cchip->clearDRIR(line);
90}
91
92Addr
93Tsunami::pciToDma(Addr pciAddr) const
94{
95 return pchip->translatePciToDma(pciAddr);
96}
97
98
99Addr
100Tsunami::calcConfigAddr(int bus, int dev, int func)
101{
102 return pchip->calcConfigAddr(bus, dev, func);
103}
104
105void
106Tsunami::serialize(std::ostream &os)
107{
108 SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
109}
110
111void
112Tsunami::unserialize(Checkpoint *cp, const std::string §ion)
113{
114 UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
115}
116
| 46#include "sim/system.hh"
47
48using namespace std;
49//Should this be AlphaISA?
50using namespace TheISA;
51
52Tsunami::Tsunami(const string &name, System *s, IntrControl *ic)
53 : Platform(name, ic), system(s)
54{
55 // set the back pointer from the system to myself
56 system->platform = this;
57
58 for (int i = 0; i < Tsunami::Max_CPUs; i++)
59 intr_sum_type[i] = 0;
60}
61
62Tick
63Tsunami::intrFrequency()
64{
65 return io->frequency();
66}
67
68void
69Tsunami::postConsoleInt()
70{
71 io->postPIC(0x10);
72}
73
74void
75Tsunami::clearConsoleInt()
76{
77 io->clearPIC(0x10);
78}
79
80void
81Tsunami::postPciInt(int line)
82{
83 cchip->postDRIR(line);
84}
85
86void
87Tsunami::clearPciInt(int line)
88{
89 cchip->clearDRIR(line);
90}
91
92Addr
93Tsunami::pciToDma(Addr pciAddr) const
94{
95 return pchip->translatePciToDma(pciAddr);
96}
97
98
99Addr
100Tsunami::calcConfigAddr(int bus, int dev, int func)
101{
102 return pchip->calcConfigAddr(bus, dev, func);
103}
104
105void
106Tsunami::serialize(std::ostream &os)
107{
108 SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
109}
110
111void
112Tsunami::unserialize(Checkpoint *cp, const std::string §ion)
113{
114 UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
115}
116
|
117BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
118
119 SimObjectParam<System *> system;
120 SimObjectParam<IntrControl *> intrctrl;
121
122END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
123
124BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
125
126 INIT_PARAM(system, "system"),
127 INIT_PARAM(intrctrl, "interrupt controller")
128
129END_INIT_SIM_OBJECT_PARAMS(Tsunami)
130
131CREATE_SIM_OBJECT(Tsunami)
| 117Tsunami *
118TsunamiParams::create()
|
132{
| 119{
|
133 return new Tsunami(getInstanceName(), system, intrctrl);
| 120 return new Tsunami(name, system, intrctrl);
|
134}
| 121}
|
135
136REGISTER_SIM_OBJECT("Tsunami", Tsunami)
| |
| |