Tsunami.py (7523:9c8fdcdae976) | Tsunami.py (8839:eeb293859255) |
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1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 79 unchanged lines hidden (view full) --- 88 io = TsunamiIO(pio_addr=0x801fc000000) 89 uart = Uart8250(pio_addr=0x801fc0003f8) 90 backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk) 91 92 # Attach I/O devices to specified bus object. Can't do this 93 # earlier, since the bus object itself is typically defined at the 94 # System level. 95 def attachIO(self, bus): | 1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 79 unchanged lines hidden (view full) --- 88 io = TsunamiIO(pio_addr=0x801fc000000) 89 uart = Uart8250(pio_addr=0x801fc0003f8) 90 backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk) 91 92 # Attach I/O devices to specified bus object. Can't do this 93 # earlier, since the bus object itself is typically defined at the 94 # System level. 95 def attachIO(self, bus): |
96 self.cchip.pio = bus.port 97 self.pchip.pio = bus.port | 96 self.cchip.pio = bus.master 97 self.pchip.pio = bus.master |
98 self.pciconfig.pio = bus.default 99 bus.use_default_range = True | 98 self.pciconfig.pio = bus.default 99 bus.use_default_range = True |
100 self.fake_sm_chip.pio = bus.port 101 self.fake_uart1.pio = bus.port 102 self.fake_uart2.pio = bus.port 103 self.fake_uart3.pio = bus.port 104 self.fake_uart4.pio = bus.port 105 self.fake_ppc.pio = bus.port 106 self.fake_OROM.pio = bus.port 107 self.fake_pnp_addr.pio = bus.port 108 self.fake_pnp_write.pio = bus.port 109 self.fake_pnp_read0.pio = bus.port 110 self.fake_pnp_read1.pio = bus.port 111 self.fake_pnp_read2.pio = bus.port 112 self.fake_pnp_read3.pio = bus.port 113 self.fake_pnp_read4.pio = bus.port 114 self.fake_pnp_read5.pio = bus.port 115 self.fake_pnp_read6.pio = bus.port 116 self.fake_pnp_read7.pio = bus.port 117 self.fake_ata0.pio = bus.port 118 self.fake_ata1.pio = bus.port 119 self.fb.pio = bus.port 120 self.io.pio = bus.port 121 self.uart.pio = bus.port 122 self.backdoor.pio = bus.port | 100 self.fake_sm_chip.pio = bus.master 101 self.fake_uart1.pio = bus.master 102 self.fake_uart2.pio = bus.master 103 self.fake_uart3.pio = bus.master 104 self.fake_uart4.pio = bus.master 105 self.fake_ppc.pio = bus.master 106 self.fake_OROM.pio = bus.master 107 self.fake_pnp_addr.pio = bus.master 108 self.fake_pnp_write.pio = bus.master 109 self.fake_pnp_read0.pio = bus.master 110 self.fake_pnp_read1.pio = bus.master 111 self.fake_pnp_read2.pio = bus.master 112 self.fake_pnp_read3.pio = bus.master 113 self.fake_pnp_read4.pio = bus.master 114 self.fake_pnp_read5.pio = bus.master 115 self.fake_pnp_read6.pio = bus.master 116 self.fake_pnp_read7.pio = bus.master 117 self.fake_ata0.pio = bus.master 118 self.fake_ata1.pio = bus.master 119 self.fb.pio = bus.master 120 self.io.pio = bus.master 121 self.uart.pio = bus.master 122 self.backdoor.pio = bus.master |