Tsunami.py (5478:ca055528a3b3) Tsunami.py (5480:b9460d7f74f0)
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Nathan Binkert
28
29from m5.params import *
30from m5.proxy import *
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Nathan Binkert
28
29from m5.params import *
30from m5.proxy import *
31from BadDevice import BadDevice
32from AlphaBackdoor import AlphaBackdoor
31from Device import BasicPioDevice, IsaFake, BadAddr
33from Device import BasicPioDevice, IsaFake, BadAddr
34from Pci import PciConfigAll
32from Platform import Platform
35from Platform import Platform
33from AlphaConsole import AlphaConsole
34from Uart import Uart8250
36from Uart import Uart8250
35from Pci import PciConfigAll
36from BadDevice import BadDevice
37
38class TsunamiCChip(BasicPioDevice):
39 type = 'TsunamiCChip'
40 tsunami = Param.Tsunami(Parent.any, "Tsunami")
41
42class TsunamiIO(BasicPioDevice):
43 type = 'TsunamiIO'
44 time = Param.Time('01/01/2009',

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82 fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
83
84 fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
85 fake_ata1 = IsaFake(pio_addr=0x801fc000170)
86
87 fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
88 io = TsunamiIO(pio_addr=0x801fc000000)
89 uart = Uart8250(pio_addr=0x801fc0003f8)
37
38class TsunamiCChip(BasicPioDevice):
39 type = 'TsunamiCChip'
40 tsunami = Param.Tsunami(Parent.any, "Tsunami")
41
42class TsunamiIO(BasicPioDevice):
43 type = 'TsunamiIO'
44 time = Param.Time('01/01/2009',

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82 fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
83
84 fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
85 fake_ata1 = IsaFake(pio_addr=0x801fc000170)
86
87 fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
88 io = TsunamiIO(pio_addr=0x801fc000000)
89 uart = Uart8250(pio_addr=0x801fc0003f8)
90 alpha_console = AlphaConsole(pio_addr=0x80200000000,
91 disk=Parent.simple_disk)
90 backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk)
92
93 # Attach I/O devices to specified bus object. Can't do this
94 # earlier, since the bus object itself is typically defined at the
95 # System level.
96 def attachIO(self, bus):
97 self.cchip.pio = bus.port
98 self.pchip.pio = bus.port
99 self.pciconfig.pio = bus.default

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116 self.fake_pnp_read5.pio = bus.port
117 self.fake_pnp_read6.pio = bus.port
118 self.fake_pnp_read7.pio = bus.port
119 self.fake_ata0.pio = bus.port
120 self.fake_ata1.pio = bus.port
121 self.fb.pio = bus.port
122 self.io.pio = bus.port
123 self.uart.pio = bus.port
91
92 # Attach I/O devices to specified bus object. Can't do this
93 # earlier, since the bus object itself is typically defined at the
94 # System level.
95 def attachIO(self, bus):
96 self.cchip.pio = bus.port
97 self.pchip.pio = bus.port
98 self.pciconfig.pio = bus.default

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115 self.fake_pnp_read5.pio = bus.port
116 self.fake_pnp_read6.pio = bus.port
117 self.fake_pnp_read7.pio = bus.port
118 self.fake_ata0.pio = bus.port
119 self.fake_ata1.pio = bus.port
120 self.fb.pio = bus.port
121 self.io.pio = bus.port
122 self.uart.pio = bus.port
124 self.alpha_console.pio = bus.port
123 self.backdoor.pio = bus.port