1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Nathan Binkert
28
29from m5.params import *
30from m5.proxy import *
| 1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Nathan Binkert
28
29from m5.params import *
30from m5.proxy import *
|
| 31from BadDevice import BadDevice
32from AlphaBackdoor import AlphaBackdoor
|
31from Device import BasicPioDevice, IsaFake, BadAddr
| 33from Device import BasicPioDevice, IsaFake, BadAddr
|
| 34from Pci import PciConfigAll
|
32from Platform import Platform
| 35from Platform import Platform
|
33from AlphaConsole import AlphaConsole
| |
34from Uart import Uart8250
| 36from Uart import Uart8250
|
35from Pci import PciConfigAll
36from BadDevice import BadDevice
| |
37
38class TsunamiCChip(BasicPioDevice):
39 type = 'TsunamiCChip'
40 tsunami = Param.Tsunami(Parent.any, "Tsunami")
41
42class TsunamiIO(BasicPioDevice):
43 type = 'TsunamiIO'
44 time = Param.Time('01/01/2009',
45 "System time to use ('Now' for actual time)")
46 year_is_bcd = Param.Bool(False,
47 "The RTC should interpret the year as a BCD value")
48 tsunami = Param.Tsunami(Parent.any, "Tsunami")
49 frequency = Param.Frequency('1024Hz', "frequency of interrupts")
50
51class TsunamiPChip(BasicPioDevice):
52 type = 'TsunamiPChip'
53 tsunami = Param.Tsunami(Parent.any, "Tsunami")
54
55class Tsunami(Platform):
56 type = 'Tsunami'
57 system = Param.System(Parent.any, "system")
58
59 cchip = TsunamiCChip(pio_addr=0x801a0000000)
60 pchip = TsunamiPChip(pio_addr=0x80180000000)
61 pciconfig = PciConfigAll()
62 fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
63
64 fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
65 fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
66 fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
67 fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
68
69 fake_ppc = IsaFake(pio_addr=0x801fc0003bb)
70
71 fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
72
73 fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
74 fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
75 fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
76 fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
77 fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
78 fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
79 fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
80 fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
81 fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
82 fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
83
84 fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
85 fake_ata1 = IsaFake(pio_addr=0x801fc000170)
86
87 fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
88 io = TsunamiIO(pio_addr=0x801fc000000)
89 uart = Uart8250(pio_addr=0x801fc0003f8)
| 37
38class TsunamiCChip(BasicPioDevice):
39 type = 'TsunamiCChip'
40 tsunami = Param.Tsunami(Parent.any, "Tsunami")
41
42class TsunamiIO(BasicPioDevice):
43 type = 'TsunamiIO'
44 time = Param.Time('01/01/2009',
45 "System time to use ('Now' for actual time)")
46 year_is_bcd = Param.Bool(False,
47 "The RTC should interpret the year as a BCD value")
48 tsunami = Param.Tsunami(Parent.any, "Tsunami")
49 frequency = Param.Frequency('1024Hz', "frequency of interrupts")
50
51class TsunamiPChip(BasicPioDevice):
52 type = 'TsunamiPChip'
53 tsunami = Param.Tsunami(Parent.any, "Tsunami")
54
55class Tsunami(Platform):
56 type = 'Tsunami'
57 system = Param.System(Parent.any, "system")
58
59 cchip = TsunamiCChip(pio_addr=0x801a0000000)
60 pchip = TsunamiPChip(pio_addr=0x80180000000)
61 pciconfig = PciConfigAll()
62 fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
63
64 fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
65 fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
66 fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
67 fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
68
69 fake_ppc = IsaFake(pio_addr=0x801fc0003bb)
70
71 fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
72
73 fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
74 fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
75 fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
76 fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
77 fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
78 fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
79 fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
80 fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
81 fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
82 fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
83
84 fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
85 fake_ata1 = IsaFake(pio_addr=0x801fc000170)
86
87 fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
88 io = TsunamiIO(pio_addr=0x801fc000000)
89 uart = Uart8250(pio_addr=0x801fc0003f8)
|
90 alpha_console = AlphaConsole(pio_addr=0x80200000000,
91 disk=Parent.simple_disk)
| 90 backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk)
|
92
93 # Attach I/O devices to specified bus object. Can't do this
94 # earlier, since the bus object itself is typically defined at the
95 # System level.
96 def attachIO(self, bus):
97 self.cchip.pio = bus.port
98 self.pchip.pio = bus.port
99 self.pciconfig.pio = bus.default
100 bus.responder_set = True
101 bus.responder = self.pciconfig
102 self.fake_sm_chip.pio = bus.port
103 self.fake_uart1.pio = bus.port
104 self.fake_uart2.pio = bus.port
105 self.fake_uart3.pio = bus.port
106 self.fake_uart4.pio = bus.port
107 self.fake_ppc.pio = bus.port
108 self.fake_OROM.pio = bus.port
109 self.fake_pnp_addr.pio = bus.port
110 self.fake_pnp_write.pio = bus.port
111 self.fake_pnp_read0.pio = bus.port
112 self.fake_pnp_read1.pio = bus.port
113 self.fake_pnp_read2.pio = bus.port
114 self.fake_pnp_read3.pio = bus.port
115 self.fake_pnp_read4.pio = bus.port
116 self.fake_pnp_read5.pio = bus.port
117 self.fake_pnp_read6.pio = bus.port
118 self.fake_pnp_read7.pio = bus.port
119 self.fake_ata0.pio = bus.port
120 self.fake_ata1.pio = bus.port
121 self.fb.pio = bus.port
122 self.io.pio = bus.port
123 self.uart.pio = bus.port
| 91
92 # Attach I/O devices to specified bus object. Can't do this
93 # earlier, since the bus object itself is typically defined at the
94 # System level.
95 def attachIO(self, bus):
96 self.cchip.pio = bus.port
97 self.pchip.pio = bus.port
98 self.pciconfig.pio = bus.default
99 bus.responder_set = True
100 bus.responder = self.pciconfig
101 self.fake_sm_chip.pio = bus.port
102 self.fake_uart1.pio = bus.port
103 self.fake_uart2.pio = bus.port
104 self.fake_uart3.pio = bus.port
105 self.fake_uart4.pio = bus.port
106 self.fake_ppc.pio = bus.port
107 self.fake_OROM.pio = bus.port
108 self.fake_pnp_addr.pio = bus.port
109 self.fake_pnp_write.pio = bus.port
110 self.fake_pnp_read0.pio = bus.port
111 self.fake_pnp_read1.pio = bus.port
112 self.fake_pnp_read2.pio = bus.port
113 self.fake_pnp_read3.pio = bus.port
114 self.fake_pnp_read4.pio = bus.port
115 self.fake_pnp_read5.pio = bus.port
116 self.fake_pnp_read6.pio = bus.port
117 self.fake_pnp_read7.pio = bus.port
118 self.fake_ata0.pio = bus.port
119 self.fake_ata1.pio = bus.port
120 self.fb.pio = bus.port
121 self.io.pio = bus.port
122 self.uart.pio = bus.port
|
124 self.alpha_console.pio = bus.port
| 123 self.backdoor.pio = bus.port
|
| |