Device.py (9198:dd9d98c16121) Device.py (9338:97b4a2be1e5b)
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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27# Authors: Nathan Binkert
28
29from m5.params import *
30from m5.proxy import *
31from MemObject import MemObject
32
33class PioDevice(MemObject):
34 type = 'PioDevice'
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 18 unchanged lines hidden (view full) ---

27# Authors: Nathan Binkert
28
29from m5.params import *
30from m5.proxy import *
31from MemObject import MemObject
32
33class PioDevice(MemObject):
34 type = 'PioDevice'
35 cxx_header = "dev/io_device.hh"
35 abstract = True
36 pio = SlavePort("Programmed I/O port")
37 system = Param.System(Parent.any, "System this device is part of")
38
39class BasicPioDevice(PioDevice):
40 type = 'BasicPioDevice'
36 abstract = True
37 pio = SlavePort("Programmed I/O port")
38 system = Param.System(Parent.any, "System this device is part of")
39
40class BasicPioDevice(PioDevice):
41 type = 'BasicPioDevice'
42 cxx_header = "dev/io_device.hh"
41 abstract = True
42 pio_addr = Param.Addr("Device Address")
43 pio_latency = Param.Latency('100ns', "Programmed IO latency")
44
45class DmaDevice(PioDevice):
46 type = 'DmaDevice'
43 abstract = True
44 pio_addr = Param.Addr("Device Address")
45 pio_latency = Param.Latency('100ns', "Programmed IO latency")
46
47class DmaDevice(PioDevice):
48 type = 'DmaDevice'
49 cxx_header = "dev/io_device.hh"
47 abstract = True
48 dma = MasterPort("DMA port")
49
50
51class IsaFake(BasicPioDevice):
52 type = 'IsaFake'
50 abstract = True
51 dma = MasterPort("DMA port")
52
53
54class IsaFake(BasicPioDevice):
55 type = 'IsaFake'
56 cxx_header = "dev/io_device.hh"
53 pio_size = Param.Addr(0x8, "Size of address range")
54 ret_data8 = Param.UInt8(0xFF, "Default data to return")
55 ret_data16 = Param.UInt16(0xFFFF, "Default data to return")
56 ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return")
57 ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return")
58 ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access")
59 update_data = Param.Bool(False, "Update the data that is returned on writes")
60 warn_access = Param.String("", "String to print when device is accessed")
61 fake_mem = Param.Bool(False,
62 "Is this device acting like a memory and thus may get a cache line sized req")
63
64class BadAddr(IsaFake):
65 pio_addr = 0
66 ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access")
67
68
57 pio_size = Param.Addr(0x8, "Size of address range")
58 ret_data8 = Param.UInt8(0xFF, "Default data to return")
59 ret_data16 = Param.UInt16(0xFFFF, "Default data to return")
60 ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return")
61 ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return")
62 ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access")
63 update_data = Param.Bool(False, "Update the data that is returned on writes")
64 warn_access = Param.String("", "String to print when device is accessed")
65 fake_mem = Param.Bool(False,
66 "Is this device acting like a memory and thus may get a cache line sized req")
67
68class BadAddr(IsaFake):
69 pio_addr = 0
70 ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access")
71
72