translation.hh (10824:308771bd2647) translation.hh (12749:223c83ed9979)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 64 unchanged lines hidden (view full) ---

73 uint8_t *data;
74 uint64_t *res;
75 BaseTLB::Mode mode;
76
77 /**
78 * Single translation state. We set the number of outstanding
79 * translations to one and indicate that it is not split.
80 */
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 64 unchanged lines hidden (view full) ---

73 uint8_t *data;
74 uint64_t *res;
75 BaseTLB::Mode mode;
76
77 /**
78 * Single translation state. We set the number of outstanding
79 * translations to one and indicate that it is not split.
80 */
81 WholeTranslationState(RequestPtr _req, uint8_t *_data, uint64_t *_res,
82 BaseTLB::Mode _mode)
81 WholeTranslationState(const RequestPtr &_req, uint8_t *_data,
82 uint64_t *_res, BaseTLB::Mode _mode)
83 : outstanding(1), delay(false), isSplit(false), mainReq(_req),
84 sreqLow(NULL), sreqHigh(NULL), data(_data), res(_res), mode(_mode)
85 {
86 faults[0] = faults[1] = NoFault;
87 assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
88 }
89
90 /**
91 * Split translation state. We copy all state into this class, set the
92 * number of outstanding translations to two and then mark this as a
93 * split translation.
94 */
83 : outstanding(1), delay(false), isSplit(false), mainReq(_req),
84 sreqLow(NULL), sreqHigh(NULL), data(_data), res(_res), mode(_mode)
85 {
86 faults[0] = faults[1] = NoFault;
87 assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
88 }
89
90 /**
91 * Split translation state. We copy all state into this class, set the
92 * number of outstanding translations to two and then mark this as a
93 * split translation.
94 */
95 WholeTranslationState(RequestPtr _req, RequestPtr _sreqLow,
96 RequestPtr _sreqHigh, uint8_t *_data, uint64_t *_res,
97 BaseTLB::Mode _mode)
95 WholeTranslationState(const RequestPtr &_req, const RequestPtr &_sreqLow,
96 const RequestPtr &_sreqHigh, uint8_t *_data,
97 uint64_t *_res, BaseTLB::Mode _mode)
98 : outstanding(2), delay(false), isSplit(true), mainReq(_req),
99 sreqLow(_sreqLow), sreqHigh(_sreqHigh), data(_data), res(_res),
100 mode(_mode)
101 {
102 faults[0] = faults[1] = NoFault;
103 assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
104 }
105

--- 85 unchanged lines hidden (view full) ---

191 {
192 return mainReq->getFlags();
193 }
194
195 /** Delete all requests that make up this translation. */
196 void
197 deleteReqs()
198 {
98 : outstanding(2), delay(false), isSplit(true), mainReq(_req),
99 sreqLow(_sreqLow), sreqHigh(_sreqHigh), data(_data), res(_res),
100 mode(_mode)
101 {
102 faults[0] = faults[1] = NoFault;
103 assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
104 }
105

--- 85 unchanged lines hidden (view full) ---

191 {
192 return mainReq->getFlags();
193 }
194
195 /** Delete all requests that make up this translation. */
196 void
197 deleteReqs()
198 {
199 delete mainReq;
199 mainReq.reset();
200 if (isSplit) {
200 if (isSplit) {
201 delete sreqLow;
202 delete sreqHigh;
201 sreqLow.reset();
202 sreqHigh.reset();
203 }
204 }
205};
206
207
208/**
209 * This class represents part of a data address translation. All state for
210 * the translation is held in WholeTranslationState (above). Therefore this

--- 33 unchanged lines hidden (view full) ---

244 state->delay = true;
245 }
246
247 /**
248 * Finish this part of the translation and indicate that the whole
249 * translation is complete if the state says so.
250 */
251 void
203 }
204 }
205};
206
207
208/**
209 * This class represents part of a data address translation. All state for
210 * the translation is held in WholeTranslationState (above). Therefore this

--- 33 unchanged lines hidden (view full) ---

244 state->delay = true;
245 }
246
247 /**
248 * Finish this part of the translation and indicate that the whole
249 * translation is complete if the state says so.
250 */
251 void
252 finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
252 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
253 BaseTLB::Mode mode)
254 {
255 assert(state);
256 assert(mode == state->mode);
257 if (state->finish(fault, index)) {
258 if (state->getFault() == NoFault) {
259 // Don't access the request if faulted (due to squash)
260 req->setTranslateLatency();

--- 14 unchanged lines hidden --- 		253 BaseTLB::Mode mode)
254 {
255 assert(state);
256 assert(mode == state->mode);
257 if (state->finish(fault, index)) {
258 if (state->getFault() == NoFault) {
259 // Don't access the request if faulted (due to squash)
260 req->setTranslateLatency();

--- 14 unchanged lines hidden ---