| trace_cpu.hh (12085:de78ea63e0ca) | trace_cpu.hh (14198:9c2f67392409) |
|---|---|
| 1/* 2 * Copyright (c) 2013 - 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1132 unchanged lines hidden (view full) --- 1141 /** Stat for number of simulated micro-ops. */ 1142 Stats::Scalar numOps; 1143 /** Stat for the CPI. This is really cycles per micro-op and not inst. */ 1144 Stats::Formula cpi; 1145 1146 public: 1147 1148 /** Used to get a reference to the icache port. */ | 1/* 2 * Copyright (c) 2013 - 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1132 unchanged lines hidden (view full) --- 1141 /** Stat for number of simulated micro-ops. */ 1142 Stats::Scalar numOps; 1143 /** Stat for the CPI. This is really cycles per micro-op and not inst. */ 1144 Stats::Formula cpi; 1145 1146 public: 1147 1148 /** Used to get a reference to the icache port. */ |
| 1149 MasterPort &getInstPort() { return icachePort; } | 1149 Port &getInstPort() { return icachePort; } |
| 1150 1151 /** Used to get a reference to the dcache port. */ | 1150 1151 /** Used to get a reference to the dcache port. */ |
| 1152 MasterPort &getDataPort() { return dcachePort; } | 1152 Port &getDataPort() { return dcachePort; } |
| 1153 1154 void regStats(); 1155}; 1156#endif // __CPU_TRACE_TRACE_CPU_HH__ | 1153 1154 void regStats(); 1155}; 1156#endif // __CPU_TRACE_TRACE_CPU_HH__ |