trace_cpu.cc (12680:91f4d6668b4f) trace_cpu.cc (12749:223c83ed9979)
1/*
2 * Copyright (c) 2013 - 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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657 unsigned blk_size = owner.cacheLineSize();
658 Addr blk_offset = (node_ptr->physAddr & (Addr)(blk_size - 1));
659 if (!(blk_offset + node_ptr->size <= blk_size)) {
660 node_ptr->size = blk_size - blk_offset;
661 ++numSplitReqs;
662 }
663
664 // Create a request and the packet containing request
1/*
2 * Copyright (c) 2013 - 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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657 unsigned blk_size = owner.cacheLineSize();
658 Addr blk_offset = (node_ptr->physAddr & (Addr)(blk_size - 1));
659 if (!(blk_offset + node_ptr->size <= blk_size)) {
660 node_ptr->size = blk_size - blk_offset;
661 ++numSplitReqs;
662 }
663
664 // Create a request and the packet containing request
665 Request* req = new Request(node_ptr->physAddr, node_ptr->size,
666 node_ptr->flags, masterID, node_ptr->seqNum,
667 ContextID(0));
665 auto req = std::make_shared<Request>(
666 node_ptr->physAddr, node_ptr->size,
667 node_ptr->flags, masterID, node_ptr->seqNum,
668 ContextID(0));
669
668 req->setPC(node_ptr->pc);
669 // If virtual address is valid, set the asid and virtual address fields
670 // of the request.
671 if (node_ptr->virtAddr != 0) {
672 req->setVirt(node_ptr->asid, node_ptr->virtAddr, node_ptr->size,
673 node_ptr->flags, masterID, node_ptr->pc);
674 req->setPaddr(node_ptr->physAddr);
675 req->setReqInstSeqNum(node_ptr->seqNum);

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1153}
1154
1155bool
1156TraceCPU::FixedRetryGen::send(Addr addr, unsigned size, const MemCmd& cmd,
1157 Request::FlagsType flags, Addr pc)
1158{
1159
1160 // Create new request
670 req->setPC(node_ptr->pc);
671 // If virtual address is valid, set the asid and virtual address fields
672 // of the request.
673 if (node_ptr->virtAddr != 0) {
674 req->setVirt(node_ptr->asid, node_ptr->virtAddr, node_ptr->size,
675 node_ptr->flags, masterID, node_ptr->pc);
676 req->setPaddr(node_ptr->physAddr);
677 req->setReqInstSeqNum(node_ptr->seqNum);

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1155}
1156
1157bool
1158TraceCPU::FixedRetryGen::send(Addr addr, unsigned size, const MemCmd& cmd,
1159 Request::FlagsType flags, Addr pc)
1160{
1161
1162 // Create new request
1161 Request* req = new Request(addr, size, flags, masterID);
1163 auto req = std::make_shared<Request>(addr, size, flags, masterID);
1162 req->setPC(pc);
1163
1164 // If this is not done it triggers assert in L1 cache for invalid contextId
1165 req->setContext(ContextID(0));
1166
1167 // Embed it in a packet
1168 PacketPtr pkt = new Packet(req, cmd);
1169

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1219 }
1220
1221}
1222
1223bool
1224TraceCPU::IcachePort::recvTimingResp(PacketPtr pkt)
1225{
1226 // All responses on the instruction fetch side are ignored. Simply delete
1164 req->setPC(pc);
1165
1166 // If this is not done it triggers assert in L1 cache for invalid contextId
1167 req->setContext(ContextID(0));
1168
1169 // Embed it in a packet
1170 PacketPtr pkt = new Packet(req, cmd);
1171

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1221 }
1222
1223}
1224
1225bool
1226TraceCPU::IcachePort::recvTimingResp(PacketPtr pkt)
1227{
1228 // All responses on the instruction fetch side are ignored. Simply delete
1227 // the request and packet to free allocated memory
1228 delete pkt->req;
1229 // the packet to free allocated memory
1229 delete pkt;
1230
1231 return true;
1232}
1233
1234void
1235TraceCPU::IcachePort::recvReqRetry()
1236{

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1245}
1246
1247bool
1248TraceCPU::DcachePort::recvTimingResp(PacketPtr pkt)
1249{
1250 // Handle the responses for data memory requests which is done inside the
1251 // elastic data generator
1252 owner->dcacheRecvTimingResp(pkt);
1230 delete pkt;
1231
1232 return true;
1233}
1234
1235void
1236TraceCPU::IcachePort::recvReqRetry()
1237{

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1246}
1247
1248bool
1249TraceCPU::DcachePort::recvTimingResp(PacketPtr pkt)
1250{
1251 // Handle the responses for data memory requests which is done inside the
1252 // elastic data generator
1253 owner->dcacheRecvTimingResp(pkt);
1253 // After processing the response delete the request and packet to free
1254 // After processing the response delete the packet to free
1254 // memory
1255 // memory
1255 delete pkt->req;
1256 delete pkt;
1257
1258 return true;
1259}
1260
1261void
1262TraceCPU::DcachePort::recvReqRetry()
1263{

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1257
1258 return true;
1259}
1260
1261void
1262TraceCPU::DcachePort::recvReqRetry()
1263{

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