trace_cpu.cc (11252:18bb597fc40c) trace_cpu.cc (11253:daf9f91b11e9)
1/*
2 * Copyright (c) 2013 - 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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592 dataLastTick = curTick();
593 }
594}
595
596PacketPtr
597TraceCPU::ElasticDataGen::executeMemReq(GraphNode* node_ptr)
598{
599
1/*
2 * Copyright (c) 2013 - 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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592 dataLastTick = curTick();
593 }
594}
595
596PacketPtr
597TraceCPU::ElasticDataGen::executeMemReq(GraphNode* node_ptr)
598{
599
600 DPRINTF(TraceCPUData, "Executing memory request %lli (addr %d, pc %#x, "
601 "size %d, flags %d).\n", node_ptr->seqNum, node_ptr->addr,
600 DPRINTF(TraceCPUData, "Executing memory request %lli (phys addr %d, "
601 "virt addr %d, pc %#x, size %d, flags %d).\n",
602 node_ptr->seqNum, node_ptr->physAddr, node_ptr->virtAddr,
602 node_ptr->pc, node_ptr->size, node_ptr->flags);
603
604 // If the request is strictly ordered, do not send it. Just return nullptr
605 // as if it was succesfully sent.
606 if (node_ptr->isStrictlyOrdered()) {
607 node_ptr->isLoad() ? ++numSOLoads : ++numSOStores;
608 DPRINTF(TraceCPUData, "Skipping strictly ordered request %lli.\n",
609 node_ptr->seqNum);
610 return nullptr;
611 }
612
613 // Check if the request spans two cache lines as this condition triggers
614 // an assert fail in the L1 cache. If it does then truncate the size to
615 // access only until the end of that line and ignore the remainder. The
616 // stat counting this is useful to keep a check on how frequently this
617 // happens. If required the code could be revised to mimick splitting such
618 // a request into two.
619 unsigned blk_size = owner.cacheLineSize();
603 node_ptr->pc, node_ptr->size, node_ptr->flags);
604
605 // If the request is strictly ordered, do not send it. Just return nullptr
606 // as if it was succesfully sent.
607 if (node_ptr->isStrictlyOrdered()) {
608 node_ptr->isLoad() ? ++numSOLoads : ++numSOStores;
609 DPRINTF(TraceCPUData, "Skipping strictly ordered request %lli.\n",
610 node_ptr->seqNum);
611 return nullptr;
612 }
613
614 // Check if the request spans two cache lines as this condition triggers
615 // an assert fail in the L1 cache. If it does then truncate the size to
616 // access only until the end of that line and ignore the remainder. The
617 // stat counting this is useful to keep a check on how frequently this
618 // happens. If required the code could be revised to mimick splitting such
619 // a request into two.
620 unsigned blk_size = owner.cacheLineSize();
620 Addr blk_offset = (node_ptr->addr & (Addr)(blk_size - 1));
621 Addr blk_offset = (node_ptr->physAddr & (Addr)(blk_size - 1));
621 if (!(blk_offset + node_ptr->size <= blk_size)) {
622 node_ptr->size = blk_size - blk_offset;
623 ++numSplitReqs;
624 }
625
626 // Create a request and the packet containing request
622 if (!(blk_offset + node_ptr->size <= blk_size)) {
623 node_ptr->size = blk_size - blk_offset;
624 ++numSplitReqs;
625 }
626
627 // Create a request and the packet containing request
627 Request* req = new Request(node_ptr->addr, node_ptr->size, node_ptr->flags,
628 masterID, node_ptr->seqNum,
628 Request* req = new Request(node_ptr->physAddr, node_ptr->size,
629 node_ptr->flags, masterID, node_ptr->seqNum,
629 ContextID(0), ThreadID(0));
630 req->setPC(node_ptr->pc);
630 ContextID(0), ThreadID(0));
631 req->setPC(node_ptr->pc);
632 // If virtual address is valid, set the asid and virtual address fields
633 // of the request.
634 if (node_ptr->virtAddr != 0) {
635 req->setVirt(node_ptr->asid, node_ptr->virtAddr, node_ptr->size,
636 node_ptr->flags, masterID, node_ptr->pc);
637 req->setPaddr(node_ptr->physAddr);
638 req->setReqInstSeqNum(node_ptr->seqNum);
639 }
640
631 PacketPtr pkt;
632 uint8_t* pkt_data = new uint8_t[req->getSize()];
633 if (node_ptr->isLoad()) {
634 pkt = Packet::createRead(req);
635 } else {
636 pkt = Packet::createWrite(req);
637 memset(pkt_data, 0xA, req->getSize());
638 }

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1272 }
1273 if (!duplicate) {
1274 element->regDep[element->numRegDep] = pkt_msg.reg_dep(i);
1275 element->numRegDep += 1;
1276 }
1277 }
1278
1279 // Optional fields
641 PacketPtr pkt;
642 uint8_t* pkt_data = new uint8_t[req->getSize()];
643 if (node_ptr->isLoad()) {
644 pkt = Packet::createRead(req);
645 } else {
646 pkt = Packet::createWrite(req);
647 memset(pkt_data, 0xA, req->getSize());
648 }

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1282 }
1283 if (!duplicate) {
1284 element->regDep[element->numRegDep] = pkt_msg.reg_dep(i);
1285 element->numRegDep += 1;
1286 }
1287 }
1288
1289 // Optional fields
1280 if (pkt_msg.has_addr())
1281 element->addr = pkt_msg.addr();
1290 if (pkt_msg.has_p_addr())
1291 element->physAddr = pkt_msg.p_addr();
1282 else
1292 else
1283 element->addr = 0;
1293 element->physAddr = 0;
1284
1294
1295 if (pkt_msg.has_v_addr())
1296 element->virtAddr = pkt_msg.v_addr();
1297 else
1298 element->virtAddr = 0;
1299
1300 if (pkt_msg.has_asid())
1301 element->asid = pkt_msg.asid();
1302 else
1303 element->asid = 0;
1304
1285 if (pkt_msg.has_size())
1286 element->size = pkt_msg.size();
1287 else
1288 element->size = 0;
1289
1290 if (pkt_msg.has_flags())
1291 element->flags = pkt_msg.flags();
1292 else

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1378}
1379
1380void
1381TraceCPU::ElasticDataGen::GraphNode::writeElementAsTrace() const
1382{
1383 DPRINTFR(TraceCPUData, "%lli", seqNum);
1384 DPRINTFR(TraceCPUData, ",%s", typeToStr());
1385 if (isLoad() || isStore()) {
1305 if (pkt_msg.has_size())
1306 element->size = pkt_msg.size();
1307 else
1308 element->size = 0;
1309
1310 if (pkt_msg.has_flags())
1311 element->flags = pkt_msg.flags();
1312 else

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1398}
1399
1400void
1401TraceCPU::ElasticDataGen::GraphNode::writeElementAsTrace() const
1402{
1403 DPRINTFR(TraceCPUData, "%lli", seqNum);
1404 DPRINTFR(TraceCPUData, ",%s", typeToStr());
1405 if (isLoad() || isStore()) {
1386 DPRINTFR(TraceCPUData, ",%i", addr);
1406 DPRINTFR(TraceCPUData, ",%i", physAddr);
1387 DPRINTFR(TraceCPUData, ",%i", size);
1388 DPRINTFR(TraceCPUData, ",%i", flags);
1389 }
1390 DPRINTFR(TraceCPUData, ",%lli", compDelay);
1391 int i = 0;
1392 DPRINTFR(TraceCPUData, "robDep:");
1393 while (robDep[i] != 0) {
1394 DPRINTFR(TraceCPUData, ",%lli", robDep[i]);

--- 62 unchanged lines hidden --- 		1407 DPRINTFR(TraceCPUData, ",%i", size);
1408 DPRINTFR(TraceCPUData, ",%i", flags);
1409 }
1410 DPRINTFR(TraceCPUData, ",%lli", compDelay);
1411 int i = 0;
1412 DPRINTFR(TraceCPUData, "robDep:");
1413 while (robDep[i] != 0) {
1414 DPRINTFR(TraceCPUData, ",%lli", robDep[i]);

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