1/* 2 * Copyright (c) 2013 - 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 648 unchanged lines hidden (view full) --- 657 unsigned blk_size = owner.cacheLineSize(); 658 Addr blk_offset = (node_ptr->physAddr & (Addr)(blk_size - 1)); 659 if (!(blk_offset + node_ptr->size <= blk_size)) { 660 node_ptr->size = blk_size - blk_offset; 661 ++numSplitReqs; 662 } 663 664 // Create a request and the packet containing request |
665 auto req = std::make_shared<Request>( 666 node_ptr->physAddr, node_ptr->size, 667 node_ptr->flags, masterID, node_ptr->seqNum, 668 ContextID(0)); 669 |
670 req->setPC(node_ptr->pc); 671 // If virtual address is valid, set the asid and virtual address fields 672 // of the request. 673 if (node_ptr->virtAddr != 0) { 674 req->setVirt(node_ptr->asid, node_ptr->virtAddr, node_ptr->size, 675 node_ptr->flags, masterID, node_ptr->pc); 676 req->setPaddr(node_ptr->physAddr); 677 req->setReqInstSeqNum(node_ptr->seqNum); --- 477 unchanged lines hidden (view full) --- 1155} 1156 1157bool 1158TraceCPU::FixedRetryGen::send(Addr addr, unsigned size, const MemCmd& cmd, 1159 Request::FlagsType flags, Addr pc) 1160{ 1161 1162 // Create new request |
1163 auto req = std::make_shared<Request>(addr, size, flags, masterID); |
1164 req->setPC(pc); 1165 1166 // If this is not done it triggers assert in L1 cache for invalid contextId 1167 req->setContext(ContextID(0)); 1168 1169 // Embed it in a packet 1170 PacketPtr pkt = new Packet(req, cmd); 1171 --- 49 unchanged lines hidden (view full) --- 1221 } 1222 1223} 1224 1225bool 1226TraceCPU::IcachePort::recvTimingResp(PacketPtr pkt) 1227{ 1228 // All responses on the instruction fetch side are ignored. Simply delete |
1229 // the packet to free allocated memory |
1230 delete pkt; 1231 1232 return true; 1233} 1234 1235void 1236TraceCPU::IcachePort::recvReqRetry() 1237{ --- 8 unchanged lines hidden (view full) --- 1246} 1247 1248bool 1249TraceCPU::DcachePort::recvTimingResp(PacketPtr pkt) 1250{ 1251 // Handle the responses for data memory requests which is done inside the 1252 // elastic data generator 1253 owner->dcacheRecvTimingResp(pkt); |
1254 // After processing the response delete the packet to free |
1255 // memory |
1256 delete pkt; 1257 1258 return true; 1259} 1260 1261void 1262TraceCPU::DcachePort::recvReqRetry() 1263{ --- 256 unchanged lines hidden --- |