1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_THREAD_STATE_HH__
32#define __CPU_THREAD_STATE_HH__
33
34#include "arch/types.hh"
35#include "cpu/profile.hh"
36#include "cpu/thread_context.hh"
37
38#if !FULL_SYSTEM
39#include "mem/mem_object.hh"
40#include "sim/process.hh"
41#endif
42
43#if FULL_SYSTEM
44class EndQuiesceEvent;
45class FunctionProfile;
46class ProfileNode;
47namespace TheISA {
48 namespace Kernel {
49 class Statistics;
50 };
51};
52#endif
53
54class BaseCPU;
55class Checkpoint;
56class Port;
57class TranslatingPort;
58
59/**
60 * Struct for holding general thread state that is needed across CPU
61 * models. This includes things such as pointers to the process,
62 * memory, quiesce events, and certain stats. This can be expanded
63 * to hold more thread-specific stats within it.
64 */
65struct ThreadState {
66 typedef ThreadContext::Status Status;
67
68#if FULL_SYSTEM
69 ThreadState(BaseCPU *cpu, int _cpuId, int _tid);
70#else
71 ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
72 short _asid);
73#endif
74
75 ~ThreadState();
76
77 void serialize(std::ostream &os);
78
79 void unserialize(Checkpoint *cp, const std::string §ion);
80
81 void setCpuId(int id) { cpuId = id; }
82
83 int readCpuId() { return cpuId; }
84
85 void setTid(int id) { tid = id; }
86
87 int readTid() { return tid; }
88
89 Tick readLastActivate() { return lastActivate; }
90
91 Tick readLastSuspend() { return lastSuspend; }
92
93#if FULL_SYSTEM
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_THREAD_STATE_HH__
32#define __CPU_THREAD_STATE_HH__
33
34#include "arch/types.hh"
35#include "cpu/profile.hh"
36#include "cpu/thread_context.hh"
37
38#if !FULL_SYSTEM
39#include "mem/mem_object.hh"
40#include "sim/process.hh"
41#endif
42
43#if FULL_SYSTEM
44class EndQuiesceEvent;
45class FunctionProfile;
46class ProfileNode;
47namespace TheISA {
48 namespace Kernel {
49 class Statistics;
50 };
51};
52#endif
53
54class BaseCPU;
55class Checkpoint;
56class Port;
57class TranslatingPort;
58
59/**
60 * Struct for holding general thread state that is needed across CPU
61 * models. This includes things such as pointers to the process,
62 * memory, quiesce events, and certain stats. This can be expanded
63 * to hold more thread-specific stats within it.
64 */
65struct ThreadState {
66 typedef ThreadContext::Status Status;
67
68#if FULL_SYSTEM
69 ThreadState(BaseCPU *cpu, int _cpuId, int _tid);
70#else
71 ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
72 short _asid);
73#endif
74
75 ~ThreadState();
76
77 void serialize(std::ostream &os);
78
79 void unserialize(Checkpoint *cp, const std::string §ion);
80
81 void setCpuId(int id) { cpuId = id; }
82
83 int readCpuId() { return cpuId; }
84
85 void setTid(int id) { tid = id; }
86
87 int readTid() { return tid; }
88
89 Tick readLastActivate() { return lastActivate; }
90
91 Tick readLastSuspend() { return lastSuspend; }
92
93#if FULL_SYSTEM
|
99
100 void dumpFuncProfile();
101
102 EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
103
104 void profileClear();
105
106 void profileSample();
107
108 TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; }
109
110 FunctionalPort *getPhysPort() { return physPort; }
111
112 void setPhysPort(FunctionalPort *port) { physPort = port; }
113
114 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; }
115
116 void setVirtPort(VirtualPort *port) { virtPort = port; }
117#else
118 Process *getProcessPtr() { return process; }
119
120 TranslatingPort *getMemPort();
121
122 void setMemPort(TranslatingPort *_port) { port = _port; }
123
124 int getInstAsid() { return asid; }
125 int getDataAsid() { return asid; }
126#endif
127
128 /** Sets the current instruction being committed. */
129 void setInst(TheISA::MachInst _inst) { inst = _inst; }
130
131 /** Returns the current instruction being committed. */
132 TheISA::MachInst getInst() { return inst; }
133
134 /** Reads the number of instructions functionally executed and
135 * committed.
136 */
137 Counter readFuncExeInst() { return funcExeInst; }
138
139 /** Sets the total number of instructions functionally executed
140 * and committed.
141 */
142 void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
143
144 /** Returns the status of this thread. */
145 Status status() const { return _status; }
146
147 /** Sets the status of this thread. */
148 void setStatus(Status new_status) { _status = new_status; }
149
150 public:
151 /** Connects port to the functional port of the memory object
152 * below the CPU. */
153 void connectToMemFunc(Port *port);
154
155 /** Number of instructions committed. */
156 Counter numInst;
157 /** Stat for number instructions committed. */
158 Stats::Scalar<> numInsts;
159 /** Stat for number of memory references. */
160 Stats::Scalar<> numMemRefs;
161
162 /** Number of simulated loads, used for tracking events based on
163 * the number of loads committed.
164 */
165 Counter numLoad;
166
167 /** The number of simulated loads committed prior to this run. */
168 Counter startNumLoad;
169
170 protected:
171 ThreadContext::Status _status;
172
173 // Pointer to the base CPU.
174 BaseCPU *baseCpu;
175
176 // ID of this context w.r.t. the System or Process object to which
177 // it belongs. For full-system mode, this is the system CPU ID.
178 int cpuId;
179
180 // Index of hardware thread context on the CPU that this represents.
181 int tid;
182
183 public:
184 /** Last time activate was called on this thread. */
185 Tick lastActivate;
186
187 /** Last time suspend was called on this thread. */
188 Tick lastSuspend;
189
190#if FULL_SYSTEM
191 public:
192 FunctionProfile *profile;
193 ProfileNode *profileNode;
194 Addr profilePC;
195 EndQuiesceEvent *quiesceEvent;
196
197 TheISA::Kernel::Statistics *kernelStats;
198 protected:
199 /** A functional port outgoing only for functional accesses to physical
200 * addresses.*/
201 FunctionalPort *physPort;
202
203 /** A functional port, outgoing only, for functional accesse to virtual
204 * addresses. That doen't require execution context information */
205 VirtualPort *virtPort;
206#else
207 TranslatingPort *port;
208
209 Process *process;
210
211 // Address space ID. Note that this is used for TIMING cache
212 // simulation only; all functional memory accesses should use
213 // one of the FunctionalMemory pointers above.
214 short asid;
215
216#endif
217
218 /** Current instruction the thread is committing. Only set and
219 * used for DTB faults currently.
220 */
221 TheISA::MachInst inst;
222
223 /** The current microcode pc for the currently executing macro
224 * operation.
225 */
226 MicroPC microPC;
227
228 /** The next microcode pc for the currently executing macro
229 * operation.
230 */
231 MicroPC nextMicroPC;
232
233 public:
234 /**
235 * Temporary storage to pass the source address from copy_load to
236 * copy_store.
237 * @todo Remove this temporary when we have a better way to do it.
238 */
239 Addr copySrcAddr;
240 /**
241 * Temp storage for the physical source address of a copy.
242 * @todo Remove this temporary when we have a better way to do it.
243 */
244 Addr copySrcPhysAddr;
245
246 /*
247 * number of executed instructions, for matching with syscall trace
248 * points in EIO files.
249 */
250 Counter funcExeInst;
251
252 //
253 // Count failed store conditionals so we can warn of apparent
254 // application deadlock situations.
255 unsigned storeCondFailures;
256};
257
258#endif // __CPU_THREAD_STATE_HH__
| 99
100 void dumpFuncProfile();
101
102 EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
103
104 void profileClear();
105
106 void profileSample();
107
108 TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; }
109
110 FunctionalPort *getPhysPort() { return physPort; }
111
112 void setPhysPort(FunctionalPort *port) { physPort = port; }
113
114 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; }
115
116 void setVirtPort(VirtualPort *port) { virtPort = port; }
117#else
118 Process *getProcessPtr() { return process; }
119
120 TranslatingPort *getMemPort();
121
122 void setMemPort(TranslatingPort *_port) { port = _port; }
123
124 int getInstAsid() { return asid; }
125 int getDataAsid() { return asid; }
126#endif
127
128 /** Sets the current instruction being committed. */
129 void setInst(TheISA::MachInst _inst) { inst = _inst; }
130
131 /** Returns the current instruction being committed. */
132 TheISA::MachInst getInst() { return inst; }
133
134 /** Reads the number of instructions functionally executed and
135 * committed.
136 */
137 Counter readFuncExeInst() { return funcExeInst; }
138
139 /** Sets the total number of instructions functionally executed
140 * and committed.
141 */
142 void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
143
144 /** Returns the status of this thread. */
145 Status status() const { return _status; }
146
147 /** Sets the status of this thread. */
148 void setStatus(Status new_status) { _status = new_status; }
149
150 public:
151 /** Connects port to the functional port of the memory object
152 * below the CPU. */
153 void connectToMemFunc(Port *port);
154
155 /** Number of instructions committed. */
156 Counter numInst;
157 /** Stat for number instructions committed. */
158 Stats::Scalar<> numInsts;
159 /** Stat for number of memory references. */
160 Stats::Scalar<> numMemRefs;
161
162 /** Number of simulated loads, used for tracking events based on
163 * the number of loads committed.
164 */
165 Counter numLoad;
166
167 /** The number of simulated loads committed prior to this run. */
168 Counter startNumLoad;
169
170 protected:
171 ThreadContext::Status _status;
172
173 // Pointer to the base CPU.
174 BaseCPU *baseCpu;
175
176 // ID of this context w.r.t. the System or Process object to which
177 // it belongs. For full-system mode, this is the system CPU ID.
178 int cpuId;
179
180 // Index of hardware thread context on the CPU that this represents.
181 int tid;
182
183 public:
184 /** Last time activate was called on this thread. */
185 Tick lastActivate;
186
187 /** Last time suspend was called on this thread. */
188 Tick lastSuspend;
189
190#if FULL_SYSTEM
191 public:
192 FunctionProfile *profile;
193 ProfileNode *profileNode;
194 Addr profilePC;
195 EndQuiesceEvent *quiesceEvent;
196
197 TheISA::Kernel::Statistics *kernelStats;
198 protected:
199 /** A functional port outgoing only for functional accesses to physical
200 * addresses.*/
201 FunctionalPort *physPort;
202
203 /** A functional port, outgoing only, for functional accesse to virtual
204 * addresses. That doen't require execution context information */
205 VirtualPort *virtPort;
206#else
207 TranslatingPort *port;
208
209 Process *process;
210
211 // Address space ID. Note that this is used for TIMING cache
212 // simulation only; all functional memory accesses should use
213 // one of the FunctionalMemory pointers above.
214 short asid;
215
216#endif
217
218 /** Current instruction the thread is committing. Only set and
219 * used for DTB faults currently.
220 */
221 TheISA::MachInst inst;
222
223 /** The current microcode pc for the currently executing macro
224 * operation.
225 */
226 MicroPC microPC;
227
228 /** The next microcode pc for the currently executing macro
229 * operation.
230 */
231 MicroPC nextMicroPC;
232
233 public:
234 /**
235 * Temporary storage to pass the source address from copy_load to
236 * copy_store.
237 * @todo Remove this temporary when we have a better way to do it.
238 */
239 Addr copySrcAddr;
240 /**
241 * Temp storage for the physical source address of a copy.
242 * @todo Remove this temporary when we have a better way to do it.
243 */
244 Addr copySrcPhysAddr;
245
246 /*
247 * number of executed instructions, for matching with syscall trace
248 * points in EIO files.
249 */
250 Counter funcExeInst;
251
252 //
253 // Count failed store conditionals so we can warn of apparent
254 // application deadlock situations.
255 unsigned storeCondFailures;
256};
257
258#endif // __CPU_THREAD_STATE_HH__
|