1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_THREAD_STATE_HH__
32#define __CPU_THREAD_STATE_HH__
33
34#include "arch/types.hh"
35#include "cpu/profile.hh"
36#include "cpu/thread_context.hh"
37
38#if !FULL_SYSTEM
39#include "mem/mem_object.hh"
40#include "sim/process.hh"
41#endif
42
43#if FULL_SYSTEM
44class EndQuiesceEvent;
45class FunctionProfile;
46class ProfileNode;
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_THREAD_STATE_HH__
32#define __CPU_THREAD_STATE_HH__
33
34#include "arch/types.hh"
35#include "cpu/profile.hh"
36#include "cpu/thread_context.hh"
37
38#if !FULL_SYSTEM
39#include "mem/mem_object.hh"
40#include "sim/process.hh"
41#endif
42
43#if FULL_SYSTEM
44class EndQuiesceEvent;
45class FunctionProfile;
46class ProfileNode;
|
47namespace Kernel {
48 class Statistics;
| 47namespace TheISA {
48 namespace Kernel {
49 class Statistics;
50 };
|
49};
50#endif
51
52class BaseCPU;
53class Checkpoint;
54class Port;
55class TranslatingPort;
56
57/**
58 * Struct for holding general thread state that is needed across CPU
59 * models. This includes things such as pointers to the process,
60 * memory, quiesce events, and certain stats. This can be expanded
61 * to hold more thread-specific stats within it.
62 */
63struct ThreadState {
64 typedef ThreadContext::Status Status;
65
66#if FULL_SYSTEM
67 ThreadState(BaseCPU *cpu, int _cpuId, int _tid);
68#else
69 ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
70 short _asid);
71#endif
72
73 ~ThreadState();
74
75 void serialize(std::ostream &os);
76
77 void unserialize(Checkpoint *cp, const std::string §ion);
78
79 void setCpuId(int id) { cpuId = id; }
80
81 int readCpuId() { return cpuId; }
82
83 void setTid(int id) { tid = id; }
84
85 int readTid() { return tid; }
86
87 Tick readLastActivate() { return lastActivate; }
88
89 Tick readLastSuspend() { return lastSuspend; }
90
91#if FULL_SYSTEM
92 void dumpFuncProfile();
93
94 EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
95
96 void profileClear();
97
98 void profileSample();
99
| 51};
52#endif
53
54class BaseCPU;
55class Checkpoint;
56class Port;
57class TranslatingPort;
58
59/**
60 * Struct for holding general thread state that is needed across CPU
61 * models. This includes things such as pointers to the process,
62 * memory, quiesce events, and certain stats. This can be expanded
63 * to hold more thread-specific stats within it.
64 */
65struct ThreadState {
66 typedef ThreadContext::Status Status;
67
68#if FULL_SYSTEM
69 ThreadState(BaseCPU *cpu, int _cpuId, int _tid);
70#else
71 ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
72 short _asid);
73#endif
74
75 ~ThreadState();
76
77 void serialize(std::ostream &os);
78
79 void unserialize(Checkpoint *cp, const std::string §ion);
80
81 void setCpuId(int id) { cpuId = id; }
82
83 int readCpuId() { return cpuId; }
84
85 void setTid(int id) { tid = id; }
86
87 int readTid() { return tid; }
88
89 Tick readLastActivate() { return lastActivate; }
90
91 Tick readLastSuspend() { return lastSuspend; }
92
93#if FULL_SYSTEM
94 void dumpFuncProfile();
95
96 EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
97
98 void profileClear();
99
100 void profileSample();
101
|
100 Kernel::Statistics *getKernelStats() { return kernelStats; }
| 102 TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; }
|
101
102 FunctionalPort *getPhysPort() { return physPort; }
103
104 void setPhysPort(FunctionalPort *port) { physPort = port; }
105
106 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; }
107
108 void setVirtPort(VirtualPort *port) { virtPort = port; }
109#else
110 Process *getProcessPtr() { return process; }
111
112 TranslatingPort *getMemPort();
113
114 void setMemPort(TranslatingPort *_port) { port = _port; }
115
116 int getInstAsid() { return asid; }
117 int getDataAsid() { return asid; }
118#endif
119
120 /** Sets the current instruction being committed. */
121 void setInst(TheISA::MachInst _inst) { inst = _inst; }
122
123 /** Returns the current instruction being committed. */
124 TheISA::MachInst getInst() { return inst; }
125
126 /** Reads the number of instructions functionally executed and
127 * committed.
128 */
129 Counter readFuncExeInst() { return funcExeInst; }
130
131 /** Sets the total number of instructions functionally executed
132 * and committed.
133 */
134 void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
135
136 /** Returns the status of this thread. */
137 Status status() const { return _status; }
138
139 /** Sets the status of this thread. */
140 void setStatus(Status new_status) { _status = new_status; }
141
142 protected:
143 /** Gets a functional port from the memory object that's connected
144 * to the CPU. */
145 Port *getMemFuncPort();
146
147 public:
148 /** Number of instructions committed. */
149 Counter numInst;
150 /** Stat for number instructions committed. */
151 Stats::Scalar<> numInsts;
152 /** Stat for number of memory references. */
153 Stats::Scalar<> numMemRefs;
154
155 /** Number of simulated loads, used for tracking events based on
156 * the number of loads committed.
157 */
158 Counter numLoad;
159
160 /** The number of simulated loads committed prior to this run. */
161 Counter startNumLoad;
162
163 protected:
164 ThreadContext::Status _status;
165
166 // Pointer to the base CPU.
167 BaseCPU *baseCpu;
168
169 // ID of this context w.r.t. the System or Process object to which
170 // it belongs. For full-system mode, this is the system CPU ID.
171 int cpuId;
172
173 // Index of hardware thread context on the CPU that this represents.
174 int tid;
175
176 public:
177 /** Last time activate was called on this thread. */
178 Tick lastActivate;
179
180 /** Last time suspend was called on this thread. */
181 Tick lastSuspend;
182
183#if FULL_SYSTEM
184 public:
185 FunctionProfile *profile;
186 ProfileNode *profileNode;
187 Addr profilePC;
188 EndQuiesceEvent *quiesceEvent;
189
| 103
104 FunctionalPort *getPhysPort() { return physPort; }
105
106 void setPhysPort(FunctionalPort *port) { physPort = port; }
107
108 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; }
109
110 void setVirtPort(VirtualPort *port) { virtPort = port; }
111#else
112 Process *getProcessPtr() { return process; }
113
114 TranslatingPort *getMemPort();
115
116 void setMemPort(TranslatingPort *_port) { port = _port; }
117
118 int getInstAsid() { return asid; }
119 int getDataAsid() { return asid; }
120#endif
121
122 /** Sets the current instruction being committed. */
123 void setInst(TheISA::MachInst _inst) { inst = _inst; }
124
125 /** Returns the current instruction being committed. */
126 TheISA::MachInst getInst() { return inst; }
127
128 /** Reads the number of instructions functionally executed and
129 * committed.
130 */
131 Counter readFuncExeInst() { return funcExeInst; }
132
133 /** Sets the total number of instructions functionally executed
134 * and committed.
135 */
136 void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
137
138 /** Returns the status of this thread. */
139 Status status() const { return _status; }
140
141 /** Sets the status of this thread. */
142 void setStatus(Status new_status) { _status = new_status; }
143
144 protected:
145 /** Gets a functional port from the memory object that's connected
146 * to the CPU. */
147 Port *getMemFuncPort();
148
149 public:
150 /** Number of instructions committed. */
151 Counter numInst;
152 /** Stat for number instructions committed. */
153 Stats::Scalar<> numInsts;
154 /** Stat for number of memory references. */
155 Stats::Scalar<> numMemRefs;
156
157 /** Number of simulated loads, used for tracking events based on
158 * the number of loads committed.
159 */
160 Counter numLoad;
161
162 /** The number of simulated loads committed prior to this run. */
163 Counter startNumLoad;
164
165 protected:
166 ThreadContext::Status _status;
167
168 // Pointer to the base CPU.
169 BaseCPU *baseCpu;
170
171 // ID of this context w.r.t. the System or Process object to which
172 // it belongs. For full-system mode, this is the system CPU ID.
173 int cpuId;
174
175 // Index of hardware thread context on the CPU that this represents.
176 int tid;
177
178 public:
179 /** Last time activate was called on this thread. */
180 Tick lastActivate;
181
182 /** Last time suspend was called on this thread. */
183 Tick lastSuspend;
184
185#if FULL_SYSTEM
186 public:
187 FunctionProfile *profile;
188 ProfileNode *profileNode;
189 Addr profilePC;
190 EndQuiesceEvent *quiesceEvent;
191
|
190 Kernel::Statistics *kernelStats;
| 192 TheISA::Kernel::Statistics *kernelStats;
|
191 protected:
192 /** A functional port outgoing only for functional accesses to physical
193 * addresses.*/
194 FunctionalPort *physPort;
195
196 /** A functional port, outgoing only, for functional accesse to virtual
197 * addresses. That doen't require execution context information */
198 VirtualPort *virtPort;
199#else
200 TranslatingPort *port;
201
202 Process *process;
203
204 // Address space ID. Note that this is used for TIMING cache
205 // simulation only; all functional memory accesses should use
206 // one of the FunctionalMemory pointers above.
207 short asid;
208
209#endif
210
211 /** Current instruction the thread is committing. Only set and
212 * used for DTB faults currently.
213 */
214 TheISA::MachInst inst;
215
216 /** The current microcode pc for the currently executing macro
217 * operation.
218 */
219 MicroPC microPC;
220
221 /** The next microcode pc for the currently executing macro
222 * operation.
223 */
224 MicroPC nextMicroPC;
225
226 public:
227 /**
228 * Temporary storage to pass the source address from copy_load to
229 * copy_store.
230 * @todo Remove this temporary when we have a better way to do it.
231 */
232 Addr copySrcAddr;
233 /**
234 * Temp storage for the physical source address of a copy.
235 * @todo Remove this temporary when we have a better way to do it.
236 */
237 Addr copySrcPhysAddr;
238
239 /*
240 * number of executed instructions, for matching with syscall trace
241 * points in EIO files.
242 */
243 Counter funcExeInst;
244
245 //
246 // Count failed store conditionals so we can warn of apparent
247 // application deadlock situations.
248 unsigned storeCondFailures;
249};
250
251#endif // __CPU_THREAD_STATE_HH__
| 193 protected:
194 /** A functional port outgoing only for functional accesses to physical
195 * addresses.*/
196 FunctionalPort *physPort;
197
198 /** A functional port, outgoing only, for functional accesse to virtual
199 * addresses. That doen't require execution context information */
200 VirtualPort *virtPort;
201#else
202 TranslatingPort *port;
203
204 Process *process;
205
206 // Address space ID. Note that this is used for TIMING cache
207 // simulation only; all functional memory accesses should use
208 // one of the FunctionalMemory pointers above.
209 short asid;
210
211#endif
212
213 /** Current instruction the thread is committing. Only set and
214 * used for DTB faults currently.
215 */
216 TheISA::MachInst inst;
217
218 /** The current microcode pc for the currently executing macro
219 * operation.
220 */
221 MicroPC microPC;
222
223 /** The next microcode pc for the currently executing macro
224 * operation.
225 */
226 MicroPC nextMicroPC;
227
228 public:
229 /**
230 * Temporary storage to pass the source address from copy_load to
231 * copy_store.
232 * @todo Remove this temporary when we have a better way to do it.
233 */
234 Addr copySrcAddr;
235 /**
236 * Temp storage for the physical source address of a copy.
237 * @todo Remove this temporary when we have a better way to do it.
238 */
239 Addr copySrcPhysAddr;
240
241 /*
242 * number of executed instructions, for matching with syscall trace
243 * points in EIO files.
244 */
245 Counter funcExeInst;
246
247 //
248 // Count failed store conditionals so we can warn of apparent
249 // application deadlock situations.
250 unsigned storeCondFailures;
251};
252
253#endif // __CPU_THREAD_STATE_HH__
|