thread_state.cc (3280:91bfa4f79c53) | thread_state.cc (3402:db60546818d0) |
---|---|
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "base/output.hh" | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "base/output.hh" |
32#include "cpu/base.hh" |
|
32#include "cpu/profile.hh" 33#include "cpu/thread_state.hh" | 33#include "cpu/profile.hh" 34#include "cpu/thread_state.hh" |
35#include "mem/port.hh" 36#include "mem/translating_port.hh" |
|
34#include "sim/serialize.hh" 35 36#if FULL_SYSTEM 37#include "cpu/quiesce_event.hh" 38#include "kern/kernel_stats.hh" 39#endif 40 41#if FULL_SYSTEM | 37#include "sim/serialize.hh" 38 39#if FULL_SYSTEM 40#include "cpu/quiesce_event.hh" 41#include "kern/kernel_stats.hh" 42#endif 43 44#if FULL_SYSTEM |
42ThreadState::ThreadState(int _cpuId, int _tid) 43 : cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), | 45ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid) 46 : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), |
44 profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL), | 47 profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL), |
48 physPort(NULL), virtPort(NULL), |
|
45 microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) 46#else | 49 microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) 50#else |
47ThreadState::ThreadState(int _cpuId, int _tid, Process *_process, 48 short _asid, MemObject *mem) 49 : cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), 50 process(_process), asid(_asid), | 51ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process, 52 short _asid) 53 : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), 54 port(NULL), process(_process), asid(_asid), |
51 microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) 52#endif 53{ 54 numInst = 0; 55 numLoad = 0; 56} 57 58void --- 44 unchanged lines hidden (view full) --- 103 104void 105ThreadState::profileSample() 106{ 107 if (profile) 108 profile->sample(profileNode, profilePC); 109} 110 | 55 microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) 56#endif 57{ 58 numInst = 0; 59 numLoad = 0; 60} 61 62void --- 44 unchanged lines hidden (view full) --- 107 108void 109ThreadState::profileSample() 110{ 111 if (profile) 112 profile->sample(profileNode, profilePC); 113} 114 |
115#else 116TranslatingPort * 117ThreadState::getMemPort() 118{ 119 if (port != NULL) 120 return port; 121 122 /* Use this port to for syscall emulation writes to memory. */ 123 Port *dcache_port, *func_mem_port; 124 port = new TranslatingPort(csprintf("%s-%d-funcport", 125 baseCpu->name(), tid), 126 process->pTable, false); 127 128 dcache_port = baseCpu->getPort("dcache_port"); 129 assert(dcache_port != NULL); 130 131 MemObject *mem_object = dcache_port->getPeer()->getOwner(); 132 assert(mem_object != NULL); 133 134 func_mem_port = mem_object->getPort("functional"); 135 assert(func_mem_port != NULL); 136 137 func_mem_port->setPeer(port); 138 port->setPeer(func_mem_port); 139 140 return port; 141} |
|
111#endif | 142#endif |