1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 23 unchanged lines hidden (view full) --- 32#include "cpu/base.hh" 33#include "cpu/profile.hh" 34#include "cpu/thread_state.hh" 35#include "mem/port.hh" 36#include "mem/translating_port.hh" 37#include "sim/serialize.hh" 38 39#if FULL_SYSTEM |
40#include "arch/kernel_stats.hh" |
41#include "cpu/quiesce_event.hh" |
42#endif 43 44#if FULL_SYSTEM 45ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid) 46 : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), 47 profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL), 48 physPort(NULL), virtPort(NULL), 49 microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) --- 116 unchanged lines hidden --- |